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-Removed sbus and gio64 buses since they aren't up to his majesty AJR's bar of quality, nw

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This commit is contained in:
MooglyGuy 2019-05-29 19:15:27 +02:00
parent e0ff1d29a0
commit 3207d504fe
22 changed files with 1 additions and 7565 deletions
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39
scripts/src/bus.lua
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@ -967,21 +967,6 @@ if (BUSES["GAMATE"]~=null) then
end
---------------------------------------------------
--
--@src/devices/bus/gio64/gio64.h,BUSES["GIO64"] = true
---------------------------------------------------
if (BUSES["GIO64"]~=null) then
files {
MAME_DIR .. "src/devices/bus/gio64/gio64.cpp",
MAME_DIR .. "src/devices/bus/gio64/gio64.h",
MAME_DIR .. "src/devices/bus/gio64/newport.cpp",
MAME_DIR .. "src/devices/bus/gio64/newport.h",
}
end
---------------------------------------------------
--
--@src/devices/bus/hp_hil/hp_hil.h,BUSES["HPHIL"] = true
@ -3277,30 +3262,6 @@ if (BUSES["SUNMOUSE"]~=null) then
}
end
---------------------------------------------------
--
--@src/devices/bus/sbus/sbus.h,BUSES["SBUS"] = true
---------------------------------------------------
if (BUSES["SBUS"]~=null) then
files {
MAME_DIR .. "src/devices/bus/sbus/artecon.cpp",
MAME_DIR .. "src/devices/bus/sbus/artecon.h",
MAME_DIR .. "src/devices/bus/sbus/bwtwo.cpp",
MAME_DIR .. "src/devices/bus/sbus/bwtwo.h",
MAME_DIR .. "src/devices/bus/sbus/cgsix.cpp",
MAME_DIR .. "src/devices/bus/sbus/cgsix.h",
MAME_DIR .. "src/devices/bus/sbus/cgthree.cpp",
MAME_DIR .. "src/devices/bus/sbus/cgthree.h",
MAME_DIR .. "src/devices/bus/sbus/hme.cpp",
MAME_DIR .. "src/devices/bus/sbus/hme.h",
MAME_DIR .. "src/devices/bus/sbus/sunpc.cpp",
MAME_DIR .. "src/devices/bus/sbus/sunpc.h",
MAME_DIR .. "src/devices/bus/sbus/sbus.cpp",
MAME_DIR .. "src/devices/bus/sbus/sbus.h",
}
end
---------------------------------------------------
--
--@src/devices/bus/ql/exp.h,BUSES["QL"] = true

2
scripts/target/mame/mess.lua
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@ -758,7 +758,6 @@ BUSES["GAMEBOY"] = true
BUSES["GAMEGEAR"] = true
BUSES["GBA"] = true
BUSES["GENERIC"] = true
BUSES["GIO64"] = true
BUSES["HEXBUS"] = true
BUSES["HPHIL"] = true
BUSES["HPDIO"] = true
@ -810,7 +809,6 @@ BUSES["RS232"] = true
BUSES["S100"] = true
BUSES["SAT_CTRL"] = true
BUSES["SATURN"] = true
BUSES["SBUS"] = true
BUSES["SCSI"] = true
BUSES["SCV"] = true
BUSES["SEGA8"] = true

182
src/devices/bus/gio64/gio64.cpp
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@ -1,182 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
gio64.cpp - SGI GIO64 slot bus and GIO64 device emulation
***************************************************************************/
#include "emu.h"
// Display boards
#include "newport.h"
#include "gio64.h"
void gio64_cards(device_slot_interface &device)
{
device.option_add("xl8", GIO64_XL8); /* SGI 8-bit XL board */
device.option_add("xl24", GIO64_XL24); /* SGI 24-bit XL board */
}
DEFINE_DEVICE_TYPE(GIO64_SLOT, gio64_slot_device, "gio64_slot", "SGI GIO64 Slot")
gio64_slot_device::gio64_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: gio64_slot_device(mconfig, GIO64_SLOT, tag, owner, clock)
{
}
gio64_slot_device::gio64_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, type, tag, owner, clock)
, device_slot_interface(mconfig, *this)
, m_gio64(*this, finder_base::DUMMY_TAG)
{
}
void gio64_slot_device::device_validity_check(validity_checker &valid) const
{
device_t *const card(get_card_device());
if (card && !dynamic_cast<device_gio64_card_interface *>(card))
osd_printf_error("Card device %s (%s) does not implement device_gio64_card_interface\n", card->tag(), card->name());
}
void gio64_slot_device::device_resolve_objects()
{
device_gio64_card_interface *const gio64_card(dynamic_cast<device_gio64_card_interface *>(get_card_device()));
if (gio64_card)
gio64_card->set_gio64(m_gio64, tag());
}
void gio64_slot_device::device_start()
{
device_t *const card(get_card_device());
if (card && !dynamic_cast<device_gio64_card_interface *>(card))
throw emu_fatalerror("gio64_slot_device: card device %s (%s) does not implement device_gio64_card_interface\n", card->tag(), card->name());
}
DEFINE_DEVICE_TYPE(GIO64, gio64_device, "gio64", "SGI GIO64 Bus")
device_memory_interface::space_config_vector gio64_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(0, &m_space_config)
};
}
gio64_device::gio64_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: gio64_device(mconfig, GIO64, tag, owner, clock)
{
}
gio64_device::gio64_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, type, tag, owner, clock)
, device_memory_interface(mconfig, *this)
, m_space_config("GIO64 Space", ENDIANNESS_BIG, 64, 32, 0, address_map_constructor())
, m_maincpu(*this, finder_base::DUMMY_TAG)
, m_hpc3(*this, finder_base::DUMMY_TAG)
{
}
void gio64_device::device_resolve_objects()
{
}
void gio64_device::device_start()
{
std::fill(std::begin(m_device_list), std::end(m_device_list), nullptr);
m_space = &space(0);
m_space->install_readwrite_handler(0x00000000, 0x003fffff, read64_delegate(FUNC(gio64_device::no_gfx_r), this), write64_delegate(FUNC(gio64_device::no_gfx_w), this));
m_space->install_readwrite_handler(0x00400000, 0x005fffff, read64_delegate(FUNC(gio64_device::no_exp0_r), this), write64_delegate(FUNC(gio64_device::no_exp0_w), this));
m_space->install_readwrite_handler(0x00600000, 0x009fffff, read64_delegate(FUNC(gio64_device::no_exp1_r), this), write64_delegate(FUNC(gio64_device::no_exp1_w), this));
}
READ64_MEMBER(gio64_device::no_gfx_r) { return ~0ULL; }
READ64_MEMBER(gio64_device::no_exp0_r) { return ~0ULL; }
READ64_MEMBER(gio64_device::no_exp1_r) { return ~0ULL; }
WRITE64_MEMBER(gio64_device::no_gfx_w) { }
WRITE64_MEMBER(gio64_device::no_exp0_w) { }
WRITE64_MEMBER(gio64_device::no_exp1_w) { }
READ64_MEMBER(gio64_device::read)
{
return m_space->read_qword(offset << 3, mem_mask);
}
WRITE64_MEMBER(gio64_device::write)
{
m_space->write_qword(offset << 3, data, mem_mask);
}
device_gio64_card_interface *gio64_device::get_gio64_card(int slot)
{
if (slot < 0)
{
return nullptr;
}
if (m_device_list[slot])
{
return m_device_list[slot];
}
return nullptr;
}
void gio64_device::add_gio64_card(device_gio64_card_interface::gio64_slot_type_t slot_type, device_gio64_card_interface *card)
{
m_device_list[slot_type] = card;
card->install_device();
}
device_gio64_card_interface::device_gio64_card_interface(const machine_config &mconfig, device_t &device)
: device_slot_card_interface(mconfig, device)
, m_gio64(nullptr)
, m_gio64_slottag(nullptr)
, m_slot_type(GIO64_SLOT_COUNT)
{
}
device_gio64_card_interface::~device_gio64_card_interface()
{
}
void device_gio64_card_interface::interface_validity_check(validity_checker &valid) const
{
}
void device_gio64_card_interface::interface_pre_start()
{
device_slot_card_interface::interface_pre_start();
if (!m_gio64)
{
fatalerror("Can't find SGI GIO64 device\n");
}
if (GIO64_SLOT_COUNT == m_slot_type)
{
if (!m_gio64->started())
throw device_missing_dependencies();
if (strcmp(m_gio64_slottag, ":gio64_gfx") == 0)
m_slot_type = GIO64_SLOT_GFX;
else if (strcmp(m_gio64_slottag, ":gio64_exp0") == 0)
m_slot_type = GIO64_SLOT_EXP0;
else if (strcmp(m_gio64_slottag, ":gio64_exp1") == 0)
m_slot_type = GIO64_SLOT_EXP1;
else
fatalerror("Slot %s incorrectly named for SGI GIO64 graphics slot\n", m_gio64_slottag);
m_gio64->add_gio64_card(m_slot_type, this);
}
}
void device_gio64_card_interface::set_gio64(gio64_device *gio64, const char *slottag)
{
m_gio64 = gio64;
m_gio64_slottag = slottag;
}

165
src/devices/bus/gio64/gio64.h
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@ -1,165 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
gio64.h - SGI GIO64 slot bus and GIO64 device emulation
***************************************************************************/
#ifndef MAME_BUS_GIO64_GIO64_H
#define MAME_BUS_GIO64_GIO64_H
#pragma once
#include "cpu/mips/r4000.h"
#include "machine/hpc3.h"
class gio64_device;
class gio64_slot_device : public device_t, public device_slot_interface
{
public:
// construction/destruction
template <typename T, typename U>
gio64_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&gio64_tag, U &&opts, const char *dflt)
: gio64_slot_device(mconfig, tag, owner, (uint32_t)0)
{
option_reset();
opts(*this);
set_default_option(dflt);
set_fixed(false);
m_gio64.set_tag(std::forward<T>(gio64_tag));
}
gio64_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
gio64_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
// device-level overrides
virtual void device_validity_check(validity_checker &valid) const override;
virtual void device_resolve_objects() override;
virtual void device_start() override;
// configuration
required_device<gio64_device> m_gio64;
DECLARE_READ32_MEMBER(timeout_r);
DECLARE_WRITE32_MEMBER(timeout_w);
};
DECLARE_DEVICE_TYPE(GIO64_SLOT, gio64_slot_device)
// class representing interface-specific live GIO64 card
class device_gio64_card_interface : public device_slot_card_interface
{
friend class gio64_device;
public:
// construction/destruction
virtual ~device_gio64_card_interface();
// inline configuration
void set_gio64(gio64_device *gio64, const char *slottag);
virtual void mem_map(address_map &map) = 0;
protected:
device_gio64_card_interface(const machine_config &mconfig, device_t &device);
enum gio64_slot_type_t : uint32_t
{
GIO64_SLOT_GFX,
GIO64_SLOT_EXP0,
GIO64_SLOT_EXP1,
GIO64_SLOT_COUNT
};
virtual void interface_validity_check(validity_checker &valid) const override;
virtual void interface_pre_start() override;
virtual void install_device() = 0;
gio64_device &gio64() { assert(m_gio64); return *m_gio64; }
gio64_device *m_gio64;
const char *m_gio64_slottag;
gio64_slot_type_t m_slot_type;
};
class gio64_device : public device_t,
public device_memory_interface
{
friend class device_gio64_card_interface;
public:
// construction/destruction
template <typename T, typename U>
gio64_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag, U &&hpc3_tag)
: gio64_device(mconfig, tag, owner, (uint32_t)0)
{
set_cpu_tag(std::forward<T>(cpu_tag));
set_hpc3_tag(std::forward<U>(hpc3_tag));
}
gio64_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// inline configuration
template <typename T> void set_cpu_tag(T &&tag) { m_maincpu.set_tag(std::forward<T>(tag)); }
template <typename T> void set_hpc3_tag(T &&tag) { m_hpc3.set_tag(std::forward<T>(tag)); }
virtual space_config_vector memory_space_config() const override;
const address_space_config m_space_config;
void add_gio64_card(device_gio64_card_interface::gio64_slot_type_t slot_type, device_gio64_card_interface *card);
device_gio64_card_interface *get_gio64_card(int slot);
template<typename T> void install_graphics(T &device, void (T::*map)(class address_map &map), uint64_t unitmask = ~u64(0))
{
m_space->install_device(0x000000, 0x3fffff, device, map, unitmask);
}
template<typename T> void install_expansion(int index, T &device, void (T::*map)(class address_map &map), uint64_t unitmask = ~u64(0))
{
if (index == 0)
m_space->install_device(0x400000, 0x5fffff, device, map, unitmask);
else if (index == 1)
m_space->install_device(0x600000, 0x9fffff, device, map, unitmask);
else
fatalerror("Invalid SGI GIO64 expansion slot index: %d\n", index);
}
hpc3_base_device* get_hpc3() { return m_hpc3.target(); }
DECLARE_READ64_MEMBER(read);
DECLARE_WRITE64_MEMBER(write);
protected:
gio64_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
// device-level overrides
virtual void device_resolve_objects() override;
virtual void device_start() override;
// internal state
required_device<r4000_base_device> m_maincpu;
required_device<hpc3_base_device> m_hpc3;
address_space *m_space;
device_gio64_card_interface *m_device_list[3];
private:
DECLARE_READ64_MEMBER(no_gfx_r);
DECLARE_READ64_MEMBER(no_exp0_r);
DECLARE_READ64_MEMBER(no_exp1_r);
DECLARE_WRITE64_MEMBER(no_gfx_w);
DECLARE_WRITE64_MEMBER(no_exp0_w);
DECLARE_WRITE64_MEMBER(no_exp1_w);
};
DECLARE_DEVICE_TYPE(GIO64, gio64_device)
void gio64_cards(device_slot_interface &device);
#endif // MAME_BUS_GIO_GIO_H

3986
src/devices/bus/gio64/newport.cpp
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File diff suppressed because it is too large Load Diff

351
src/devices/bus/gio64/newport.h
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@ -1,351 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*
SGI "Newport" graphics board used in the Indy and some Indigo2s
*/
#ifndef MAME_BUS_GIO_NEWPORT_H
#define MAME_BUS_GIO_NEWPORT_H
#pragma once
#include "gio64.h"
#include "screen.h"
#define ENABLE_NEWVIEW_LOG (0)
class newport_base_device : public device_t
, public device_palette_interface
, public device_gio64_card_interface
{
public:
newport_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t global_mask);
// device_gio_slot_interface overrides
virtual void install_device() override;
DECLARE_READ64_MEMBER(rex3_r);
DECLARE_WRITE64_MEMBER(rex3_w);
uint32_t screen_update(screen_device &device, bitmap_rgb32 &bitmap, const rectangle &cliprect);
DECLARE_WRITE_LINE_MEMBER(vblank_w);
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
virtual void device_add_mconfig(machine_config &config) override;
virtual uint32_t palette_entries() const override { return 0x2000; }
virtual void device_start() override;
virtual void device_reset() override;
void mem_map(address_map &map) override;
static constexpr device_timer_id DCB_TIMEOUT = 0;
enum
{
DCR_CURSOR_FUNC_ENABLE_BIT = 4,
DCR_CURSOR_ENABLE_BIT = 7,
DCR_CURSOR_MODE_BIT = 8,
DCR_CURSOR_MODE_GLYPH = 0,
DCR_CURSOR_MODE_CROSSHAIR = 1,
DCR_CURSOR_SIZE_BIT = 9,
DCR_CURSOR_SIZE_32 = 0,
DCR_CURSOR_SIZE_64 = 1
};
enum
{
DCB_ADDR_VC2,
DCB_ADDR_CMAP01,
DCB_ADDR_CMAP0,
DCB_ADDR_CMAP1,
DCB_ADDR_XMAP01,
DCB_ADDR_XMAP0,
DCB_ADDR_XMAP1,
DCB_ADDR_RAMDAC,
DCB_ADDR_CC1,
DCB_ADDR_AB1,
DCB_ADDR_PCD = 12
};
enum
{
STATUS_GFXBUSY = (1 << 3),
STATUS_BACKBUSY = (1 << 4),
STATUS_VRINT = (1 << 5),
STATUS_VIDEOINT = (1 << 6),
STATUS_GFIFOLEVEL_SHIFT = 7,
STATUS_GFIFOLEVEL_MASK = (0x3f << STATUS_GFIFOLEVEL_SHIFT),
STATUS_BFIFOLEVEL_SHIFT = 13,
STATUS_BFIFOLEVEL_MASK = (0x1f << STATUS_BFIFOLEVEL_SHIFT),
STATUS_BFIFO_INT = 18,
STATUS_GFIFO_INT = 19
};
struct vc2_t
{
uint16_t m_vid_entry;
uint16_t m_cursor_entry;
uint16_t m_cursor_x;
uint16_t m_cursor_y;
uint16_t m_cur_cursor_x;
uint16_t m_did_entry;
uint16_t m_scanline_len;
uint16_t m_ram_addr;
uint16_t m_vt_frame_ptr;
uint16_t m_vt_line_ptr;
uint16_t m_vt_line_run;
uint16_t m_vt_line_count;
uint16_t m_cursor_table_ptr;
uint16_t m_work_cursor_y;
uint16_t m_did_frame_ptr;
uint16_t m_did_line_ptr;
uint16_t m_display_ctrl;
uint16_t m_config;
uint16_t m_ram[0x8000];
uint8_t m_reg_idx;
uint16_t m_reg_data;
};
struct xmap_t
{
uint32_t m_config;
uint32_t m_revision;
uint32_t m_entries;
uint32_t m_cursor_cmap;
uint32_t m_popup_cmap;
uint32_t m_mode_table_idx;
uint32_t m_mode_table[0x20];
};
struct rex3_t
{
uint32_t m_draw_mode0;
bool m_color_host;
uint32_t m_draw_mode1;
uint8_t m_plane_enable;
uint8_t m_plane_depth;
bool m_rwpacked;
bool m_rwdouble;
uint8_t m_hostdepth;
uint8_t m_sfactor;
uint8_t m_dfactor;
uint8_t m_logicop;
uint32_t m_store_shift;
uint32_t m_host_shift;
uint32_t m_write_width;
uint32_t m_ls_mode;
uint32_t m_ls_pattern;
uint32_t m_ls_pattern_saved;
uint32_t m_z_pattern;
uint32_t m_color_back;
uint32_t m_color_vram;
uint32_t m_alpha_ref;
uint32_t m_setup;
uint32_t m_step_z;
int32_t m_x_start;
int32_t m_y_start;
int32_t m_x_end;
int32_t m_y_end;
int16_t m_x_start_frac;
int16_t m_y_start_frac;
int16_t m_x_end_frac;
int16_t m_y_end_frac;
int16_t m_x_save;
uint32_t m_xy_move;
int16_t m_x_move;
int16_t m_y_move;
uint32_t m_bres_d;
uint32_t m_bres_s1;
uint32_t m_bres_octant_inc1;
uint32_t m_bres_round_inc2;
uint32_t m_bres_e1;
uint32_t m_bres_s2;
uint32_t m_a_weight0;
uint32_t m_a_weight1;
uint32_t m_x_start_f;
uint32_t m_y_start_f;
uint32_t m_x_end_f;
uint32_t m_y_end_f;
int16_t m_x_start_i;
uint32_t m_xy_start_i;
int16_t m_y_start_i;
uint32_t m_xy_end_i;
int16_t m_x_end_i;
int16_t m_y_end_i;
uint32_t m_x_start_end_i;
uint32_t m_color_red;
uint32_t m_color_alpha;
uint32_t m_color_green;
uint32_t m_color_blue;
uint32_t m_slope_red;
uint32_t m_slope_alpha;
uint32_t m_slope_green;
uint32_t m_slope_blue;
uint32_t m_write_mask;
uint32_t m_color_i;
uint32_t m_zero_overflow;
uint64_t m_host_dataport;
uint32_t m_dcb_mode;
uint32_t m_dcb_reg_select;
uint32_t m_dcb_slave_select;
uint32_t m_dcb_data_msw;
uint32_t m_dcb_data_lsw;
uint32_t m_smask_x[5];
uint32_t m_smask_y[5];
uint32_t m_top_scanline;
uint32_t m_xy_window;
int16_t m_x_window;
int16_t m_y_window;
uint32_t m_clip_mode;
uint32_t m_config;
uint32_t m_status;
uint8_t m_xfer_width;
};
struct cmap_t
{
uint16_t m_palette_idx;
uint32_t m_palette[0x10000];
};
uint8_t get_cursor_pixel(int x, int y);
// internal state
uint32_t cmap0_read();
void cmap0_write(uint32_t data);
uint32_t cmap1_read();
uint32_t xmap0_read();
void xmap0_write(uint32_t data);
uint32_t xmap1_read();
void xmap1_write(uint32_t data);
uint32_t vc2_read();
void vc2_write(uint32_t data);
void ramdac_write(uint32_t data);
void write_x_start(int32_t val);
void write_y_start(int32_t val);
void write_x_end(int32_t val);
void write_y_end(int32_t val);
bool pixel_clip_pass(int16_t x, int16_t y);
void write_pixel(uint32_t color);
void write_pixel(int16_t x, int16_t y, uint32_t color);
void blend_pixel(uint32_t *dest_buf, uint32_t src);
void logic_pixel(uint32_t *dest_buf, uint32_t src);
void store_pixel(uint32_t *dest_buf, uint32_t src);
void iterate_shade();
virtual uint32_t get_cmap_revision() = 0;
virtual uint32_t get_xmap_revision() = 0;
uint32_t get_host_color();
uint32_t get_rgb_color(int16_t x, int16_t y);
uint32_t convert_4bpp_bgr_to_8bpp(uint8_t pix_in);
uint32_t convert_4bpp_bgr_to_12bpp(uint8_t pix_in);
uint32_t convert_4bpp_bgr_to_24bpp(uint8_t pix_in);
uint32_t convert_8bpp_bgr_to_4bpp(uint8_t pix_in);
uint32_t convert_8bpp_bgr_to_12bpp(uint8_t pix_in);
uint32_t convert_8bpp_bgr_to_24bpp(uint8_t pix_in);
uint32_t convert_12bpp_bgr_to_4bpp(uint16_t pix_in);
uint32_t convert_12bpp_bgr_to_8bpp(uint16_t pix_in);
uint32_t convert_12bpp_bgr_to_24bpp(uint16_t pix_in);
uint32_t convert_24bpp_bgr_to_4bpp(uint32_t pix_in);
uint32_t convert_24bpp_bgr_to_8bpp(uint32_t pix_in);
uint32_t convert_24bpp_bgr_to_12bpp(uint32_t pix_in);
uint32_t convert_4bpp_bgr_to_24bpp_rgb(uint8_t pix_in);
uint32_t convert_8bpp_bgr_to_24bpp_rgb(uint8_t pix_in);
uint32_t convert_12bpp_bgr_to_24bpp_rgb(uint16_t pix_in);
struct bresenham_octant_info_t
{
int16_t incrx1;
int16_t incrx2;
int16_t incry1;
int16_t incry2;
uint8_t loop;
};
uint8_t get_octant(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t dx, uint16_t dy);
void do_fline(uint32_t color);
void do_iline(uint32_t color);
uint32_t do_pixel_read();
uint64_t do_pixel_word_read();
void do_rex3_command();
void decode_vt_line(uint32_t line, uint32_t line_seq_ptr);
void decode_vt_table();
void update_screen_size();
void ramdac_remap(uint32_t *dest);
required_device<screen_device> m_screen;
uint32_t m_ramdac_lut_r[256];
uint32_t m_ramdac_lut_g[256];
uint32_t m_ramdac_lut_b[256];
uint8_t m_ramdac_lut_index;
vc2_t m_vc2;
xmap_t m_xmap0;
xmap_t m_xmap1;
rex3_t m_rex3;
std::unique_ptr<uint32_t[]> m_rgbci;
std::unique_ptr<uint32_t[]> m_olay;
std::unique_ptr<uint32_t[]> m_pup;
std::unique_ptr<uint32_t[]> m_cid;
std::unique_ptr<uint32_t[]> m_vt_table;
cmap_t m_cmap0;
uint32_t m_global_mask;
emu_timer *m_dcb_timeout_timer;
int m_readout_x0;
int m_readout_y0;
int m_readout_x1;
int m_readout_y1;
#if ENABLE_NEWVIEW_LOG
void start_logging();
void stop_logging();
FILE *m_newview_log;
#endif
static const uint32_t s_host_shifts[4];
};
class gio64_xl8_device : public newport_base_device
{
public:
gio64_xl8_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0U);
protected:
virtual uint32_t get_cmap_revision() override;
virtual uint32_t get_xmap_revision() override;
};
class gio64_xl24_device : public newport_base_device
{
public:
gio64_xl24_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0U);
protected:
virtual uint32_t get_cmap_revision() override;
virtual uint32_t get_xmap_revision() override;
};
DECLARE_DEVICE_TYPE(GIO64_XL8, gio64_xl8_device)
DECLARE_DEVICE_TYPE(GIO64_XL24, gio64_xl24_device)
#endif // MAME_BUS_GIO_NEWPORT_H

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src/devices/bus/sbus/artecon.cpp
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// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Artecon SB-300P 3-serial 1-parallel SBus card skeleton
The Artecon SB series of SBus cards uses up to 4 Cirrus Logic
CL-CD1400 Four-Channel Serial/Parallel Communications Engines.
Each chip supports up to four full-duplex serial channels, or three
full-duplex serial channels and one high-speed bidirectional parallel
channel.
***************************************************************************/
#include "emu.h"
#include "artecon.h"
DEFINE_DEVICE_TYPE(SBUS_SB300P, sbus_artecon_device, "sb300p", "Artecon SB-300P 3S/1P controller")
void sbus_artecon_device::mem_map(address_map &map)
{
map(0x00000000, 0x01ffffff).rw(FUNC(sbus_artecon_device::unknown_r), FUNC(sbus_artecon_device::unknown_w));
map(0x00000000, 0x00003fff).r(FUNC(sbus_artecon_device::rom_r));
}
ROM_START( sbus_artecon )
ROM_REGION32_BE(0x8000, "prom", ROMREGION_ERASEFF)
ROM_LOAD( "artecon_sbus_port.bin", 0x0000, 0x4000, CRC(bced6981) SHA1(1c6006fb8cb555eff0cb7c2783c776d05c6797f8))
ROM_END
const tiny_rom_entry *sbus_artecon_device::device_rom_region() const
{
return ROM_NAME( sbus_artecon );
}
void sbus_artecon_device::device_add_mconfig(machine_config &config)
{
}
sbus_artecon_device::sbus_artecon_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, SBUS_SB300P, tag, owner, clock)
, device_sbus_card_interface(mconfig, *this)
, m_rom(*this, "prom")
{
}
void sbus_artecon_device::device_start()
{
}
void sbus_artecon_device::install_device()
{
m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_artecon_device::mem_map);
}
READ32_MEMBER(sbus_artecon_device::unknown_r)
{
logerror("%s: unknown_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask);
return 0;
}
WRITE32_MEMBER(sbus_artecon_device::unknown_w)
{
logerror("%s: unknown_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
}
READ32_MEMBER(sbus_artecon_device::rom_r)
{
return ((uint32_t*)m_rom->base())[offset];
}

45
src/devices/bus/sbus/artecon.h
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// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Artecon SB-300P 3-serial 1-parallel SBus card skeleton
***************************************************************************/
#ifndef MAME_BUS_SBUS_ARTECON_H
#define MAME_BUS_SBUS_ARTECON_H
#pragma once
#include "sbus.h"
class sbus_artecon_device : public device_t, public device_sbus_card_interface
{
public:
// construction/destruction
sbus_artecon_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
// device_t overrides
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual void device_start() override;
// device_sbus_slot_interface overrides
virtual void install_device() override;
DECLARE_READ32_MEMBER(unknown_r);
DECLARE_WRITE32_MEMBER(unknown_w);
DECLARE_READ32_MEMBER(rom_r);
private:
void mem_map(address_map &map) override;
required_memory_region m_rom;
};
DECLARE_DEVICE_TYPE(SBUS_SB300P, sbus_artecon_device)
#endif // MAME_BUS_SBUS_ARTECON_H

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src/devices/bus/sbus/bwtwo.cpp
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// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Sun bwtwo monochrome video controller
***************************************************************************/
#include "emu.h"
#include "bwtwo.h"
#include "screen.h"
DEFINE_DEVICE_TYPE(SBUS_BWTWO, sbus_bwtwo_device, "bwtwo", "Sun bwtwo SBus Video")
void sbus_bwtwo_device::mem_map(address_map &map)
{
map(0x00000000, 0x00007fff).r(FUNC(sbus_bwtwo_device::rom_r));
map(0x00400000, 0x0040001f).rw(FUNC(sbus_bwtwo_device::regs_r), FUNC(sbus_bwtwo_device::regs_w));
map(0x00800000, 0x008fffff).rw(FUNC(sbus_bwtwo_device::vram_r), FUNC(sbus_bwtwo_device::vram_w));
}
ROM_START( sbus_bwtwo )
ROM_REGION32_BE(0x8000, "prom", ROMREGION_ERASEFF)
ROM_SYSTEM_BIOS(0, "1081", "P/N 525-1081-01")
ROMX_LOAD( "bw2_525-1081-01.bin", 0x0000, 0x8000, CRC(8b70c8c7) SHA1(fd750ad2fd6efdde957f8b0f9abf962e14fe221a), ROM_BIOS(0) )
ROM_SYSTEM_BIOS(1, "1124", "P/N 525-1124-01")
ROMX_LOAD( "bw2_525-1124-01.bin", 0x0000, 0x0800, CRC(e37a3314) SHA1(78761bd2369cb0c58ef1344c697a47d3a659d4bc), ROM_BIOS(1) )
ROM_END
const tiny_rom_entry *sbus_bwtwo_device::device_rom_region() const
{
return ROM_NAME( sbus_bwtwo );
}
void sbus_bwtwo_device::device_add_mconfig(machine_config &config)
{
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
screen.set_screen_update(FUNC(sbus_bwtwo_device::screen_update));
screen.set_size(1152, 900);
screen.set_visarea(0, 1152-1, 0, 900-1);
screen.set_refresh_hz(72);
}
sbus_bwtwo_device::sbus_bwtwo_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, SBUS_BWTWO, tag, owner, clock)
, device_sbus_card_interface(mconfig, *this)
, m_rom(*this, "prom")
, m_screen(*this, "screen")
{
}
void sbus_bwtwo_device::device_start()
{
m_vram = std::make_unique<uint8_t[]>(0x100000);
save_pointer(NAME(m_vram), 0x100000);
for (int i = 0; i < 0x100; i++)
{
for (int bit = 7; bit >= 0; bit--)
{
m_mono_lut[i][7 - bit] = BIT(i, bit) ? 0 : ~0;
}
}
}
void sbus_bwtwo_device::install_device()
{
m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_bwtwo_device::mem_map);
}
uint32_t sbus_bwtwo_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
uint8_t *line = &m_vram[0];
for (int y = 0; y < 900; y++)
{
uint32_t *scanline = &bitmap.pix32(y);
for (int x = 0; x < 1152/8; x++)
{
memcpy(scanline, m_mono_lut[*line], sizeof(uint32_t) * 8);
line++;
scanline += 8;
}
}
return 0;
}
READ8_MEMBER(sbus_bwtwo_device::regs_r)
{
logerror("%s: regs_r (unimplemented): %08x\n", machine().describe_context(), 0x400000 + offset);
return 0;
}
WRITE8_MEMBER(sbus_bwtwo_device::regs_w)
{
logerror("%s: regs_w (unimplemented): %08x = %02x\n", machine().describe_context(), 0x400000 + offset, data);
}
READ32_MEMBER(sbus_bwtwo_device::rom_r)
{
return ((uint32_t*)m_rom->base())[offset];
}
READ8_MEMBER(sbus_bwtwo_device::vram_r)
{
return m_vram[offset];
}
WRITE8_MEMBER(sbus_bwtwo_device::vram_w)
{
m_vram[offset] = data;
}

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src/devices/bus/sbus/bwtwo.h
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// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Sun bwtwo monochrome video controller
***************************************************************************/
#ifndef MAME_BUS_SBUS_BWTWO_H
#define MAME_BUS_SBUS_BWTWO_H
#pragma once
#include "sbus.h"
class sbus_bwtwo_device : public device_t, public device_sbus_card_interface
{
public:
// construction/destruction
sbus_bwtwo_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
// device_t overrides
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual void device_start() override;
// device_sbus_slot_interface overrides
virtual void install_device() override;
DECLARE_READ8_MEMBER(regs_r);
DECLARE_WRITE8_MEMBER(regs_w);
DECLARE_READ32_MEMBER(rom_r);
DECLARE_READ8_MEMBER(vram_r);
DECLARE_WRITE8_MEMBER(vram_w);
private:
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
void mem_map(address_map &map) override;
required_memory_region m_rom;
std::unique_ptr<uint8_t[]> m_vram;
required_device<screen_device> m_screen;
uint32_t m_mono_lut[256][8];
};
DECLARE_DEVICE_TYPE(SBUS_BWTWO, sbus_bwtwo_device)
#endif // MAME_BUS_SBUS_BWTWO_H

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src/devices/bus/sbus/cgsix.cpp
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src/devices/bus/sbus/cgsix.h
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// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Sun cgsix-series accelerated 8-bit color video controller
***************************************************************************/
#ifndef MAME_BUS_SBUS_CGSIX_H
#define MAME_BUS_SBUS_CGSIX_H
#pragma once
#include "sbus.h"
#include "video/bt45x.h"
#include "screen.h"
class sbus_cgsix_device : public device_t, public device_sbus_card_interface
{
public:
static constexpr feature_type imperfect_features() { return feature::GRAPHICS; }
protected:
// construction/destruction
sbus_cgsix_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const uint32_t vram_size)
: sbus_cgsix_device(mconfig, type, tag, owner, clock)
{
set_vram_size(vram_size);
}
sbus_cgsix_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
// configuration
void set_vram_size(uint32_t vram_size) { m_vram_size = vram_size; }
// device_t overrides
virtual void device_start() override;
virtual void device_reset() override;
DECLARE_READ32_MEMBER(rom_r);
DECLARE_READ32_MEMBER(unknown_r);
DECLARE_WRITE32_MEMBER(unknown_w);
DECLARE_READ32_MEMBER(vram_r);
DECLARE_WRITE32_MEMBER(vram_w);
DECLARE_READ32_MEMBER(fbc_r);
DECLARE_WRITE32_MEMBER(fbc_w);
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
uint8_t perform_rasterop(uint8_t src, uint8_t dst);
void handle_font_poke();
void handle_draw_command();
void handle_blit_command();
void base_map(address_map &map);
enum
{
ROP_CLR = 0x00,
ROP_SRC_NOR_DST = 0x01,
ROP_NSRC_AND_DST = 0x02,
ROP_NOT_SRC = 0x03,
ROP_SRC_AND_NDST = 0x04,
ROP_NOT_DST = 0x05,
ROP_SRC_XOR_DST = 0x06,
ROP_SRC_NAND_DST = 0x07,
ROP_SRC_AND_DST = 0x08,
ROP_SRC_XNOR_DST = 0x09,
ROP_DST = 0x0a,
ROP_NSRC_OR_DST = 0x0b,
ROP_SRC = 0x0c,
ROP_SRC_OR_NDST = 0x0d,
ROP_SRC_OR_DST = 0x0e,
ROP_SET = 0x0f
};
enum
{
FBC_MISC_INDEX_SHIFT = 4,
FBC_MISC_INDEX_MOD_SHIFT = 6,
FBC_MISC_BDISP_SHIFT = 7,
FBC_MISC_BREAD_SHIFT = 9,
FBC_MISC_BWRITE1_SHIFT = 11,
FBC_MISC_BWRITE0_SHIFT = 13,
FBC_MISC_DRAW_SHIFT = 15,
FBC_MISC_DATA_SHIFT = 17,
FBC_MISC_VBLANK_SHIFT = 19,
FBC_MISC_BLIT_SHIFT = 20
};
enum
{
FBC_MISC_INDEX_MASK = 0x3,
FBC_MISC_INDEX_MOD_MASK = 0x1,
FBC_MISC_BDISP_MASK = 0x3,
FBC_MISC_BREAD_MASK = 0x3,
FBC_MISC_BWRITE1_MASK = 0x3,
FBC_MISC_BWRITE0_MASK = 0x3,
FBC_MISC_DRAW_MASK = 0x3,
FBC_MISC_DATA_MASK = 0x3,
FBC_MISC_VBLANK_MASK = 0x1,
FBC_MISC_BLIT_MASK = 0x3
};
enum
{
FBC_MISC_BDISP_IGNORE = 0,
FBC_MISC_BDISP_0 = 1,
FBC_MISC_BDISP_1 = 2,
FBC_MISC_BDISP_ILLEGAL = 3,
FBC_MISC_BREAD_IGNORE = 0,
FBC_MISC_BREAD_0 = 1,
FBC_MISC_BREAD_1 = 2,
FBC_MISC_BREAD_ILLEGAL = 3,
FBC_MISC_BWRITE1_IGNORE = 0,
FBC_MISC_BWRITE1_ENABLE = 1,
FBC_MISC_BWRITE1_DISABLE = 2,
FBC_MISC_BWRITE1_ILLEGAL = 3,
FBC_MISC_BWRITE0_IGNORE = 0,
FBC_MISC_BWRITE0_ENABLE = 1,
FBC_MISC_BWRITE0_DISABLE = 2,
FBC_MISC_BWRITE0_ILLEGAL = 3,
FBC_MISC_DRAW_IGNORE = 0,
FBC_MISC_DRAW_RENDER = 1,
FBC_MISC_DRAW_PICK = 2,
FBC_MISC_DRAW_ILLEGAL = 3,
FBC_MISC_DATA_IGNORE = 0,
FBC_MISC_DATA_COLOR8 = 1,
FBC_MISC_DATA_COLOR1 = 2,
FBC_MISC_DATA_HRMONO = 3,
FBC_MISC_BLIT_IGNORE = 0,
FBC_MISC_BLIT_NOSRC = 1,
FBC_MISC_BLIT_SRC = 2,
FBC_MISC_BLIT_ILLEGAL = 3
};
inline uint32_t fbc_misc_index() { return (m_fbc.m_misc >> FBC_MISC_INDEX_SHIFT) & FBC_MISC_INDEX_MASK; }
inline uint32_t fbc_misc_index_mod() { return (m_fbc.m_misc >> FBC_MISC_INDEX_MOD_SHIFT) & FBC_MISC_INDEX_MOD_MASK; }
inline uint32_t fbc_misc_bdisp() { return (m_fbc.m_misc >> FBC_MISC_BDISP_SHIFT) & FBC_MISC_BDISP_MASK; }
inline uint32_t fbc_misc_bread() { return (m_fbc.m_misc >> FBC_MISC_BREAD_SHIFT) & FBC_MISC_BREAD_MASK; }
inline uint32_t fbc_misc_bwrite1() { return (m_fbc.m_misc >> FBC_MISC_BWRITE1_SHIFT) & FBC_MISC_BWRITE1_MASK; }
inline uint32_t fbc_misc_bwrite0() { return (m_fbc.m_misc >> FBC_MISC_BWRITE0_SHIFT) & FBC_MISC_BWRITE0_MASK; }
inline uint32_t fbc_misc_draw() { return (m_fbc.m_misc >> FBC_MISC_DRAW_SHIFT) & FBC_MISC_DRAW_MASK; }
inline uint32_t fbc_misc_data() { return (m_fbc.m_misc >> FBC_MISC_DATA_SHIFT) & FBC_MISC_DATA_MASK; }
inline uint32_t fbc_misc_blit() { return (m_fbc.m_misc >> FBC_MISC_BLIT_SHIFT) & FBC_MISC_BLIT_MASK; }
enum
{
FBC_RASTEROP_ROP00_SHIFT = 0,
FBC_RASTEROP_ROP01_SHIFT = 4,
FBC_RASTEROP_ROP10_SHIFT = 8,
FBC_RASTEROP_ROP11_SHIFT = 12,
FBC_RASTEROP_PLOT_SHIFT = 16,
FBC_RASTEROP_RAST_SHIFT = 17,
FBC_RASTEROP_ATTR_SHIFT = 22,
FBC_RASTEROP_POLYG_SHIFT = 24,
FBC_RASTEROP_PATT_SHIFT = 26,
FBC_RASTEROP_PIXEL_SHIFT = 28,
FBC_RASTEROP_PLANE_SHIFT = 30
};
enum
{
FBC_RASTEROP_ROP00_MASK = 0xf,
FBC_RASTEROP_ROP01_MASK = 0xf,
FBC_RASTEROP_ROP10_MASK = 0xf,
FBC_RASTEROP_ROP11_MASK = 0xf,
FBC_RASTEROP_PLOT_MASK = 0x1,
FBC_RASTEROP_RAST_MASK = 0x1,
FBC_RASTEROP_ATTR_MASK = 0x3,
FBC_RASTEROP_POLYG_MASK = 0x3,
FBC_RASTEROP_PATT_MASK = 0x3,
FBC_RASTEROP_PIXEL_MASK = 0x3,
FBC_RASTEROP_PLANE_MASK = 0x3
};
enum
{
FBC_RASTEROP_PLOT_PLOT = 0,
FBC_RASTEROP_PLOT_UNPLOT = 1,
FBC_RASTEROP_RAST_BOOL = 0,
FBC_RASTEROP_RAST_LINEAR = 1,
FBC_RASTEROP_ATTR_IGNORE = 0,
FBC_RASTEROP_ATTR_UNSUPP = 1,
FBC_RASTEROP_ATTR_SUPP = 2,
FBC_RASTEROP_ATTR_ILLEGAL = 3,
FBC_RASTEROP_POLYG_IGNORE = 0,
FBC_RASTEROP_POLYG_OVERLAP = 1,
FBC_RASTEROP_POLYG_NONOVERLAP = 2,
FBC_RASTEROP_POLYG_ILLEGAL = 3,
FBC_RASTEROP_PATTERN_IGNORE = 0,
FBC_RASTEROP_PATTERN_ZEROES = 1,
FBC_RASTEROP_PATTERN_ONES = 2,
FBC_RASTEROP_PATTERN_MSK = 3,
FBC_RASTEROP_PIXEL_IGNORE = 0,
FBC_RASTEROP_PIXEL_ZEROES = 1,
FBC_RASTEROP_PIXEL_ONES = 2,
FBC_RASTEROP_PIXEL_MSK = 3,
FBC_RASTEROP_PLANE_IGNORE = 0,
FBC_RASTEROP_PLANE_ZEROES = 1,
FBC_RASTEROP_PLANE_ONES = 2,
FBC_RASTEROP_PLANE_MSK = 3
};
inline uint32_t fbc_rasterop_rop00() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP00_SHIFT) & FBC_RASTEROP_ROP00_MASK; }
inline uint32_t fbc_rasterop_rop01() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP01_SHIFT) & FBC_RASTEROP_ROP01_MASK; }
inline uint32_t fbc_rasterop_rop10() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP10_SHIFT) & FBC_RASTEROP_ROP10_MASK; }
inline uint32_t fbc_rasterop_rop11() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP11_SHIFT) & FBC_RASTEROP_ROP11_MASK; }
inline uint32_t fbc_rasterop_plot() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PLOT_SHIFT) & FBC_RASTEROP_PLOT_MASK; }
inline uint32_t fbc_rasterop_rast() { return (m_fbc.m_rasterop >> FBC_RASTEROP_RAST_SHIFT) & FBC_RASTEROP_RAST_MASK; }
inline uint32_t fbc_rasterop_attr() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ATTR_SHIFT) & FBC_RASTEROP_ATTR_MASK; }
inline uint32_t fbc_rasterop_polyg() { return (m_fbc.m_rasterop >> FBC_RASTEROP_POLYG_SHIFT) & FBC_RASTEROP_POLYG_MASK; }
inline uint32_t fbc_rasterop_pattern() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PATT_SHIFT) & FBC_RASTEROP_PATT_MASK; }
inline uint32_t fbc_rasterop_pixel() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PIXEL_SHIFT) & FBC_RASTEROP_PIXEL_MASK; }
inline uint32_t fbc_rasterop_plane() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PLANE_SHIFT) & FBC_RASTEROP_PLANE_MASK; }
enum
{
FBC_MISC = 0x004/4,
FBC_CLIP_CHECK = 0x008/4,
FBC_STATUS = 0x010/4,
FBC_DRAW_STATUS = 0x014/4,
FBC_BLIT_STATUS = 0x018/4,
FBC_FONT = 0x01c/4,
FBC_X0 = 0x080/4,
FBC_Y0 = 0x084/4,
FBC_Z0 = 0x088/4,
FBC_COLOR0 = 0x08c/4,
FBC_X1 = 0x090/4,
FBC_Y1 = 0x094/4,
FBC_Z1 = 0x098/4,
FBC_COLOR1 = 0x09c/4,
FBC_X2 = 0x0a0/4,
FBC_Y2 = 0x0a4/4,
FBC_Z2 = 0x0a8/4,
FBC_COLOR2 = 0x0ac/4,
FBC_X3 = 0x0b0/4,
FBC_Y3 = 0x0b4/4,
FBC_Z3 = 0x0b8/4,
FBC_COLOR3 = 0x0bc/4,
FBC_RASTER_OFFX = 0x0c0/4,
FBC_RASTER_OFFY = 0x0c4/4,
FBC_AUTOINCX = 0x0d0/4,
FBC_AUTOINCY = 0x0d4/4,
FBC_CLIP_MINX = 0x0e0/4,
FBC_CLIP_MINY = 0x0e4/4,
FBC_CLIP_MAXX = 0x0f0/4,
FBC_CLIP_MAXY = 0x0f4/4,
FBC_FCOLOR = 0x100/4,
FBC_BCOLOR = 0x104/4,
FBC_RASTEROP = 0x108/4,
FBC_PLANE_MASK = 0x10c/4,
FBC_PIXEL_MASK = 0x110/4,
FBC_PATT_ALIGN = 0x11c/4,
FBC_PATTERN0 = 0x120/4,
FBC_PATTERN1 = 0x124/4,
FBC_PATTERN2 = 0x128/4,
FBC_PATTERN3 = 0x12c/4,
FBC_PATTERN4 = 0x130/4,
FBC_PATTERN5 = 0x134/4,
FBC_PATTERN6 = 0x138/4,
FBC_PATTERN7 = 0x13c/4,
FBC_IPOINT_ABSX = 0x800/4,
FBC_IPOINT_ABSY = 0x804/4,
FBC_IPOINT_ABSZ = 0x808/4,
FBC_IPOINT_RELX = 0x810/4,
FBC_IPOINT_RELY = 0x814/4,
FBC_IPOINT_RELZ = 0x818/4,
FBC_IPOINT_R = 0x830/4,
FBC_IPOINT_G = 0x834/4,
FBC_IPOINT_B = 0x838/4,
FBC_IPOINT_A = 0x83c/4,
FBC_ILINE_ABSX = 0x840/4,
FBC_ILINE_ABSY = 0x844/4,
FBC_ILINE_ABSZ = 0x848/4,
FBC_ILINE_RELX = 0x850/4,
FBC_ILINE_RELY = 0x854/4,
FBC_ILINE_RELZ = 0x858/4,
FBC_ILINE_R = 0x870/4,
FBC_ILINE_G = 0x874/4,
FBC_ILINE_B = 0x878/4,
FBC_ILINE_A = 0x87c/4,
FBC_ITRI_ABSX = 0x880/4,
FBC_ITRI_ABSY = 0x884/4,
FBC_ITRI_ABSZ = 0x888/4,
FBC_ITRI_RELX = 0x890/4,
FBC_ITRI_RELY = 0x894/4,
FBC_ITRI_RELZ = 0x898/4,
FBC_ITRI_R = 0x8b0/4,
FBC_ITRI_G = 0x8b4/4,
FBC_ITRI_B = 0x8b8/4,
FBC_ITRI_A = 0x8bc/4,
FBC_IQUAD_ABSX = 0x8c0/4,
FBC_IQUAD_ABSY = 0x8c4/4,
FBC_IQUAD_ABSZ = 0x8c8/4,
FBC_IQUAD_RELX = 0x8d0/4,
FBC_IQUAD_RELY = 0x8d4/4,
FBC_IQUAD_RELZ = 0x8d8/4,
FBC_IQUAD_R = 0x8f0/4,
FBC_IQUAD_G = 0x8f4/4,
FBC_IQUAD_B = 0x8f8/4,
FBC_IQUAD_A = 0x8fc/4,
FBC_IRECT_ABSX = 0x900/4,
FBC_IRECT_ABSY = 0x904/4,
FBC_IRECT_ABSZ = 0x908/4,
FBC_IRECT_RELX = 0x910/4,
FBC_IRECT_RELY = 0x914/4,
FBC_IRECT_RELZ = 0x918/4,
FBC_IRECT_R = 0x930/4,
FBC_IRECT_G = 0x934/4,
FBC_IRECT_B = 0x938/4,
FBC_IRECT_A = 0x93c/4,
};
struct vertex_t
{
uint32_t m_absx;
uint32_t m_absy;
uint32_t m_absz;
uint32_t m_relx;
uint32_t m_rely;
uint32_t m_relz;
uint32_t m_r;
uint32_t m_g;
uint32_t m_b;
uint32_t m_a;
};
enum prim_type : uint32_t
{
PRIM_POINT = 0,
PRIM_LINE,
PRIM_TRI,
PRIM_QUAD,
PRIM_RECT,
PRIM_COUNT
};
struct fbc_t
{
uint32_t m_misc;
uint32_t m_clip_check;
uint32_t m_status;
uint32_t m_draw_status;
uint32_t m_blit_status;
uint32_t m_font;
uint32_t m_x0;
uint32_t m_y0;
uint32_t m_z0;
uint32_t m_color0;
uint32_t m_x1;
uint32_t m_y1;
uint32_t m_z1;
uint32_t m_color1;
uint32_t m_x2;
uint32_t m_y2;
uint32_t m_z2;
uint32_t m_color2;
uint32_t m_x3;
uint32_t m_y3;
uint32_t m_z3;
uint32_t m_color3;
uint32_t m_raster_offx;
uint32_t m_raster_offy;
uint32_t m_autoincx;
uint32_t m_autoincy;
uint32_t m_clip_minx;
uint32_t m_clip_miny;
uint32_t m_clip_maxx;
uint32_t m_clip_maxy;
uint8_t m_fcolor;
uint8_t m_bcolor;
uint32_t m_rasterop;
uint32_t m_plane_mask;
uint32_t m_pixel_mask;
uint32_t m_patt_align;
uint32_t m_pattern[8];
uint32_t m_ipoint_absx;
uint32_t m_ipoint_absy;
uint32_t m_ipoint_absz;
uint32_t m_ipoint_relx;
uint32_t m_ipoint_rely;
uint32_t m_ipoint_relz;
uint32_t m_ipoint_r;
uint32_t m_ipoint_g;
uint32_t m_ipoint_b;
uint32_t m_ipoint_a;
uint32_t m_iline_absx;
uint32_t m_iline_absy;
uint32_t m_iline_absz;
uint32_t m_iline_relx;
uint32_t m_iline_rely;
uint32_t m_iline_relz;
uint32_t m_iline_r;
uint32_t m_iline_g;
uint32_t m_iline_b;
uint32_t m_iline_a;
uint32_t m_itri_absx;
uint32_t m_itri_absy;
uint32_t m_itri_absz;
uint32_t m_itri_relx;
uint32_t m_itri_rely;
uint32_t m_itri_relz;
uint32_t m_itri_r;
uint32_t m_itri_g;
uint32_t m_itri_b;
uint32_t m_itri_a;
uint32_t m_iquad_absx;
uint32_t m_iquad_absy;
uint32_t m_iquad_absz;
uint32_t m_iquad_relx;
uint32_t m_iquad_rely;
uint32_t m_iquad_relz;
uint32_t m_iquad_r;
uint32_t m_iquad_g;
uint32_t m_iquad_b;
uint32_t m_iquad_a;
uint32_t m_irect_absx;
uint32_t m_irect_absy;
uint32_t m_irect_absz;
uint32_t m_irect_relx;
uint32_t m_irect_rely;
uint32_t m_irect_relz;
uint32_t m_irect_r;
uint32_t m_irect_g;
uint32_t m_irect_b;
uint32_t m_irect_a;
vertex_t m_prim_buf[0x1000]; // unknown size
uint32_t m_vertex_count;
uint32_t m_curr_prim_type;
};
required_memory_region m_rom;
std::unique_ptr<uint32_t[]> m_vram;
required_device<screen_device> m_screen;
required_device<bt458_device> m_ramdac;
fbc_t m_fbc;
uint32_t m_vram_size;
};
class sbus_turbogx_device : public sbus_cgsix_device
{
public:
sbus_turbogx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
// device_t overrides
virtual const tiny_rom_entry *device_rom_region() const override;
void device_add_mconfig(machine_config &config) override;
// device_sbus_slot_interface overrides
virtual void install_device() override;
void mem_map(address_map &map) override;
};
class sbus_turbogxp_device : public sbus_cgsix_device
{
public:
sbus_turbogxp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
// device_t overrides
virtual const tiny_rom_entry *device_rom_region() const override;
void device_add_mconfig(machine_config &config) override;
// device_sbus_slot_interface overrides
virtual void install_device() override;
void mem_map(address_map &map) override;
};
DECLARE_DEVICE_TYPE(SBUS_TURBOGX, sbus_turbogx_device)
DECLARE_DEVICE_TYPE(SBUS_TURBOGXP, sbus_turbogxp_device)
#endif // MAME_BUS_SBUS_CGSIX_H

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src/devices/bus/sbus/cgthree.cpp
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@ -1,121 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Sun cgthree color video controller
***************************************************************************/
#include "emu.h"
#include "cgthree.h"
#include "screen.h"
DEFINE_DEVICE_TYPE(SBUS_CGTHREE, sbus_cgthree_device, "cgthree", "Sun cgthree SBus Video")
void sbus_cgthree_device::mem_map(address_map &map)
{
map(0x00000000, 0x01ffffff).rw(FUNC(sbus_cgthree_device::unknown_r), FUNC(sbus_cgthree_device::unknown_w));
map(0x00000000, 0x000007ff).r(FUNC(sbus_cgthree_device::rom_r));
map(0x00400000, 0x0040000f).m(m_ramdac, FUNC(bt458_device::map)).umask32(0xff000000);
map(0x007ff800, 0x007ff81f).rw(FUNC(sbus_cgthree_device::regs_r), FUNC(sbus_cgthree_device::regs_w));
map(0x00800000, 0x008fffff).rw(FUNC(sbus_cgthree_device::vram_r), FUNC(sbus_cgthree_device::vram_w));
map(0x00bff800, 0x00cff7ff).rw(FUNC(sbus_cgthree_device::vram_r), FUNC(sbus_cgthree_device::vram_w));
}
ROM_START( sbus_cgthree )
ROM_REGION32_BE(0x800, "prom", ROMREGION_ERASEFF)
ROM_LOAD( "sunw,501-1415.bin", 0x0000, 0x0800, CRC(d1eb6f4d) SHA1(9bef98b2784b6e70167337bb27cd07952b348b5a))
ROM_END
const tiny_rom_entry *sbus_cgthree_device::device_rom_region() const
{
return ROM_NAME( sbus_cgthree );
}
void sbus_cgthree_device::device_add_mconfig(machine_config &config)
{
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_screen_update(FUNC(sbus_cgthree_device::screen_update));
m_screen->set_raw(92.9405_MHz_XTAL, 1504, 0, 1152, 937, 0, 900);
BT458(config, m_ramdac, 0);
}
sbus_cgthree_device::sbus_cgthree_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, SBUS_CGTHREE, tag, owner, clock)
, device_sbus_card_interface(mconfig, *this)
, m_rom(*this, "prom")
, m_screen(*this, "screen")
, m_ramdac(*this, "ramdac")
{
}
void sbus_cgthree_device::device_start()
{
m_vram = std::make_unique<uint32_t[]>(0x100000/4);
save_pointer(NAME(m_vram), 0x100000/4);
}
void sbus_cgthree_device::device_reset()
{
}
void sbus_cgthree_device::install_device()
{
m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_cgthree_device::mem_map);
}
uint32_t sbus_cgthree_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
const pen_t *pens = m_ramdac->pens();
uint8_t *vram = (uint8_t *)&m_vram[0];
for (int y = 0; y < 900; y++)
{
uint32_t *scanline = &bitmap.pix32(y);
for (int x = 0; x < 1152; x++)
{
const uint8_t pixel = vram[y * 1152 + BYTE4_XOR_BE(x)];
*scanline++ = pens[pixel];
}
}
return 0;
}
READ32_MEMBER(sbus_cgthree_device::unknown_r)
{
logerror("%s: unknown_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask);
return 0;
}
WRITE32_MEMBER(sbus_cgthree_device::unknown_w)
{
logerror("%s: unknown_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
}
READ8_MEMBER(sbus_cgthree_device::regs_r)
{
logerror("%s: regs_r: Unimplemented: %08x\n", machine().describe_context(), 0x7ff800 + offset);
return 0;
}
WRITE8_MEMBER(sbus_cgthree_device::regs_w)
{
logerror("%s: regs_w: Unimplemented: %08x = %02x\n", machine().describe_context(), 0x7ff800 + offset, data);
}
READ32_MEMBER(sbus_cgthree_device::rom_r)
{
return ((uint32_t*)m_rom->base())[offset];
}
READ32_MEMBER(sbus_cgthree_device::vram_r)
{
return m_vram[offset];
}
WRITE32_MEMBER(sbus_cgthree_device::vram_w)
{
COMBINE_DATA(&m_vram[offset]);
}

58
src/devices/bus/sbus/cgthree.h
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@ -1,58 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Sun cgthree color video controller
***************************************************************************/
#ifndef MAME_BUS_SBUS_CGTHREE_H
#define MAME_BUS_SBUS_CGTHREE_H
#pragma once
#include "sbus.h"
#include "video/bt45x.h"
class sbus_cgthree_device : public device_t, public device_sbus_card_interface
{
public:
static constexpr feature_type imperfect_features() { return feature::GRAPHICS; }
// construction/destruction
sbus_cgthree_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
// device_t overrides
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual void device_start() override;
virtual void device_reset() override;
// device_sbus_slot_interface overrides
virtual void install_device() override;
DECLARE_READ32_MEMBER(unknown_r);
DECLARE_WRITE32_MEMBER(unknown_w);
DECLARE_WRITE32_MEMBER(palette_w);
DECLARE_READ8_MEMBER(regs_r);
DECLARE_WRITE8_MEMBER(regs_w);
DECLARE_READ32_MEMBER(rom_r);
DECLARE_READ32_MEMBER(vram_r);
DECLARE_WRITE32_MEMBER(vram_w);
private:
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
void mem_map(address_map &map) override;
required_memory_region m_rom;
std::unique_ptr<uint32_t[]> m_vram;
required_device<screen_device> m_screen;
required_device<bt458_device> m_ramdac;
};
DECLARE_DEVICE_TYPE(SBUS_CGTHREE, sbus_cgthree_device)
#endif // MAME_BUS_SBUS_CGTHREE_H

71
src/devices/bus/sbus/hme.cpp
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// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Sun SunSwift 10/100 + Fast Wide SCSI "Colossus" skeleton
Notable parts on board:
- 1x 32-pin PLCC ROM, label 525 / 1409 / -08 on separate lines
- 1x Sun STP2002QFP, marked 100-4156-05 / 609-0392458 / DP03972
- 1x National Semiconductor DP83840AVCE-1 Ethernet Physical Layer
- 1x National Semiconductor DP83223V Twisted Pair Transceiver
***************************************************************************/
#include "emu.h"
#include "hme.h"
DEFINE_DEVICE_TYPE(SBUS_HME, sbus_hme_device, "sbus_hme", "Sun 10/100 + Fast Wide SCSI")
void sbus_hme_device::mem_map(address_map &map)
{
map(0x00000000, 0x01ffffff).rw(FUNC(sbus_hme_device::unknown_r), FUNC(sbus_hme_device::unknown_w));
map(0x00000000, 0x0000ffff).r(FUNC(sbus_hme_device::rom_r));
}
ROM_START( sbus_hme )
ROM_REGION32_BE(0x10000, "prom", ROMREGION_ERASEFF)
ROM_LOAD( "525 1409 -08.bin", 0x00000, 0x10000, CRC(10f0b28f) SHA1(b54bb0f01c45accdbc58c3a86f8de34949374880))
ROM_END
const tiny_rom_entry *sbus_hme_device::device_rom_region() const
{
return ROM_NAME( sbus_hme );
}
void sbus_hme_device::device_add_mconfig(machine_config &config)
{
}
sbus_hme_device::sbus_hme_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, SBUS_HME, tag, owner, clock)
, device_sbus_card_interface(mconfig, *this)
, m_rom(*this, "prom")
{
}
void sbus_hme_device::device_start()
{
}
void sbus_hme_device::install_device()
{
m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_hme_device::mem_map);
}
READ32_MEMBER(sbus_hme_device::unknown_r)
{
logerror("%s: unknown_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask);
return 0;
}
WRITE32_MEMBER(sbus_hme_device::unknown_w)
{
logerror("%s: unknown_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
}
READ32_MEMBER(sbus_hme_device::rom_r)
{
return ((uint32_t*)m_rom->base())[offset];
}

45
src/devices/bus/sbus/hme.h
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// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Sun SunSwift 10/100 + Fast Wide SCSI "Colossus" skeleton
***************************************************************************/
#ifndef MAME_BUS_SBUS_HME_H
#define MAME_BUS_SBUS_HME_H
#pragma once
#include "sbus.h"
class sbus_hme_device : public device_t, public device_sbus_card_interface
{
public:
// construction/destruction
sbus_hme_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
// device_t overrides
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual void device_start() override;
// device_sbus_slot_interface overrides
virtual void install_device() override;
DECLARE_READ32_MEMBER(unknown_r);
DECLARE_WRITE32_MEMBER(unknown_w);
DECLARE_READ32_MEMBER(rom_r);
private:
void mem_map(address_map &map) override;
required_memory_region m_rom;
};
DECLARE_DEVICE_TYPE(SBUS_HME, sbus_hme_device)
#endif // MAME_BUS_SBUS_HME_H

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src/devices/bus/sbus/sbus.cpp
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// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
sbus.c - Sun SBus slot bus and card emulation
***************************************************************************/
#include "emu.h"
// Display boards
#include "bwtwo.h"
#include "cgthree.h"
#include "cgsix.h"
// Accelerator boards
#include "sunpc.h"
// Peripheral boards
#include "artecon.h"
#include "hme.h"
#include "sbus.h"
void sbus_cards(device_slot_interface &device)
{
device.option_add("bwtwo", SBUS_BWTWO); /* Sun bwtwo monochrome display board */
device.option_add("cgthree", SBUS_CGTHREE); /* Sun cgthree color display board */
device.option_add("turbogx", SBUS_TURBOGX); /* Sun TurboGX 8-bit color display board */
device.option_add("turbogxp", SBUS_TURBOGXP); /* Sun TurboGX+ 8-bit color display board */
device.option_add("sunpc", SBUS_SUNPC); /* Sun SunPC 5x86 Accelerator board */
device.option_add("hme", SBUS_HME); /* Sun SunSwift 10/100 + Fast Wide SCSI "Colossus" board */
device.option_add("sb300p", SBUS_SB300P); /* Artecon CB300P 3-serial/1-parallel board */
}
DEFINE_DEVICE_TYPE(SBUS_SLOT, sbus_slot_device, "sbus_slot", "Sun SBus Slot")
sbus_slot_device::sbus_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: sbus_slot_device(mconfig, SBUS_SLOT, tag, owner, clock)
{
}
sbus_slot_device::sbus_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, type, tag, owner, clock)
, device_slot_interface(mconfig, *this)
, m_sbus(*this, finder_base::DUMMY_TAG)
{
}
void sbus_slot_device::device_validity_check(validity_checker &valid) const
{
device_t *const card(get_card_device());
if (card && !dynamic_cast<device_sbus_card_interface *>(card))
osd_printf_error("Card device %s (%s) does not implement device_sbus_card_interface\n", card->tag(), card->name());
}
void sbus_slot_device::device_resolve_objects()
{
device_sbus_card_interface *const sbus_card(dynamic_cast<device_sbus_card_interface *>(get_card_device()));
if (sbus_card)
sbus_card->set_sbus(m_sbus, tag());
}
void sbus_slot_device::device_start()
{
device_t *const card(get_card_device());
if (card && !dynamic_cast<device_sbus_card_interface *>(card))
throw emu_fatalerror("sbus_slot_device: card device %s (%s) does not implement device_sbus_card_interface\n", card->tag(), card->name());
}
DEFINE_DEVICE_TYPE(SBUS, sbus_device, "sbus", "Sun SBus")
device_memory_interface::space_config_vector sbus_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(0, &m_space_config)
};
}
sbus_device::sbus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: sbus_device(mconfig, SBUS, tag, owner, clock)
{
}
sbus_device::sbus_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, type, tag, owner, clock)
, device_memory_interface(mconfig, *this)
, m_space_config("SBus Space", ENDIANNESS_BIG, 32, 32, 0, address_map_constructor())
, m_maincpu(*this, finder_base::DUMMY_TAG)
, m_type1space(*this, finder_base::DUMMY_TAG)
, m_irq_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}}
, m_buserr(*this)
{
}
void sbus_device::device_resolve_objects()
{
// resolve callbacks
for (int i = 0; i < 7; i++)
m_irq_cb[i].resolve_safe();
m_buserr.resolve_safe();
}
void sbus_device::device_start()
{
std::fill(std::begin(m_device_list), std::end(m_device_list), nullptr);
m_space = &space(0);
m_space->install_readwrite_handler(0x00000000, 0x01ffffff, read32_delegate(FUNC(sbus_device::slot_timeout_r<0>), this), write32_delegate(FUNC(sbus_device::slot_timeout_w<0>), this));
m_space->install_readwrite_handler(0x02000000, 0x03ffffff, read32_delegate(FUNC(sbus_device::slot_timeout_r<1>), this), write32_delegate(FUNC(sbus_device::slot_timeout_w<1>), this));
m_space->install_readwrite_handler(0x04000000, 0x05ffffff, read32_delegate(FUNC(sbus_device::slot_timeout_r<2>), this), write32_delegate(FUNC(sbus_device::slot_timeout_w<2>), this));
}
template <unsigned Slot> READ32_MEMBER(sbus_device::slot_timeout_r)
{
m_maincpu->set_mae();
m_buserr(0, 0x20);
m_buserr(1, 0xffa00000 + (Slot << 21));
return 0;
}
template <unsigned Slot> WRITE32_MEMBER(sbus_device::slot_timeout_w)
{
m_maincpu->set_mae();
m_buserr(0, 0x8020);
m_buserr(1, 0xffa00000 + (Slot << 21));
}
READ32_MEMBER(sbus_device::read)
{
return m_space->read_dword(offset << 2, mem_mask);
}
WRITE32_MEMBER(sbus_device::write)
{
m_space->write_dword(offset << 2, data, mem_mask);
}
device_sbus_card_interface *sbus_device::get_sbus_card(int slot)
{
if (slot < 0)
{
return nullptr;
}
if (m_device_list[slot])
{
return m_device_list[slot];
}
return nullptr;
}
void sbus_device::add_sbus_card(int slot, device_sbus_card_interface *card)
{
m_device_list[slot] = card;
card->install_device();
}
void sbus_device::set_irq_line(int state, int line)
{
m_irq_cb[line](state);
}
device_sbus_card_interface::device_sbus_card_interface(const machine_config &mconfig, device_t &device)
: device_slot_card_interface(mconfig, device)
, m_sbus_finder(device, finder_base::DUMMY_TAG)
, m_sbus(nullptr)
, m_sbus_slottag(nullptr)
, m_slot(-1)
, m_base(0)
{
}
device_sbus_card_interface::~device_sbus_card_interface()
{
}
void device_sbus_card_interface::interface_validity_check(validity_checker &valid) const
{
if (m_sbus_finder && m_sbus && (m_sbus != m_sbus_finder))
osd_printf_error("Contradictory buses configured (%s and %s)\n", m_sbus_finder->tag(), m_sbus->tag());
}
void device_sbus_card_interface::interface_pre_start()
{
device_slot_card_interface::interface_pre_start();
if (!m_sbus)
{
m_sbus = m_sbus_finder;
if (!m_sbus)
fatalerror("Can't find Sun SBus device %s\n", m_sbus_finder.finder_tag());
}
if (0 > m_slot)
{
if (!m_sbus->started())
throw device_missing_dependencies();
// extract the slot number from the last digit of the slot tag
size_t const tlen = strlen(m_sbus_slottag);
m_slot = (m_sbus_slottag[tlen - 1] - '1');
if (m_slot < 0 || m_slot > 2)
fatalerror("Slot %x out of range for Sun SBus\n", m_slot);
m_base = m_slot << 25;
m_sbus->add_sbus_card(m_slot, this);
}
}
void device_sbus_card_interface::set_sbus(sbus_device *sbus, const char *slottag)
{
m_sbus = sbus;
m_sbus_slottag = slottag;
}

160
src/devices/bus/sbus/sbus.h
View File

@ -1,160 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
sbus.h - Sun SBus slot bus and card emulation
***************************************************************************/
#ifndef MAME_BUS_SBUS_SBUS_H
#define MAME_BUS_SBUS_SBUS_H
#pragma once
#include "cpu/sparc/sparc.h"
#include "machine/bankdev.h"
class sbus_device;
class sbus_slot_device : public device_t, public device_slot_interface
{
public:
// construction/destruction
template <typename T, typename U>
sbus_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&sbus_tag, U &&opts, const char *dflt, bool fixed = false)
: sbus_slot_device(mconfig, tag, owner, clock)
{
option_reset();
opts(*this);
set_default_option(dflt);
set_fixed(fixed);
m_sbus.set_tag(std::forward<T>(sbus_tag));
}
sbus_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
sbus_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
// device-level overrides
virtual void device_validity_check(validity_checker &valid) const override;
virtual void device_resolve_objects() override;
virtual void device_start() override;
// configuration
required_device<sbus_device> m_sbus;
DECLARE_READ32_MEMBER(timeout_r);
DECLARE_WRITE32_MEMBER(timeout_w);
};
DECLARE_DEVICE_TYPE(SBUS_SLOT, sbus_slot_device)
class device_sbus_card_interface;
class sbus_device : public device_t,
public device_memory_interface
{
friend class device_sbus_card_interface;
public:
// construction/destruction
template <typename T, typename U>
sbus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag, U &&space_tag)
: sbus_device(mconfig, tag, owner, clock)
{
set_cpu_tag(std::forward<T>(cpu_tag));
set_space_tag(std::forward<U>(space_tag));
}
sbus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// inline configuration
template <typename T> void set_cpu_tag(T &&tag) { m_maincpu.set_tag(std::forward<T>(tag)); }
template <typename T> void set_space_tag(T &&tag) { m_type1space.set_tag(std::forward<T>(tag)); }
// devcb3
template <unsigned Line> auto irq() { return m_irq_cb[Line].bind(); }
auto buserr() { return m_buserr.bind(); }
virtual space_config_vector memory_space_config() const override;
const address_space_config m_space_config;
void add_sbus_card(int slot, device_sbus_card_interface *card);
device_sbus_card_interface *get_sbus_card(int slot);
void set_irq_line(int state, int line);
template<typename T> void install_device(offs_t addrstart, offs_t addrend, T &device, void (T::*map)(class address_map &map), uint64_t unitmask = ~u64(0))
{
m_space->install_device(addrstart, addrend, device, map, unitmask);
}
DECLARE_READ32_MEMBER(read);
DECLARE_WRITE32_MEMBER(write);
protected:
sbus_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
// device-level overrides
virtual void device_resolve_objects() override;
virtual void device_start() override;
// internal state
required_device<mb86901_device> m_maincpu;
required_device<address_map_bank_device> m_type1space;
address_space *m_space;
devcb_write_line m_irq_cb[7];
devcb_write32 m_buserr;
device_sbus_card_interface *m_device_list[3];
private:
void slot1_timeout_map(address_map &map);
void slot2_timeout_map(address_map &map);
void slot3_timeout_map(address_map &map);
template <unsigned Slot> DECLARE_READ32_MEMBER(slot_timeout_r);
template <unsigned Slot> DECLARE_WRITE32_MEMBER(slot_timeout_w);
};
DECLARE_DEVICE_TYPE(SBUS, sbus_device)
// class representing interface-specific live sbus card
class device_sbus_card_interface : public device_slot_card_interface
{
friend class sbus_device;
public:
// construction/destruction
virtual ~device_sbus_card_interface();
// inline configuration
void set_sbus(sbus_device *sbus, const char *slottag);
template <typename T> void set_onboard(T &&sbus) { m_sbus_finder.set_tag(std::forward<T>(sbus)); m_sbus_slottag = device().tag(); }
virtual void mem_map(address_map &map) = 0;
protected:
void raise_irq(int line) { m_sbus->set_irq_line(ASSERT_LINE, line); }
void lower_irq(int line) { m_sbus->set_irq_line(CLEAR_LINE, line); }
device_sbus_card_interface(const machine_config &mconfig, device_t &device);
virtual void interface_validity_check(validity_checker &valid) const override;
virtual void interface_pre_start() override;
virtual void install_device() = 0;
sbus_device &sbus() { assert(m_sbus); return *m_sbus; }
optional_device<sbus_device> m_sbus_finder;
sbus_device *m_sbus;
const char *m_sbus_slottag;
int m_slot;
uint32_t m_base;
};
void sbus_cards(device_slot_interface &device);
#endif // MAME_BUS_SBUS_SBUS_H

71
src/devices/bus/sbus/sunpc.cpp
View File

@ -1,71 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Sun SunPC 5x86 Accelerator (501-4230) skeleton
Notable parts on board:
- 1x AMD AM27C256 PLCC ROM
- 1x Motorola SunPC Accelerator 100-3069-03, mfr/date AANL9732
- 6x Cypress CY7B185-10VC 64kBit Static RAM
- 1x AMD 5x86 (under heatsink; markings unknown)
***************************************************************************/
#include "emu.h"
#include "sunpc.h"
DEFINE_DEVICE_TYPE(SBUS_SUNPC, sbus_sunpc_device, "sbus_sunpc", "Sun SunPC accelerator")
void sbus_sunpc_device::mem_map(address_map &map)
{
map(0x00000000, 0x01ffffff).rw(FUNC(sbus_sunpc_device::unknown_r), FUNC(sbus_sunpc_device::unknown_w));
map(0x00000000, 0x00007fff).r(FUNC(sbus_sunpc_device::rom_r));
}
ROM_START( sbus_sunpc )
ROM_REGION32_BE(0x8000, "prom", ROMREGION_ERASEFF)
ROM_LOAD( "sunw,501-1763-01.bin", 0x0000, 0x8000, CRC(171f50f8) SHA1(21c4c02bc5a3a0494301f19c54ba0e207568fb42))
ROM_END
const tiny_rom_entry *sbus_sunpc_device::device_rom_region() const
{
return ROM_NAME( sbus_sunpc );
}
void sbus_sunpc_device::device_add_mconfig(machine_config &config)
{
}
sbus_sunpc_device::sbus_sunpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, SBUS_SUNPC, tag, owner, clock)
, device_sbus_card_interface(mconfig, *this)
, m_rom(*this, "prom")
{
}
void sbus_sunpc_device::device_start()
{
}
void sbus_sunpc_device::install_device()
{
m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_sunpc_device::mem_map);
}
READ32_MEMBER(sbus_sunpc_device::unknown_r)
{
logerror("%s: unknown_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask);
return 0;
}
WRITE32_MEMBER(sbus_sunpc_device::unknown_w)
{
logerror("%s: unknown_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
}
READ32_MEMBER(sbus_sunpc_device::rom_r)
{
return ((uint32_t*)m_rom->base())[offset];
}

45
src/devices/bus/sbus/sunpc.h
View File

@ -1,45 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/***************************************************************************
Sun SunPC 5x86 Accelerator (501-4230) skeleton
***************************************************************************/
#ifndef MAME_BUS_SBUS_SUNPC_H
#define MAME_BUS_SBUS_SUNPC_H
#pragma once
#include "sbus.h"
class sbus_sunpc_device : public device_t, public device_sbus_card_interface
{
public:
// construction/destruction
sbus_sunpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
// device_t overrides
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_add_mconfig(machine_config &config) override;
virtual void device_start() override;
// device_sbus_slot_interface overrides
virtual void install_device() override;
DECLARE_READ32_MEMBER(unknown_r);
DECLARE_WRITE32_MEMBER(unknown_w);
DECLARE_READ32_MEMBER(rom_r);
private:
void mem_map(address_map &map) override;
required_memory_region m_rom;
};
DECLARE_DEVICE_TYPE(SBUS_SUNPC, sbus_sunpc_device)
#endif // MAME_BUS_SBUS_SUNPC_H

17
src/mame/drivers/indy_indigo2.cpp
View File

@ -54,8 +54,6 @@
#include "emu.h"
#include "bus/gio64/gio64.h"
#include "cpu/mips/r4000.h"
#include "machine/hpc3.h"
@ -81,10 +79,6 @@ public:
, m_scsi_ctrl(*this, "scsibus:0:wd33c93")
, m_hpc3(*this, "hpc3")
, m_vino(*this, "vino")
, m_gio64(*this, "gio64")
, m_gio64_gfx(*this, "gio64_gfx")
, m_gio64_exp0(*this, "gio64_exp0")
, m_gio64_exp1(*this, "gio64_exp1")
{
}
@ -111,10 +105,6 @@ protected:
required_device<wd33c93b_device> m_scsi_ctrl;
required_device<hpc3_base_device> m_hpc3;
optional_device<vino_device> m_vino;
optional_device<gio64_device> m_gio64;
optional_device<gio64_slot_device> m_gio64_gfx;
optional_device<gio64_slot_device> m_gio64_exp0;
optional_device<gio64_slot_device> m_gio64_exp1;
};
class ip24_state : public ip22_state
@ -172,7 +162,6 @@ void ip22_state::ip22_base_map(address_map &map)
{
map(0x00000000, 0x0007ffff).bankrw("bank1"); /* mirror of first 512k of main RAM */
map(0x08000000, 0x0fffffff).share("mainram").ram().w(FUNC(ip22_state::write_ram)); /* 128 MB of main RAM */
map(0x1f000000, 0x1f9fffff).rw(m_gio64, FUNC(gio64_device::read), FUNC(gio64_device::write));
map(0x1fa00000, 0x1fa1ffff).rw(m_mem_ctrl, FUNC(sgi_mc_device::read), FUNC(sgi_mc_device::write));
map(0x1fb00000, 0x1fb7ffff).r(FUNC(ip22_state::bus_error));
map(0x1fb80000, 0x1fbfffff).m(m_hpc3, FUNC(hpc3_base_device::map));
@ -243,12 +232,6 @@ void ip22_state::ip22_base(machine_config &config)
NSCSI_CONNECTOR(config, "scsibus:5", scsi_devices, nullptr, false);
NSCSI_CONNECTOR(config, "scsibus:6", scsi_devices, "cdrom", false);
NSCSI_CONNECTOR(config, "scsibus:7", scsi_devices, nullptr, false);
// GIO64
GIO64(config, m_gio64, m_maincpu, m_hpc3);
GIO64_SLOT(config, m_gio64_gfx, m_gio64, gio64_cards, "xl24");
GIO64_SLOT(config, m_gio64_exp0, m_gio64, gio64_cards, nullptr);
GIO64_SLOT(config, m_gio64_exp1, m_gio64, gio64_cards, nullptr);
}
void ip22_state::ip225015(machine_config &config)

46
src/mame/drivers/sun4.cpp
View File

@ -414,8 +414,6 @@
#include "bus/rs232/rs232.h"
#include "bus/sunkbd/sunkbd.h"
#include "bus/sunmouse/sunmouse.h"
#include "bus/sbus/sbus.h"
#include "bus/sbus/bwtwo.h"
#include "cpu/sparc/sparc.h"
#include "imagedev/floppy.h"
#include "machine/am79c90.h"
@ -541,8 +539,6 @@ public:
, m_lance(*this, LANCE_TAG)
, m_scsibus(*this, "scsibus")
, m_scsi(*this, "scsibus:7:ncr53c90a")
, m_sbus(*this, "sbus")
, m_sbus_slot(*this, "slot%u", 1U)
, m_type0space(*this, "type0")
, m_type1space(*this, "type1")
, m_ram(*this, RAM_TAG)
@ -658,7 +654,6 @@ private:
void type0space_map(address_map &map);
void type1space_map(address_map &map);
void type1space_sbus_map(address_map &map);
void type1space_s4_map(address_map &map);
enum sun4_arch
@ -681,8 +676,6 @@ private:
required_device<nscsi_bus_device> m_scsibus;
required_device<ncr53c90a_device> m_scsi;
optional_device<sbus_device> m_sbus;
optional_device_array<sbus_slot_device, 3> m_sbus_slot;
optional_device<address_map_bank_device> m_type0space;
optional_device<address_map_bank_device> m_type1space;
memory_access_cache<2, 0, ENDIANNESS_BIG> *m_type1_cache;
@ -1159,12 +1152,6 @@ void sun4_state::type1space_map(address_map &map)
map(0x08c00000, 0x08c00003).rw(m_lance, FUNC(am79c90_device::regs_r), FUNC(am79c90_device::regs_w));
}
void sun4_state::type1space_sbus_map(address_map &map)
{
type1space_map(map);
map(0x0a000000, 0x0fffffff).rw(m_sbus, FUNC(sbus_device::read), FUNC(sbus_device::write));
}
void sun4_state::type1space_s4_map(address_map &map)
{
map(0x00000000, 0x0000000f).rw(m_scc1, FUNC(z80scc_device::ba_cd_inv_r), FUNC(z80scc_device::ba_cd_inv_w)).umask32(0xff00ff00);
@ -1962,7 +1949,7 @@ void sun4_state::sun4c(machine_config &config)
ADDRESS_MAP_BANK(config, m_type0space).set_map(&sun4_state::type0space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// MMU Type 1 device space
ADDRESS_MAP_BANK(config, m_type1space).set_map(&sun4_state::type1space_sbus_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
ADDRESS_MAP_BANK(config, m_type1space).set_map(&sun4_state::type1space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// Ethernet
AM79C90(config, m_lance);
@ -2014,12 +2001,6 @@ void sun4_state::sun4c(machine_config &config)
NSCSI_CONNECTOR(config, "scsibus:5", sun_scsi_devices, nullptr);
NSCSI_CONNECTOR(config, "scsibus:6", sun_scsi_devices, nullptr);
NSCSI_CONNECTOR(config, "scsibus:7", sun_scsi_devices, "ncr53c90a", true).set_option_machine_config("ncr53c90a", [this] (device_t *device) { ncr53c90a(device); });
// SBus
SBUS(config, m_sbus, 20'000'000, "maincpu", "type1");
SBUS_SLOT(config, m_sbus_slot[0], 20'000'000, m_sbus, sbus_cards, nullptr);
SBUS_SLOT(config, m_sbus_slot[1], 20'000'000, m_sbus, sbus_cards, nullptr);
SBUS_SLOT(config, m_sbus_slot[2], 20'000'000, m_sbus, sbus_cards, nullptr);
}
void sun4_state::sun4_20(machine_config &config)
@ -2027,11 +2008,6 @@ void sun4_state::sun4_20(machine_config &config)
sun4c(config);
m_ram->set_extra_options("4M,8M,12M,16M");
m_sbus_slot[0]->set_fixed(true);
m_sbus_slot[1]->set_fixed(true);
m_sbus_slot[2]->set_default_option("bwtwo");
m_sbus_slot[2]->set_fixed(true);
}
void sun4_state::sun4_40(machine_config &config)
@ -2042,13 +2018,6 @@ void sun4_state::sun4_40(machine_config &config)
m_mmu->set_clock(25'000'000);
m_maincpu->set_clock(25'000'000);
m_sbus->set_clock(25'000'000);
m_sbus_slot[0]->set_clock(25'000'000);
m_sbus_slot[1]->set_clock(25'000'000);
m_sbus_slot[2]->set_clock(25'000'000);
m_sbus_slot[2]->set_default_option("bwtwo");
m_sbus_slot[2]->set_fixed(true);
}
void sun4_state::sun4_50(machine_config &config)
@ -2060,13 +2029,6 @@ void sun4_state::sun4_50(machine_config &config)
m_mmu->set_clock(40'000'000);
m_maincpu->set_clock(40'000'000);
m_sbus->set_clock(20'000'000);
m_sbus_slot[0]->set_clock(20'000'000);
m_sbus_slot[1]->set_clock(20'000'000);
m_sbus_slot[2]->set_clock(20'000'000);
m_sbus_slot[2]->set_default_option("turbogx"); // not accurate, should be gxp, not turbogx
m_sbus_slot[2]->set_fixed(true);
}
void sun4_state::sun4_60(machine_config &config)
@ -2080,12 +2042,6 @@ void sun4_state::sun4_65(machine_config &config)
m_mmu->set_clock(25'000'000);
m_maincpu->set_clock(25'000'000);
m_sbus->set_clock(25'000'000);
m_sbus_slot[0]->set_clock(25'000'000);
m_sbus_slot[1]->set_clock(25'000'000);
m_sbus_slot[2]->set_clock(25'000'000);
m_sbus_slot[2]->set_default_option("bwtwo");
}
void sun4_state::sun4_75(machine_config &config)