mirror of
https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
some more handlers simplified (nw)
This commit is contained in:
parent
e2ddb46215
commit
320b2f66b0
@ -97,7 +97,7 @@ READ8_MEMBER(a1bus_cffa_device::cffa_r)
|
||||
break;
|
||||
|
||||
case 0x8:
|
||||
m_lastdata = m_ata->read_cs0((offset & 0xf) - 8, 0xff);
|
||||
m_lastdata = m_ata->cs0_r((offset & 0xf) - 8, 0xff);
|
||||
return m_lastdata & 0x00ff;
|
||||
|
||||
case 0x9:
|
||||
@ -107,7 +107,7 @@ READ8_MEMBER(a1bus_cffa_device::cffa_r)
|
||||
case 0xd:
|
||||
case 0xe:
|
||||
case 0xf:
|
||||
return m_ata->read_cs0((offset & 0xf) - 8, 0xff);
|
||||
return m_ata->cs0_r((offset & 0xf) - 8, 0xff);
|
||||
}
|
||||
|
||||
return 0xff;
|
||||
@ -132,7 +132,7 @@ WRITE8_MEMBER(a1bus_cffa_device::cffa_w)
|
||||
|
||||
|
||||
case 0x8:
|
||||
m_ata->write_cs0((offset & 0xf) - 8, data, 0xff);
|
||||
m_ata->cs0_w((offset & 0xf) - 8, data, 0xff);
|
||||
break;
|
||||
|
||||
case 0x9:
|
||||
@ -142,7 +142,7 @@ WRITE8_MEMBER(a1bus_cffa_device::cffa_w)
|
||||
case 0xd:
|
||||
case 0xe:
|
||||
case 0xf:
|
||||
m_ata->write_cs0((offset & 0xf) - 8, data, 0xff);
|
||||
m_ata->cs0_w((offset & 0xf) - 8, data, 0xff);
|
||||
break;
|
||||
|
||||
}
|
||||
|
@ -145,7 +145,7 @@ uint8_t a2bus_cffa2000_device::read_c0nx(uint8_t offset)
|
||||
// Apple /// driver uses sta $c080,x when writing, which causes spurious reads of c088
|
||||
if (!m_inwritecycle)
|
||||
{
|
||||
m_lastreaddata = m_ata->read_cs0(offset - 8);
|
||||
m_lastreaddata = m_ata->cs0_r(offset - 8);
|
||||
}
|
||||
return m_lastreaddata & 0xff;
|
||||
|
||||
@ -156,7 +156,7 @@ uint8_t a2bus_cffa2000_device::read_c0nx(uint8_t offset)
|
||||
case 0xd:
|
||||
case 0xe:
|
||||
case 0xf:
|
||||
return m_ata->read_cs0(offset-8, 0xff);
|
||||
return m_ata->cs0_r(offset-8, 0xff);
|
||||
}
|
||||
|
||||
return 0xff;
|
||||
@ -192,7 +192,7 @@ void a2bus_cffa2000_device::write_c0nx(uint8_t offset, uint8_t data)
|
||||
m_lastdata &= 0xff00;
|
||||
m_lastdata |= data;
|
||||
// printf("%02x to 8, m_lastdata = %x\n", data, m_lastdata);
|
||||
m_ata->write_cs0(offset-8, m_lastdata);
|
||||
m_ata->cs0_w(offset-8, m_lastdata);
|
||||
break;
|
||||
|
||||
case 9:
|
||||
@ -202,7 +202,7 @@ void a2bus_cffa2000_device::write_c0nx(uint8_t offset, uint8_t data)
|
||||
case 0xd:
|
||||
case 0xe:
|
||||
case 0xf:
|
||||
m_ata->write_cs0(offset-8, data, 0xff);
|
||||
m_ata->cs0_w(offset-8, data, 0xff);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -191,7 +191,7 @@ uint8_t a2bus_vulcanbase_device::read_c0nx(uint8_t offset)
|
||||
switch (offset)
|
||||
{
|
||||
case 0:
|
||||
m_lastdata = m_ata->read_cs0(offset);
|
||||
m_lastdata = m_ata->cs0_r(offset);
|
||||
// printf("IDE: read %04x\n", m_lastdata);
|
||||
m_last_read_was_0 = true;
|
||||
return m_lastdata&0xff;
|
||||
@ -204,7 +204,7 @@ uint8_t a2bus_vulcanbase_device::read_c0nx(uint8_t offset)
|
||||
}
|
||||
else
|
||||
{
|
||||
return m_ata->read_cs0(offset, 0xff);
|
||||
return m_ata->cs0_r(offset, 0xff);
|
||||
}
|
||||
|
||||
case 2:
|
||||
@ -213,7 +213,7 @@ uint8_t a2bus_vulcanbase_device::read_c0nx(uint8_t offset)
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
return m_ata->read_cs0(offset, 0xff);
|
||||
return m_ata->cs0_r(offset, 0xff);
|
||||
|
||||
default:
|
||||
logerror("a2vulcan: unknown read @ C0n%x\n", offset);
|
||||
@ -245,11 +245,11 @@ void a2bus_vulcanbase_device::write_c0nx(uint8_t offset, uint8_t data)
|
||||
m_lastdata &= 0x00ff;
|
||||
m_lastdata |= (data << 8);
|
||||
// printf("IDE: write %04x\n", m_lastdata);
|
||||
m_ata->write_cs0(0, m_lastdata);
|
||||
m_ata->cs0_w(0, m_lastdata);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ata->write_cs0(offset, data, 0xff);
|
||||
m_ata->cs0_w(offset, data, 0xff);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -260,7 +260,7 @@ void a2bus_vulcanbase_device::write_c0nx(uint8_t offset, uint8_t data)
|
||||
case 6:
|
||||
case 7:
|
||||
// printf("%02x to IDE controller @ %x\n", data, offset);
|
||||
m_ata->write_cs0(offset, data, 0xff);
|
||||
m_ata->cs0_w(offset, data, 0xff);
|
||||
break;
|
||||
|
||||
case 9: // ROM bank
|
||||
|
@ -175,10 +175,10 @@ uint8_t a2bus_zipdrivebase_device::read_c0nx(uint8_t offset)
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
return m_ata->read_cs0(offset, 0xff);
|
||||
return m_ata->cs0_r(offset, 0xff);
|
||||
|
||||
case 8: // data port
|
||||
m_lastdata = m_ata->read_cs0(0, 0xffff);
|
||||
m_lastdata = m_ata->cs0_r(0, 0xffff);
|
||||
// printf("%04x @ IDE data\n", m_lastdata);
|
||||
return m_lastdata&0xff;
|
||||
|
||||
@ -205,10 +205,10 @@ uint8_t a2bus_focusdrive_device::read_c0nx(uint8_t offset)
|
||||
case 0xd:
|
||||
case 0xe:
|
||||
case 0xf:
|
||||
return m_ata->read_cs0(offset&7, 0xff);
|
||||
return m_ata->cs0_r(offset&7, 0xff);
|
||||
|
||||
case 0: // data port
|
||||
m_lastdata = m_ata->read_cs0(0, 0xffff);
|
||||
m_lastdata = m_ata->cs0_r(0, 0xffff);
|
||||
//printf("%04x @ IDE data\n", m_lastdata);
|
||||
return m_lastdata&0xff;
|
||||
|
||||
@ -240,7 +240,7 @@ void a2bus_zipdrivebase_device::write_c0nx(uint8_t offset, uint8_t data)
|
||||
case 6:
|
||||
case 7:
|
||||
// printf("%02x to IDE controller @ %x\n", data, offset);
|
||||
m_ata->write_cs0(offset, data, 0xff);
|
||||
m_ata->cs0_w(offset, data, 0xff);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
@ -252,7 +252,7 @@ void a2bus_zipdrivebase_device::write_c0nx(uint8_t offset, uint8_t data)
|
||||
// printf("%02x to IDE data hi\n", data);
|
||||
m_lastdata &= 0x00ff;
|
||||
m_lastdata |= (data << 8);
|
||||
m_ata->write_cs0(0, m_lastdata, 0xffff);
|
||||
m_ata->cs0_w(0, m_lastdata, 0xffff);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -275,14 +275,14 @@ void a2bus_focusdrive_device::write_c0nx(uint8_t offset, uint8_t data)
|
||||
case 0xf:
|
||||
// due to a bug in the 6502 firmware, eat data if DRQ is set
|
||||
#if 0
|
||||
while (m_ata->read_cs0(7, 0xff) & 0x08)
|
||||
while (m_ata->cs0_r(7, 0xff) & 0x08)
|
||||
{
|
||||
m_ata->read_cs0(0, 0xffff);
|
||||
m_ata->cs0_r(0, 0xffff);
|
||||
printf("eating 2 bytes to clear DRQ\n");
|
||||
}
|
||||
#endif
|
||||
// printf("%02x to IDE controller @ %x\n", data, offset);
|
||||
m_ata->write_cs0(offset & 7, data, 0xff);
|
||||
m_ata->cs0_w(offset & 7, data, 0xff);
|
||||
break;
|
||||
|
||||
case 0:
|
||||
@ -294,7 +294,7 @@ void a2bus_focusdrive_device::write_c0nx(uint8_t offset, uint8_t data)
|
||||
// printf("%02x to IDE data hi\n", data);
|
||||
m_lastdata &= 0x00ff;
|
||||
m_lastdata |= (data << 8);
|
||||
m_ata->write_cs0(0, m_lastdata, 0xffff);
|
||||
m_ata->cs0_w(0, m_lastdata, 0xffff);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
@ -116,7 +116,7 @@ uint8_t powermate_ide_device::adam_bd_r(offs_t offset, uint8_t data, int bmreq,
|
||||
case 0x05:
|
||||
case 0x06:
|
||||
case 0x07:
|
||||
data = m_ata->read_cs0(offset & 0x07, 0xff);
|
||||
data = m_ata->cs0_r(offset & 0x07, 0xff);
|
||||
break;
|
||||
|
||||
case 0x40: // Printer status
|
||||
@ -137,7 +137,7 @@ uint8_t powermate_ide_device::adam_bd_r(offs_t offset, uint8_t data, int bmreq,
|
||||
break;
|
||||
|
||||
case 0x58:
|
||||
m_ata_data = m_ata->read_cs0(0);
|
||||
m_ata_data = m_ata->cs0_r(0);
|
||||
|
||||
data = m_ata_data & 0xff;
|
||||
break;
|
||||
@ -147,7 +147,7 @@ uint8_t powermate_ide_device::adam_bd_r(offs_t offset, uint8_t data, int bmreq,
|
||||
break;
|
||||
|
||||
case 0x5a:
|
||||
data = m_ata->read_cs1(6, 0xff);
|
||||
data = m_ata->cs1_r(6, 0xff);
|
||||
break;
|
||||
|
||||
case 0x5b: // Digital Input Register
|
||||
@ -176,7 +176,7 @@ void powermate_ide_device::adam_bd_w(offs_t offset, uint8_t data, int bmreq, int
|
||||
case 0x05:
|
||||
case 0x06:
|
||||
case 0x07:
|
||||
m_ata->write_cs0(offset & 0x07, data, 0xff);
|
||||
m_ata->cs0_w(offset & 0x07, data, 0xff);
|
||||
break;
|
||||
|
||||
case 0x40:
|
||||
@ -188,7 +188,7 @@ void powermate_ide_device::adam_bd_w(offs_t offset, uint8_t data, int bmreq, int
|
||||
|
||||
case 0x58:
|
||||
m_ata_data |= data;
|
||||
m_ata->write_cs0(0, m_ata_data);
|
||||
m_ata->cs0_w(0, m_ata_data);
|
||||
break;
|
||||
|
||||
case 0x59:
|
||||
|
@ -248,7 +248,7 @@ WRITE16_MEMBER( buddha_device::ide_interrupt_enable_w )
|
||||
|
||||
READ16_MEMBER( buddha_device::ide_0_cs0_r )
|
||||
{
|
||||
uint16_t data = m_ata_0->read_cs0((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
|
||||
uint16_t data = m_ata_0->cs0_r((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
|
||||
data = (data << 8) | (data >> 8);
|
||||
|
||||
LOG("ide_0_cs0_r(%04x) %04x [mask = %04x]\n", offset, data, mem_mask);
|
||||
@ -263,12 +263,12 @@ WRITE16_MEMBER( buddha_device::ide_0_cs0_w )
|
||||
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
|
||||
data = (data << 8) | (data >> 8);
|
||||
|
||||
m_ata_0->write_cs0((offset >> 1) & 0x07, data, mem_mask);
|
||||
m_ata_0->cs0_w((offset >> 1) & 0x07, data, mem_mask);
|
||||
}
|
||||
|
||||
READ16_MEMBER( buddha_device::ide_0_cs1_r )
|
||||
{
|
||||
uint16_t data = m_ata_0->read_cs1((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
|
||||
uint16_t data = m_ata_0->cs1_r((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
|
||||
data = (data << 8) | (data >> 8);
|
||||
|
||||
LOG("ide_0_cs1_r(%04x) %04x [mask = %04x]\n", offset, data, mem_mask);
|
||||
@ -283,12 +283,12 @@ WRITE16_MEMBER( buddha_device::ide_0_cs1_w )
|
||||
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
|
||||
data = (data << 8) | (data >> 8);
|
||||
|
||||
m_ata_0->write_cs1((offset >> 1) & 0x07, data, mem_mask);
|
||||
m_ata_0->cs1_w((offset >> 1) & 0x07, data, mem_mask);
|
||||
}
|
||||
|
||||
READ16_MEMBER( buddha_device::ide_1_cs0_r )
|
||||
{
|
||||
uint16_t data = m_ata_1->read_cs0((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
|
||||
uint16_t data = m_ata_1->cs0_r((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
|
||||
data = (data << 8) | (data >> 8);
|
||||
|
||||
LOG("ide_1_cs0_r(%04x) %04x [mask = %04x]\n", offset, data, mem_mask);
|
||||
@ -303,12 +303,12 @@ WRITE16_MEMBER( buddha_device::ide_1_cs0_w )
|
||||
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
|
||||
data = (data << 8) | (data >> 8);
|
||||
|
||||
m_ata_1->write_cs0((offset >> 1) & 0x07, data, mem_mask);
|
||||
m_ata_1->cs0_w((offset >> 1) & 0x07, data, mem_mask);
|
||||
}
|
||||
|
||||
READ16_MEMBER( buddha_device::ide_1_cs1_r )
|
||||
{
|
||||
uint16_t data = m_ata_1->read_cs1((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
|
||||
uint16_t data = m_ata_1->cs1_r((offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
|
||||
data = (data << 8) | (data >> 8);
|
||||
|
||||
LOG("ide_1_cs1_r(%04x) %04x [mask = %04x]\n", offset, data, mem_mask);
|
||||
@ -323,7 +323,7 @@ WRITE16_MEMBER( buddha_device::ide_1_cs1_w )
|
||||
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
|
||||
data = (data << 8) | (data >> 8);
|
||||
|
||||
m_ata_1->write_cs1((offset >> 1) & 0x07, data, mem_mask);
|
||||
m_ata_1->cs1_w((offset >> 1) & 0x07, data, mem_mask);
|
||||
}
|
||||
|
||||
} } } // namespace bus::amiga::zorro
|
||||
|
@ -133,15 +133,10 @@ public:
|
||||
return *this;
|
||||
}
|
||||
|
||||
uint16_t read_cs0(offs_t offset, uint16_t mem_mask = 0xffff) { return internal_read_cs0(offset, mem_mask); }
|
||||
uint16_t read_cs1(offs_t offset, uint16_t mem_mask = 0xffff) { return internal_read_cs1(offset, mem_mask); }
|
||||
void write_cs0(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff) { internal_write_cs0(offset, data, mem_mask); }
|
||||
void write_cs1(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff) { internal_write_cs1(offset, data, mem_mask); }
|
||||
|
||||
DECLARE_READ16_MEMBER(cs0_r) { return read_cs0(offset, mem_mask); }
|
||||
DECLARE_READ16_MEMBER(cs1_r) { return read_cs1(offset, mem_mask); }
|
||||
DECLARE_WRITE16_MEMBER(cs0_w) { write_cs0(offset, data, mem_mask); }
|
||||
DECLARE_WRITE16_MEMBER(cs1_w) { write_cs1(offset, data, mem_mask); }
|
||||
uint16_t cs0_r(offs_t offset, uint16_t mem_mask = 0xffff) { return internal_read_cs0(offset, mem_mask); }
|
||||
uint16_t cs1_r(offs_t offset, uint16_t mem_mask = 0xffff) { return internal_read_cs1(offset, mem_mask); }
|
||||
void cs0_w(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff) { internal_write_cs0(offset, data, mem_mask); }
|
||||
void cs1_w(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff) { internal_write_cs1(offset, data, mem_mask); }
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(ATA_INTERFACE, ata_interface_device)
|
||||
|
@ -149,18 +149,18 @@ uint8_t bbc_datacentre_device::fred_r(offs_t offset)
|
||||
case 0x40:
|
||||
if (offset & 0x07)
|
||||
{
|
||||
data = m_ide->read_cs0(offset & 0x07, 0xff);
|
||||
data = m_ide->cs0_r(offset & 0x07, 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ide_data = m_ide->read_cs0(offset & 0x07);
|
||||
m_ide_data = m_ide->cs0_r(offset & 0x07);
|
||||
data = m_ide_data & 0xff;
|
||||
}
|
||||
break;
|
||||
case 0x48:
|
||||
if (offset & 0x04)
|
||||
{
|
||||
data = m_ide->read_cs1(offset & 0x07, 0xff);
|
||||
data = m_ide->cs1_r(offset & 0x07, 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -206,18 +206,18 @@ void bbc_datacentre_device::fred_w(offs_t offset, uint8_t data)
|
||||
case 0x40:
|
||||
if (offset & 0x07)
|
||||
{
|
||||
m_ide->write_cs0(offset & 0x07, data, 0xff);
|
||||
m_ide->cs0_w(offset & 0x07, data, 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ide_data = (m_ide_data & 0xff00) | data;
|
||||
m_ide->write_cs0(offset & 0x07, m_ide_data);
|
||||
m_ide->cs0_w(offset & 0x07, m_ide_data);
|
||||
}
|
||||
break;
|
||||
case 0x48:
|
||||
if (offset & 0x04)
|
||||
{
|
||||
m_ide->write_cs1(offset & 0x07, data, 0xff);
|
||||
m_ide->cs1_w(offset & 0x07, data, 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -117,7 +117,7 @@ uint8_t bbc_ide8_device::fred_r(offs_t offset)
|
||||
switch (offset & 0xf8)
|
||||
{
|
||||
case 0x40:
|
||||
data = m_ide->read_cs0(offset & 0x07, 0xff);
|
||||
data = m_ide->cs0_r(offset & 0x07, 0xff);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -129,7 +129,7 @@ void bbc_ide8_device::fred_w(offs_t offset, uint8_t data)
|
||||
switch (offset & 0xf8)
|
||||
{
|
||||
case 0x40:
|
||||
m_ide->write_cs0(offset & 0x07, data, 0xff);
|
||||
m_ide->cs0_w(offset & 0x07, data, 0xff);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -146,18 +146,18 @@ uint8_t bbc_beebide_device::fred_r(offs_t offset)
|
||||
case 0x40:
|
||||
if (offset & 0x07)
|
||||
{
|
||||
data = m_ide->read_cs0(offset & 0x07, 0xff);
|
||||
data = m_ide->cs0_r(offset & 0x07, 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ide_data = m_ide->read_cs0(offset & 0x07);
|
||||
m_ide_data = m_ide->cs0_r(offset & 0x07);
|
||||
data = m_ide_data & 0xff;
|
||||
}
|
||||
break;
|
||||
case 0x48:
|
||||
if (offset & 0x04)
|
||||
{
|
||||
data = m_ide->read_cs1(offset & 0x07, 0xff);
|
||||
data = m_ide->cs1_r(offset & 0x07, 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -181,18 +181,18 @@ void bbc_beebide_device::fred_w(offs_t offset, uint8_t data)
|
||||
case 0x40:
|
||||
if (offset & 0x07)
|
||||
{
|
||||
m_ide->write_cs0(offset & 0x07, data, 0xff);
|
||||
m_ide->cs0_w(offset & 0x07, data, 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ide_data = (m_ide_data & 0xff00) | data;
|
||||
m_ide->write_cs0(offset & 0x07, m_ide_data);
|
||||
m_ide->cs0_w(offset & 0x07, m_ide_data);
|
||||
}
|
||||
break;
|
||||
case 0x48:
|
||||
if (offset & 0x04)
|
||||
{
|
||||
m_ide->write_cs1(offset & 0x07, data, 0xff);
|
||||
m_ide->cs1_w(offset & 0x07, data, 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -173,13 +173,13 @@ uint8_t c64_ide64_cartridge_device::c64_cd_r(offs_t offset, uint8_t data, int sp
|
||||
|
||||
if (io1_offset >= 0x20 && io1_offset < 0x28)
|
||||
{
|
||||
m_ata_data = m_ata->read_cs0(offset & 0x07);
|
||||
m_ata_data = m_ata->cs0_r(offset & 0x07);
|
||||
|
||||
data = m_ata_data & 0xff;
|
||||
}
|
||||
else if (io1_offset >= 0x28 && io1_offset < 0x30)
|
||||
{
|
||||
m_ata_data = m_ata->read_cs1(offset & 0x07);
|
||||
m_ata_data = m_ata->cs1_r(offset & 0x07);
|
||||
|
||||
data = m_ata_data & 0xff;
|
||||
}
|
||||
@ -276,13 +276,13 @@ void c64_ide64_cartridge_device::c64_cd_w(offs_t offset, uint8_t data, int sphi2
|
||||
{
|
||||
m_ata_data = (m_ata_data & 0xff00) | data;
|
||||
|
||||
m_ata->write_cs0(offset & 0x07, m_ata_data);
|
||||
m_ata->cs0_w(offset & 0x07, m_ata_data);
|
||||
}
|
||||
else if (io1_offset >= 0x28 && io1_offset < 0x30)
|
||||
{
|
||||
m_ata_data = (m_ata_data & 0xff00) | data;
|
||||
|
||||
m_ata->write_cs1(offset & 0x07, m_ata_data);
|
||||
m_ata->cs1_w(offset & 0x07, m_ata_data);
|
||||
}
|
||||
else if (io1_offset == 0x31)
|
||||
{
|
||||
|
@ -133,27 +133,27 @@ READ8_MEMBER(cpc_symbiface2_device::ide_cs0_r)
|
||||
else
|
||||
{
|
||||
m_iohigh = true;
|
||||
m_ide_data = m_ide->read_cs0(offset);
|
||||
m_ide_data = m_ide->cs0_r(offset);
|
||||
return m_ide_data & 0xff;
|
||||
}
|
||||
}
|
||||
else
|
||||
return m_ide->read_cs0(offset);
|
||||
return m_ide->cs0_r(offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(cpc_symbiface2_device::ide_cs0_w)
|
||||
{
|
||||
m_ide->write_cs0(offset, data);
|
||||
m_ide->cs0_w(offset, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(cpc_symbiface2_device::ide_cs1_r)
|
||||
{
|
||||
return m_ide->read_cs1(offset);
|
||||
return m_ide->cs1_r(offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(cpc_symbiface2_device::ide_cs1_w)
|
||||
{
|
||||
m_ide->write_cs1(offset, data);
|
||||
m_ide->cs1_w(offset, data);
|
||||
}
|
||||
|
||||
// RTC (Dallas DS1287A)
|
||||
|
@ -135,13 +135,13 @@ READ8_MEMBER( side116_device::read )
|
||||
|
||||
if (offset == 0)
|
||||
{
|
||||
uint16_t ide_data = m_ata->read_cs0(0);
|
||||
uint16_t ide_data = m_ata->cs0_r(0);
|
||||
data = ide_data & 0xff;
|
||||
m_latch = ide_data >> 8;
|
||||
}
|
||||
else if (offset < 8)
|
||||
{
|
||||
data = m_ata->read_cs0(offset & 7, 0xff);
|
||||
data = m_ata->cs0_r(offset & 7, 0xff);
|
||||
}
|
||||
else if (offset == 8)
|
||||
{
|
||||
@ -149,7 +149,7 @@ READ8_MEMBER( side116_device::read )
|
||||
}
|
||||
else
|
||||
{
|
||||
data = m_ata->read_cs1(offset & 7, 0xff);
|
||||
data = m_ata->cs1_r(offset & 7, 0xff);
|
||||
}
|
||||
|
||||
return data;
|
||||
@ -160,11 +160,11 @@ WRITE8_MEMBER( side116_device::write )
|
||||
if (offset == 0)
|
||||
{
|
||||
uint16_t ide_data = (m_latch << 8) | data;
|
||||
m_ata->write_cs0(0, ide_data);
|
||||
m_ata->cs0_w(0, ide_data);
|
||||
}
|
||||
else if (offset < 8)
|
||||
{
|
||||
m_ata->write_cs0(offset & 7, data, 0xff);
|
||||
m_ata->cs0_w(offset & 7, data, 0xff);
|
||||
}
|
||||
else if (offset == 8)
|
||||
{
|
||||
@ -172,7 +172,7 @@ WRITE8_MEMBER( side116_device::write )
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ata->write_cs1(offset & 7, data, 0xff);
|
||||
m_ata->cs1_w(offset & 7, data, 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -63,13 +63,13 @@ READ8_MEMBER( xtide_device::read )
|
||||
|
||||
if (offset == 0)
|
||||
{
|
||||
uint16_t data16 = m_ata->read_cs0(offset & 7);
|
||||
uint16_t data16 = m_ata->cs0_r(offset & 7);
|
||||
result = data16 & 0xff;
|
||||
m_d8_d15_latch = data16 >> 8;
|
||||
}
|
||||
else if (offset < 8)
|
||||
{
|
||||
result = m_ata->read_cs0(offset & 7, 0xff);
|
||||
result = m_ata->cs0_r(offset & 7, 0xff);
|
||||
}
|
||||
else if (offset == 8)
|
||||
{
|
||||
@ -77,7 +77,7 @@ READ8_MEMBER( xtide_device::read )
|
||||
}
|
||||
else
|
||||
{
|
||||
result = m_ata->read_cs1(offset & 7, 0xff);
|
||||
result = m_ata->cs1_r(offset & 7, 0xff);
|
||||
}
|
||||
|
||||
// logerror("%s xtide_device::read: offset=%d, result=%2X\n",device->machine().describe_context(),offset,result);
|
||||
@ -93,11 +93,11 @@ WRITE8_MEMBER( xtide_device::write )
|
||||
{
|
||||
// Data register transfer low byte and latched high
|
||||
uint16_t data16 = (m_d8_d15_latch << 8) | data;
|
||||
m_ata->write_cs0(offset & 7, data16);
|
||||
m_ata->cs0_w(offset & 7, data16);
|
||||
}
|
||||
else if (offset < 8)
|
||||
{
|
||||
m_ata->write_cs0(offset & 7, data, 0xff);
|
||||
m_ata->cs0_w(offset & 7, data, 0xff);
|
||||
}
|
||||
else if (offset == 8)
|
||||
{
|
||||
@ -105,7 +105,7 @@ WRITE8_MEMBER( xtide_device::write )
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ata->write_cs1(offset & 7, data, 0xff);
|
||||
m_ata->cs1_w(offset & 7, data, 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -440,11 +440,11 @@ READ8_MEMBER(kc_d004_gide_device::gide_r)
|
||||
{
|
||||
if (ide_cs == 0 )
|
||||
{
|
||||
m_ata_data = m_ata->read_cs0(io_addr & 0x07);
|
||||
m_ata_data = m_ata->cs0_r(io_addr & 0x07);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ata_data = m_ata->read_cs1(io_addr & 0x07);
|
||||
m_ata_data = m_ata->cs1_r(io_addr & 0x07);
|
||||
}
|
||||
}
|
||||
|
||||
@ -489,11 +489,11 @@ WRITE8_MEMBER(kc_d004_gide_device::gide_w)
|
||||
{
|
||||
if (ide_cs == 0)
|
||||
{
|
||||
m_ata->write_cs0(io_addr & 0x07, m_ata_data);
|
||||
m_ata->cs0_w(io_addr & 0x07, m_ata_data);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ata->write_cs1(io_addr & 0x07, m_ata_data);
|
||||
m_ata->cs1_w(io_addr & 0x07, m_ata_data);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -211,15 +211,15 @@ uint8_t qubide_device::read(offs_t offset, uint8_t data)
|
||||
switch (offset & 0x0f)
|
||||
{
|
||||
case 0:
|
||||
data = m_ata->read_cs1(0x07, 0xff);
|
||||
data = m_ata->cs1_r(0x07, 0xff);
|
||||
break;
|
||||
|
||||
default:
|
||||
data = m_ata->read_cs0(offset & 0x07, 0xff);
|
||||
data = m_ata->cs0_r(offset & 0x07, 0xff);
|
||||
break;
|
||||
|
||||
case 0x08: case 0x0a: case 0x0c:
|
||||
m_ata_data = m_ata->read_cs0(0);
|
||||
m_ata_data = m_ata->cs0_r(0);
|
||||
|
||||
data = m_ata_data >> 8;
|
||||
break;
|
||||
@ -229,7 +229,7 @@ uint8_t qubide_device::read(offs_t offset, uint8_t data)
|
||||
break;
|
||||
|
||||
case 0x0e: case 0x0f:
|
||||
data = m_ata->read_cs1(0x05, 0xff);
|
||||
data = m_ata->cs1_r(0x05, 0xff);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -256,7 +256,7 @@ void qubide_device::write(offs_t offset, uint8_t data)
|
||||
switch (offset & 0x0f)
|
||||
{
|
||||
case 0: case 0x0e: case 0x0f:
|
||||
m_ata->write_cs1(0x05, data, 0xff);
|
||||
m_ata->cs1_w(0x05, data, 0xff);
|
||||
break;
|
||||
|
||||
case 0x08: case 0x0a: case 0x0c:
|
||||
@ -266,11 +266,11 @@ void qubide_device::write(offs_t offset, uint8_t data)
|
||||
case 0x09: case 0x0b: case 0x0d:
|
||||
m_ata_data = (m_ata_data & 0xff00) | data;
|
||||
|
||||
m_ata->write_cs0(0, m_ata_data);
|
||||
m_ata->cs0_w(0, m_ata_data);
|
||||
break;
|
||||
|
||||
default:
|
||||
m_ata->write_cs0(offset & 0x07, data, 0xff);
|
||||
m_ata->cs0_w(offset & 0x07, data, 0xff);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -252,9 +252,9 @@ READ8Z_MEMBER(nouspikel_ide_card_device::readz)
|
||||
if (first && ((offset & 0x0010)==0))
|
||||
{
|
||||
if (cs1fx)
|
||||
atavalue = m_ata->read_cs0(reg);
|
||||
atavalue = m_ata->cs0_r(reg);
|
||||
else
|
||||
atavalue = m_ata->read_cs1(reg);
|
||||
atavalue = m_ata->cs1_r(reg);
|
||||
LOGMASKED(LOG_ATA, "%s %02x -> %04x\n", cs1fx? "cs1" : "cs3", reg, atavalue);
|
||||
}
|
||||
|
||||
@ -420,9 +420,9 @@ void nouspikel_ide_card_device::write(offs_t offset, uint8_t data)
|
||||
LOGMASKED(LOG_ATA, "%s %02x <- %04x\n", cs1fx? "cs1" : "cs3", reg, atavalue);
|
||||
|
||||
if (cs1fx)
|
||||
m_ata->write_cs0(reg, atavalue);
|
||||
m_ata->cs0_w(reg, atavalue);
|
||||
else
|
||||
m_ata->write_cs1(reg, atavalue);
|
||||
m_ata->cs1_w(reg, atavalue);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -347,13 +347,11 @@ public:
|
||||
DECLARE_READ16_MEMBER( clock_r );
|
||||
DECLARE_WRITE16_MEMBER( clock_w );
|
||||
|
||||
DECLARE_READ8_MEMBER( dmac_scsi_data_read );
|
||||
DECLARE_WRITE8_MEMBER( dmac_scsi_data_write );
|
||||
DECLARE_READ8_MEMBER( dmac_io_read );
|
||||
DECLARE_WRITE8_MEMBER( dmac_io_write );
|
||||
uint8_t dmac_scsi_data_read(offs_t offset);
|
||||
void dmac_scsi_data_write(offs_t offset, uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER( dmac_int_w );
|
||||
|
||||
DECLARE_WRITE8_MEMBER( tpi_port_b_write );
|
||||
void tpi_port_b_write(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER( tpi_int_w );
|
||||
|
||||
void cdtv(machine_config &config);
|
||||
@ -545,7 +543,7 @@ public:
|
||||
{ }
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( akiko_int_w );
|
||||
DECLARE_WRITE8_MEMBER( akiko_cia_0_port_a_write );
|
||||
void akiko_cia_0_port_a_write(uint8_t data);
|
||||
|
||||
void handle_joystick_cia(u8 pra, u8 dra);
|
||||
u16 handle_joystick_potgor(u16 potgor);
|
||||
@ -613,7 +611,7 @@ WRITE16_MEMBER( a500p_state::clock_w )
|
||||
// CD-ROM CONTROLLER
|
||||
//**************************************************************************
|
||||
|
||||
READ8_MEMBER( cdtv_state::dmac_scsi_data_read )
|
||||
uint8_t cdtv_state::dmac_scsi_data_read(offs_t offset)
|
||||
{
|
||||
if (offset >= 0xb0 && offset <= 0xbf)
|
||||
return m_tpi->read(offset);
|
||||
@ -621,29 +619,19 @@ READ8_MEMBER( cdtv_state::dmac_scsi_data_read )
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( cdtv_state::dmac_scsi_data_write )
|
||||
void cdtv_state::dmac_scsi_data_write(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (offset >= 0xb0 && offset <= 0xbf)
|
||||
m_tpi->write(offset, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER( cdtv_state::dmac_io_read )
|
||||
{
|
||||
return m_cdrom->read();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( cdtv_state::dmac_io_write )
|
||||
{
|
||||
m_cdrom->write(data);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( cdtv_state::dmac_int_w )
|
||||
{
|
||||
m_dmac_irq = state;
|
||||
update_int2();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( cdtv_state::tpi_port_b_write )
|
||||
void cdtv_state::tpi_port_b_write(uint8_t data)
|
||||
{
|
||||
m_cdrom->cmd_w(BIT(data, 0));
|
||||
m_cdrom->enable_w(BIT(data, 1));
|
||||
@ -987,9 +975,9 @@ READ16_MEMBER( a4000_state::ide_r )
|
||||
|
||||
// this very likely doesn't respond to all the addresses, figure out which ones
|
||||
if (BIT(offset, 12))
|
||||
data = m_ata->read_cs1((offset >> 1) & 0x07, mem_mask);
|
||||
data = m_ata->cs1_r((offset >> 1) & 0x07, mem_mask);
|
||||
else
|
||||
data = m_ata->read_cs0((offset >> 1) & 0x07, mem_mask);
|
||||
data = m_ata->cs0_r((offset >> 1) & 0x07, mem_mask);
|
||||
|
||||
// swap
|
||||
data = (data << 8) | (data >> 8);
|
||||
@ -1009,9 +997,9 @@ WRITE16_MEMBER( a4000_state::ide_w )
|
||||
|
||||
// this very likely doesn't respond to all the addresses, figure out which ones
|
||||
if (BIT(offset, 12))
|
||||
m_ata->write_cs1((offset >> 1) & 0x07, data, mem_mask);
|
||||
m_ata->cs1_w((offset >> 1) & 0x07, data, mem_mask);
|
||||
else
|
||||
m_ata->write_cs0((offset >> 1) & 0x07, data, mem_mask);
|
||||
m_ata->cs0_w((offset >> 1) & 0x07, data, mem_mask);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( a4000_state::ide_interrupt_w )
|
||||
@ -1152,7 +1140,7 @@ READ_LINE_MEMBER( cd32_state::cd32_sel_mirror_input )
|
||||
return (bits & 0x20)>>5;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( cd32_state::akiko_cia_0_port_a_write )
|
||||
void cd32_state::akiko_cia_0_port_a_write(uint8_t data)
|
||||
{
|
||||
// bit 0, cd audio mute
|
||||
m_cdda->set_output_gain(0, BIT(data, 0) ? 0.0 : 1.0);
|
||||
@ -1823,8 +1811,8 @@ void cdtv_state::cdtv(machine_config &config)
|
||||
AMIGA_DMAC(config, m_dmac, amiga_state::CLK_7M_PAL);
|
||||
m_dmac->scsi_read_handler().set(FUNC(cdtv_state::dmac_scsi_data_read));
|
||||
m_dmac->scsi_write_handler().set(FUNC(cdtv_state::dmac_scsi_data_write));
|
||||
m_dmac->io_read_handler().set(FUNC(cdtv_state::dmac_io_read));
|
||||
m_dmac->io_write_handler().set(FUNC(cdtv_state::dmac_io_write));
|
||||
m_dmac->io_read_handler().set(m_cdrom, FUNC(cr511b_device::read));
|
||||
m_dmac->io_write_handler().set(m_cdrom, FUNC(cr511b_device::write));
|
||||
m_dmac->int_handler().set(FUNC(cdtv_state::dmac_int_w));
|
||||
|
||||
TPI6525(config, m_tpi, 0);
|
||||
|
@ -114,16 +114,16 @@ public:
|
||||
void apfimag(machine_config &config);
|
||||
|
||||
private:
|
||||
DECLARE_READ8_MEMBER(videoram_r);
|
||||
DECLARE_READ8_MEMBER(pia0_porta_r);
|
||||
DECLARE_WRITE8_MEMBER(pia0_portb_w);
|
||||
uint8_t videoram_r(offs_t offset);
|
||||
uint8_t pia0_porta_r();
|
||||
void pia0_portb_w(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(pia0_ca2_w);
|
||||
DECLARE_READ8_MEMBER(pia1_porta_r);
|
||||
DECLARE_READ8_MEMBER(pia1_portb_r);
|
||||
DECLARE_WRITE8_MEMBER(pia1_portb_w);
|
||||
DECLARE_WRITE8_MEMBER(apf_dischw_w);
|
||||
DECLARE_READ8_MEMBER(serial_r);
|
||||
DECLARE_WRITE8_MEMBER(serial_w);
|
||||
uint8_t pia1_porta_r();
|
||||
uint8_t pia1_portb_r();
|
||||
void pia1_portb_w(uint8_t data);
|
||||
void apf_dischw_w(offs_t offset, uint8_t data);
|
||||
uint8_t serial_r(offs_t offset);
|
||||
void serial_w(offs_t offset, uint8_t data);
|
||||
|
||||
void apfimag_map(address_map &map);
|
||||
void apfm1000_map(address_map &map);
|
||||
@ -153,7 +153,7 @@ private:
|
||||
};
|
||||
|
||||
|
||||
READ8_MEMBER( apf_state::videoram_r )
|
||||
uint8_t apf_state::videoram_r(offs_t offset)
|
||||
{
|
||||
if (BIT(m_pad_data, 7)) // AG line
|
||||
{
|
||||
@ -184,7 +184,7 @@ READ8_MEMBER( apf_state::videoram_r )
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( apf_state::pia0_porta_r )
|
||||
uint8_t apf_state::pia0_porta_r()
|
||||
{
|
||||
uint8_t data = 0xff;
|
||||
|
||||
@ -195,7 +195,7 @@ READ8_MEMBER( apf_state::pia0_porta_r )
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( apf_state::pia0_portb_w )
|
||||
void apf_state::pia0_portb_w(uint8_t data)
|
||||
{
|
||||
/* bit 7..6 video control */
|
||||
m_crtc->ag_w(BIT(data, 7));
|
||||
@ -210,12 +210,12 @@ WRITE_LINE_MEMBER( apf_state::pia0_ca2_w )
|
||||
m_ca2 = state;
|
||||
}
|
||||
|
||||
READ8_MEMBER( apf_state::pia1_porta_r )
|
||||
uint8_t apf_state::pia1_porta_r()
|
||||
{
|
||||
return m_key[m_keyboard_data]->read();
|
||||
}
|
||||
|
||||
READ8_MEMBER( apf_state::pia1_portb_r )
|
||||
uint8_t apf_state::pia1_portb_r()
|
||||
{
|
||||
uint8_t data = m_portb;
|
||||
|
||||
@ -226,7 +226,7 @@ READ8_MEMBER( apf_state::pia1_portb_r )
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( apf_state::pia1_portb_w )
|
||||
void apf_state::pia1_portb_w(uint8_t data)
|
||||
{
|
||||
/* bits 2..0 = keyboard line */
|
||||
/* bit 3 = cass audio enable */
|
||||
@ -284,7 +284,7 @@ void apf_state::machine_reset()
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( apf_state::apf_dischw_w)
|
||||
void apf_state::apf_dischw_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
/* bit 3 is index of drive to select */
|
||||
uint8_t drive = BIT(data, 3);
|
||||
@ -305,13 +305,13 @@ WRITE8_MEMBER( apf_state::apf_dischw_w)
|
||||
logerror("disc w %04x %04x\n",offset,data);
|
||||
}
|
||||
|
||||
READ8_MEMBER( apf_state::serial_r)
|
||||
uint8_t apf_state::serial_r(offs_t offset)
|
||||
{
|
||||
logerror("serial r %04x\n",offset);
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( apf_state::serial_w)
|
||||
void apf_state::serial_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
logerror("serial w %04x %04x\n",offset,data);
|
||||
}
|
||||
|
@ -136,10 +136,10 @@ private:
|
||||
|
||||
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
|
||||
DECLARE_READ8_MEMBER(ram_r);
|
||||
DECLARE_WRITE8_MEMBER(ram_w);
|
||||
DECLARE_READ8_MEMBER(pia_keyboard_r);
|
||||
DECLARE_WRITE8_MEMBER(pia_display_w);
|
||||
uint8_t ram_r(offs_t offset);
|
||||
void ram_w(offs_t offset, uint8_t data);
|
||||
uint8_t pia_keyboard_r();
|
||||
void pia_display_w(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(pia_display_gate_w);
|
||||
DECLARE_SNAPSHOT_LOAD_MEMBER(snapshot_cb);
|
||||
TIMER_CALLBACK_MEMBER(ready_start_cb);
|
||||
@ -414,7 +414,7 @@ void apple1_state::machine_reset()
|
||||
m_lastports[0] = m_lastports[1] = m_lastports[2] = m_lastports[3] = 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER(apple1_state::ram_r)
|
||||
uint8_t apple1_state::ram_r(offs_t offset)
|
||||
{
|
||||
if (offset < m_ram_size)
|
||||
{
|
||||
@ -424,7 +424,7 @@ READ8_MEMBER(apple1_state::ram_r)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(apple1_state::ram_w)
|
||||
void apple1_state::ram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (offset < m_ram_size)
|
||||
{
|
||||
@ -440,12 +440,12 @@ void apple1_state::apple1_map(address_map &map)
|
||||
map(0xff00, 0xffff).rom().region(A1_CPU_TAG, 0);
|
||||
}
|
||||
|
||||
READ8_MEMBER(apple1_state::pia_keyboard_r)
|
||||
uint8_t apple1_state::pia_keyboard_r()
|
||||
{
|
||||
return m_transchar | 0x80; // bit 7 is wired high, similar-ish to the Apple II
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(apple1_state::pia_display_w)
|
||||
void apple1_state::pia_display_w(uint8_t data)
|
||||
{
|
||||
data &= 0x7f; // D7 is ignored by the video h/w
|
||||
|
||||
|
@ -369,7 +369,7 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(ay3600_ako_w);
|
||||
DECLARE_READ8_MEMBER(memexp_r);
|
||||
DECLARE_WRITE8_MEMBER(memexp_w);
|
||||
DECLARE_READ8_MEMBER(nsc_backing_r);
|
||||
uint8_t nsc_backing_r(offs_t offset);
|
||||
|
||||
void apple2cp(machine_config &config);
|
||||
void laser128ex2(machine_config &config);
|
||||
@ -2380,7 +2380,7 @@ uint8_t apple2e_state::read_int_rom(int slotbias, int offset)
|
||||
return m_ds1315->read(slotbias + offset);
|
||||
}
|
||||
|
||||
READ8_MEMBER(apple2e_state::nsc_backing_r) { return m_rom_ptr[offset]; }
|
||||
uint8_t apple2e_state::nsc_backing_r(offs_t offset) { return m_rom_ptr[offset]; }
|
||||
|
||||
READ8_MEMBER(apple2e_state::c100_r) { return read_slot_rom(1, offset); }
|
||||
READ8_MEMBER(apple2e_state::c100_int_r) { return read_int_rom(0x100, offset); }
|
||||
|
@ -485,7 +485,7 @@ private:
|
||||
DECLARE_WRITE_LINE_MEMBER(a2bus_inh_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(doc_irq_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(scc_irq_w);
|
||||
DECLARE_READ8_MEMBER(doc_adc_read);
|
||||
uint8_t doc_adc_read();
|
||||
DECLARE_READ8_MEMBER(apple2gs_read_vector);
|
||||
|
||||
#if !RUN_ADB_MICRO
|
||||
@ -502,17 +502,17 @@ private:
|
||||
void keyglu_816_write(uint8_t offset, uint8_t data);
|
||||
void keyglu_regen_irqs();
|
||||
|
||||
DECLARE_READ8_MEMBER(adbmicro_p0_in);
|
||||
DECLARE_READ8_MEMBER(adbmicro_p1_in);
|
||||
DECLARE_READ8_MEMBER(adbmicro_p2_in);
|
||||
DECLARE_READ8_MEMBER(adbmicro_p3_in);
|
||||
DECLARE_WRITE8_MEMBER(adbmicro_p0_out);
|
||||
DECLARE_WRITE8_MEMBER(adbmicro_p1_out);
|
||||
DECLARE_WRITE8_MEMBER(adbmicro_p2_out);
|
||||
DECLARE_WRITE8_MEMBER(adbmicro_p3_out);
|
||||
uint8_t adbmicro_p0_in();
|
||||
uint8_t adbmicro_p1_in();
|
||||
uint8_t adbmicro_p2_in();
|
||||
uint8_t adbmicro_p3_in();
|
||||
void adbmicro_p0_out(uint8_t data);
|
||||
void adbmicro_p1_out(uint8_t data);
|
||||
void adbmicro_p2_out(uint8_t data);
|
||||
void adbmicro_p3_out(uint8_t data);
|
||||
|
||||
offs_t dasm_trampoline(std::ostream &stream, offs_t pc, const util::disasm_interface::data_buffer &opcodes, const util::disasm_interface::data_buffer ¶ms);
|
||||
DECLARE_WRITE8_MEMBER(wdm_trampoline) { }; //m_a2host->wdm_w(space, offset, data); }
|
||||
void wdm_trampoline(offs_t offset, uint8_t data) { }; //m_a2host->wdm_w(space, offset, data); }
|
||||
|
||||
private:
|
||||
bool m_is_rom3;
|
||||
@ -3770,12 +3770,12 @@ void apple2gs_state::a2gs_es5503_map(address_map &map)
|
||||
http://www.llx.com/~nparker/a2/adb.html
|
||||
***************************************************************************/
|
||||
|
||||
READ8_MEMBER(apple2gs_state::adbmicro_p0_in)
|
||||
uint8_t apple2gs_state::adbmicro_p0_in()
|
||||
{
|
||||
return m_glu_bus;
|
||||
}
|
||||
|
||||
READ8_MEMBER(apple2gs_state::adbmicro_p1_in)
|
||||
uint8_t apple2gs_state::adbmicro_p1_in()
|
||||
{
|
||||
#if RUN_ADB_MICRO
|
||||
switch (m_glu_kbd_y)
|
||||
@ -3805,7 +3805,7 @@ READ8_MEMBER(apple2gs_state::adbmicro_p1_in)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
READ8_MEMBER(apple2gs_state::adbmicro_p2_in)
|
||||
uint8_t apple2gs_state::adbmicro_p2_in()
|
||||
{
|
||||
uint8_t rv = 0;
|
||||
|
||||
@ -3815,7 +3815,7 @@ READ8_MEMBER(apple2gs_state::adbmicro_p2_in)
|
||||
return rv;
|
||||
}
|
||||
|
||||
READ8_MEMBER(apple2gs_state::adbmicro_p3_in)
|
||||
uint8_t apple2gs_state::adbmicro_p3_in()
|
||||
{
|
||||
uint8_t rv = 0;
|
||||
#if RUN_ADB_MICRO
|
||||
@ -3832,16 +3832,16 @@ READ8_MEMBER(apple2gs_state::adbmicro_p3_in)
|
||||
return rv;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(apple2gs_state::adbmicro_p0_out)
|
||||
void apple2gs_state::adbmicro_p0_out(uint8_t data)
|
||||
{
|
||||
m_glu_bus = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(apple2gs_state::adbmicro_p1_out)
|
||||
void apple2gs_state::adbmicro_p1_out(uint8_t data)
|
||||
{
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(apple2gs_state::adbmicro_p2_out)
|
||||
void apple2gs_state::adbmicro_p2_out(uint8_t data)
|
||||
{
|
||||
if (!(data & 0x10))
|
||||
{
|
||||
@ -3860,7 +3860,7 @@ WRITE8_MEMBER(apple2gs_state::adbmicro_p2_out)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(apple2gs_state::adbmicro_p3_out)
|
||||
void apple2gs_state::adbmicro_p3_out(uint8_t data)
|
||||
{
|
||||
if (((data & 0x08) == 0x08) != m_adb_line)
|
||||
{
|
||||
@ -4094,7 +4094,7 @@ WRITE_LINE_MEMBER(apple2gs_state::doc_irq_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(apple2gs_state::doc_adc_read)
|
||||
uint8_t apple2gs_state::doc_adc_read()
|
||||
{
|
||||
return 0x80;
|
||||
}
|
||||
|
@ -91,7 +91,7 @@ public:
|
||||
DECLARE_WRITE16_MEMBER(arcadia_multibios_change_game);
|
||||
template <int Coin> DECLARE_CUSTOM_INPUT_MEMBER(coin_counter_r);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(coin_changed_callback);
|
||||
DECLARE_WRITE8_MEMBER(arcadia_cia_0_portb_w);
|
||||
void arcadia_cia_0_portb_w(uint8_t data);
|
||||
|
||||
private:
|
||||
inline void generic_decode(const char *tag, int bit7, int bit6, int bit5, int bit4, int bit3, int bit2, int bit1, int bit0);
|
||||
@ -142,7 +142,7 @@ WRITE16_MEMBER(arcadia_amiga_state::arcadia_multibios_change_game)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE8_MEMBER(arcadia_amiga_state::arcadia_cia_0_portb_w)
|
||||
void arcadia_amiga_state::arcadia_cia_0_portb_w(uint8_t data)
|
||||
{
|
||||
/* writing a 0 in the low bit clears one of the coins */
|
||||
if ((data & 1) == 0)
|
||||
|
@ -1911,7 +1911,7 @@ READ16_MEMBER(cobra_state::sub_ata0_r)
|
||||
{
|
||||
mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
|
||||
|
||||
uint32_t data = m_ata->read_cs0(offset, mem_mask);
|
||||
uint32_t data = m_ata->cs0_r(offset, mem_mask);
|
||||
data = ( data << 8 ) | ( data >> 8 );
|
||||
|
||||
return data;
|
||||
@ -1922,14 +1922,14 @@ WRITE16_MEMBER(cobra_state::sub_ata0_w)
|
||||
mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
|
||||
data = ( data << 8 ) | ( data >> 8 );
|
||||
|
||||
m_ata->write_cs0(offset, data, mem_mask);
|
||||
m_ata->cs0_w(offset, data, mem_mask);
|
||||
}
|
||||
|
||||
READ16_MEMBER(cobra_state::sub_ata1_r)
|
||||
{
|
||||
mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
|
||||
|
||||
uint32_t data = m_ata->read_cs1(offset, mem_mask);
|
||||
uint32_t data = m_ata->cs1_r(offset, mem_mask);
|
||||
|
||||
return ( data << 8 ) | ( data >> 8 );
|
||||
}
|
||||
@ -1939,7 +1939,7 @@ WRITE16_MEMBER(cobra_state::sub_ata1_w)
|
||||
mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
|
||||
data = ( data << 8 ) | ( data >> 8 );
|
||||
|
||||
m_ata->write_cs1(offset, data, mem_mask);
|
||||
m_ata->cs1_w(offset, data, mem_mask);
|
||||
}
|
||||
|
||||
READ32_MEMBER(cobra_state::sub_comram_r)
|
||||
|
@ -342,7 +342,7 @@ public:
|
||||
template <int P> DECLARE_READ_LINE_MEMBER(cd32_sel_mirror_input);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( akiko_int_w );
|
||||
DECLARE_WRITE8_MEMBER( akiko_cia_0_port_a_write );
|
||||
void akiko_cia_0_port_a_write(uint8_t data);
|
||||
|
||||
void init_cubo();
|
||||
void init_mgprem11();
|
||||
@ -406,7 +406,7 @@ WRITE_LINE_MEMBER( cubo_state::akiko_int_w )
|
||||
*************************************/
|
||||
|
||||
|
||||
WRITE8_MEMBER( cubo_state::akiko_cia_0_port_a_write )
|
||||
void cubo_state::akiko_cia_0_port_a_write(uint8_t data)
|
||||
{
|
||||
/* bit 0 = cd audio mute */
|
||||
m_cdda->set_output_gain( 0, ( data & 1 ) ? 0.0 : 1.0 );
|
||||
|
@ -335,12 +335,12 @@ READ32_MEMBER(firebeat_state::ata_command_r )
|
||||
// printf("ata_command_r: %08X, %08X\n", offset, mem_mask);
|
||||
if (ACCESSING_BITS_16_31)
|
||||
{
|
||||
r = m_ata->read_cs0(offset*2, BYTESWAP16((mem_mask >> 16) & 0xffff));
|
||||
r = m_ata->cs0_r(offset*2, BYTESWAP16((mem_mask >> 16) & 0xffff));
|
||||
return BYTESWAP16(r) << 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
r = m_ata->read_cs0((offset*2) + 1, BYTESWAP16((mem_mask >> 0) & 0xffff));
|
||||
r = m_ata->cs0_r((offset*2) + 1, BYTESWAP16((mem_mask >> 0) & 0xffff));
|
||||
return BYTESWAP16(r) << 0;
|
||||
}
|
||||
}
|
||||
@ -351,11 +351,11 @@ WRITE32_MEMBER(firebeat_state::ata_command_w )
|
||||
|
||||
if (ACCESSING_BITS_16_31)
|
||||
{
|
||||
m_ata->write_cs0(offset*2, BYTESWAP16((data >> 16) & 0xffff), BYTESWAP16((mem_mask >> 16) & 0xffff));
|
||||
m_ata->cs0_w(offset*2, BYTESWAP16((data >> 16) & 0xffff), BYTESWAP16((mem_mask >> 16) & 0xffff));
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ata->write_cs0((offset*2) + 1, BYTESWAP16((data >> 0) & 0xffff), BYTESWAP16((mem_mask >> 0) & 0xffff));
|
||||
m_ata->cs0_w((offset*2) + 1, BYTESWAP16((data >> 0) & 0xffff), BYTESWAP16((mem_mask >> 0) & 0xffff));
|
||||
}
|
||||
}
|
||||
|
||||
@ -367,12 +367,12 @@ READ32_MEMBER(firebeat_state::ata_control_r )
|
||||
|
||||
if (ACCESSING_BITS_16_31)
|
||||
{
|
||||
r = m_ata->read_cs1(offset*2, BYTESWAP16((mem_mask >> 16) & 0xffff));
|
||||
r = m_ata->cs1_r(offset*2, BYTESWAP16((mem_mask >> 16) & 0xffff));
|
||||
return BYTESWAP16(r) << 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
r = m_ata->read_cs1((offset*2) + 1, BYTESWAP16((mem_mask >> 0) & 0xffff));
|
||||
r = m_ata->cs1_r((offset*2) + 1, BYTESWAP16((mem_mask >> 0) & 0xffff));
|
||||
return BYTESWAP16(r) << 0;
|
||||
}
|
||||
}
|
||||
@ -381,11 +381,11 @@ WRITE32_MEMBER(firebeat_state::ata_control_w )
|
||||
{
|
||||
if (ACCESSING_BITS_16_31)
|
||||
{
|
||||
m_ata->write_cs1(offset*2, BYTESWAP16(data >> 16) & 0xffff, BYTESWAP16((mem_mask >> 16) & 0xffff));
|
||||
m_ata->cs1_w(offset*2, BYTESWAP16(data >> 16) & 0xffff, BYTESWAP16((mem_mask >> 16) & 0xffff));
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ata->write_cs1((offset*2) + 1, BYTESWAP16(data >> 0) & 0xffff, BYTESWAP16((mem_mask >> 0) & 0xffff));
|
||||
m_ata->cs1_w((offset*2) + 1, BYTESWAP16(data >> 0) & 0xffff, BYTESWAP16((mem_mask >> 0) & 0xffff));
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -71,12 +71,12 @@ void gscpm_state::gscpm_io(address_map &map)
|
||||
|
||||
READ8_MEMBER( gscpm_state::cflash_r )
|
||||
{
|
||||
return m_ide->read_cs0(offset, 0xff);
|
||||
return m_ide->cs0_r(offset, 0xff);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( gscpm_state::cflash_w )
|
||||
{
|
||||
m_ide->write_cs0(offset, data, 0xff);
|
||||
m_ide->cs0_w(offset, data, 0xff);
|
||||
}
|
||||
|
||||
READ8_MEMBER( gscpm_state::sio_r )
|
||||
|
@ -374,25 +374,25 @@ INTERRUPT_GEN_MEMBER(kinst_state::irq0_start)
|
||||
|
||||
READ32_MEMBER(kinst_state::ide_r)
|
||||
{
|
||||
return m_ata->read_cs0(offset / 2, mem_mask);
|
||||
return m_ata->cs0_r(offset / 2, mem_mask);
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(kinst_state::ide_w)
|
||||
{
|
||||
m_ata->write_cs0(offset / 2, data, mem_mask);
|
||||
m_ata->cs0_w(offset / 2, data, mem_mask);
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(kinst_state::ide_extra_r)
|
||||
{
|
||||
return m_ata->read_cs1(6, 0xff);
|
||||
return m_ata->cs1_r(6, 0xff);
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(kinst_state::ide_extra_w)
|
||||
{
|
||||
m_ata->write_cs1(6, data, 0xff);
|
||||
m_ata->cs1_w(6, data, 0xff);
|
||||
}
|
||||
|
||||
|
||||
|
@ -203,9 +203,9 @@ READ16_MEMBER(gsan_state::cf_regs_r)
|
||||
offset *= 2;
|
||||
u16 data = 0;
|
||||
if (ACCESSING_BITS_0_7)
|
||||
data |= m_ata->read_cs0(offset, 0xff) & 0xff;
|
||||
data |= m_ata->cs0_r(offset, 0xff) & 0xff;
|
||||
if (ACCESSING_BITS_8_15)
|
||||
data |= (m_ata->read_cs0(offset + 1, 0xff) << 8);
|
||||
data |= (m_ata->cs0_r(offset + 1, 0xff) << 8);
|
||||
return data;
|
||||
}
|
||||
|
||||
@ -213,20 +213,20 @@ WRITE16_MEMBER(gsan_state::cf_regs_w)
|
||||
{
|
||||
offset *= 2;
|
||||
if (ACCESSING_BITS_0_7)
|
||||
m_ata->write_cs0(offset, data & 0xff, 0xff);
|
||||
m_ata->cs0_w(offset, data & 0xff, 0xff);
|
||||
if (ACCESSING_BITS_8_15)
|
||||
m_ata->write_cs0(offset + 1, data >> 8, 0xff);
|
||||
m_ata->cs0_w(offset + 1, data >> 8, 0xff);
|
||||
}
|
||||
|
||||
READ16_MEMBER(gsan_state::cf_data_r)
|
||||
{
|
||||
u16 data = m_ata->read_cs0(0, 0xffff);
|
||||
u16 data = m_ata->cs0_r(0, 0xffff);
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(gsan_state::cf_data_w)
|
||||
{
|
||||
m_ata->write_cs0(0, data, 0xffff);
|
||||
m_ata->cs0_w(0, data, 0xffff);
|
||||
}
|
||||
|
||||
// misc I/O
|
||||
|
@ -326,12 +326,12 @@ public:
|
||||
|
||||
DECLARE_READ16_MEMBER(konami_ide_r)
|
||||
{
|
||||
return swapendian_int16(m_ata->read_cs0(offset, mem_mask));
|
||||
return swapendian_int16(m_ata->cs0_r(offset, mem_mask));
|
||||
}
|
||||
|
||||
DECLARE_WRITE16_MEMBER(konami_ide_w)
|
||||
{
|
||||
m_ata->write_cs0(offset, swapendian_int16(data), mem_mask);
|
||||
m_ata->cs0_w(offset, swapendian_int16(data), mem_mask);
|
||||
}
|
||||
|
||||
private:
|
||||
|
@ -734,15 +734,15 @@ TIMER_CALLBACK_MEMBER( ksys573_state::atapi_xfer_end )
|
||||
|
||||
for( int i = 0; i < m_atapi_xfersize; i++ )
|
||||
{
|
||||
uint32_t d = m_ata->read_cs0(0) << 0;
|
||||
d |= m_ata->read_cs0(0) << 16;
|
||||
uint32_t d = m_ata->cs0_r(0) << 0;
|
||||
d |= m_ata->cs0_r(0) << 16;
|
||||
|
||||
m_p_n_psxram[ m_atapi_xferbase / 4 ] = d;
|
||||
m_atapi_xferbase += 4;
|
||||
}
|
||||
|
||||
/// HACK: konami80s only works if you dma more data than requested
|
||||
if( ( m_ata->read_cs1(6) & 8 ) != 0 )
|
||||
if( ( m_ata->cs1_r(6) & 8 ) != 0 )
|
||||
{
|
||||
m_atapi_timer->adjust( m_maincpu->cycles_to_attotime( ( ATAPI_CYCLES_PER_SECTOR * ( m_atapi_xfersize / 64 ) ) ) );
|
||||
}
|
||||
|
@ -2,7 +2,7 @@
|
||||
// copyright-holders:Raphael Nabet
|
||||
/*********************************************************************
|
||||
|
||||
drivers/lisa.c
|
||||
drivers/lisa.cpp
|
||||
|
||||
Experimental LISA driver
|
||||
|
||||
|
@ -120,11 +120,11 @@ private:
|
||||
DECLARE_WRITE16_MEMBER(bankedarea_w);
|
||||
DECLARE_WRITE8_MEMBER(led_out_w);
|
||||
DECLARE_WRITE8_MEMBER(fifo_out_w);
|
||||
DECLARE_READ8_MEMBER(via_pa_r);
|
||||
DECLARE_WRITE8_MEMBER(via_pa_w);
|
||||
uint8_t via_pa_r();
|
||||
void via_pa_w(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(via_ca2_w);
|
||||
DECLARE_READ8_MEMBER(via_pb_r);
|
||||
DECLARE_WRITE8_MEMBER(via_pb_w);
|
||||
uint8_t via_pb_r();
|
||||
void via_pb_w(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(via_cb1_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(via_cb2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(via_int_w);
|
||||
@ -296,13 +296,13 @@ WRITE8_MEMBER(lwriter_state::fifo_out_w)
|
||||
}
|
||||
|
||||
/* via stuff */
|
||||
READ8_MEMBER(lwriter_state::via_pa_r)
|
||||
uint8_t lwriter_state::via_pa_r()
|
||||
{
|
||||
logerror(" VIA: Port A read!\n");
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lwriter_state::via_pa_w)
|
||||
void lwriter_state::via_pa_w(uint8_t data)
|
||||
{
|
||||
logerror(" VIA: Port A written with data of 0x%02x!\n", data);
|
||||
}
|
||||
@ -312,13 +312,13 @@ WRITE_LINE_MEMBER(lwriter_state::via_ca2_w)
|
||||
logerror(" VIA: CA2 written with %d!\n", state);
|
||||
}
|
||||
|
||||
READ8_MEMBER(lwriter_state::via_pb_r)
|
||||
uint8_t lwriter_state::via_pb_r()
|
||||
{
|
||||
logerror(" VIA: Port B read!\n");
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lwriter_state::via_pb_w)
|
||||
void lwriter_state::via_pb_w(uint8_t data)
|
||||
{
|
||||
logerror(" VIA: Port B written with data of 0x%02x!\n", data);
|
||||
/* Like early Mac models which had VIA A4 control overlaying, the
|
||||
|
@ -233,10 +233,10 @@ private:
|
||||
DECLARE_WRITE_LINE_MEMBER(mac_kbd_clk_in);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(mac_via_out_cb2);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_a);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_b);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_a);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_b);
|
||||
uint8_t mac_via_in_a();
|
||||
uint8_t mac_via_in_b();
|
||||
void mac_via_out_a(uint8_t data);
|
||||
void mac_via_out_b(uint8_t data);
|
||||
void mac128_state_load();
|
||||
DECLARE_WRITE_LINE_MEMBER(mac_via_irq);
|
||||
int scan_keyboard();
|
||||
@ -690,12 +690,12 @@ READ16_MEMBER ( mac128_state::mac_autovector_r )
|
||||
return 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac128_state::mac_via_in_a)
|
||||
uint8_t mac128_state::mac_via_in_a()
|
||||
{
|
||||
return 0x80;
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac128_state::mac_via_in_b)
|
||||
uint8_t mac128_state::mac_via_in_b()
|
||||
{
|
||||
int val = 0x40;
|
||||
|
||||
@ -713,7 +713,7 @@ READ8_MEMBER(mac128_state::mac_via_in_b)
|
||||
return val;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac128_state::mac_via_out_a)
|
||||
void mac128_state::mac_via_out_a(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT A: %02x (PC %x)\n", machine().describe_context().c_str(), data);
|
||||
|
||||
@ -735,7 +735,7 @@ WRITE8_MEMBER(mac128_state::mac_via_out_a)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac128_state::mac_via_out_b)
|
||||
void mac128_state::mac_via_out_b(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT B: %02x\n", machine().describe_context().c_str(), data);
|
||||
|
||||
|
@ -2,7 +2,7 @@
|
||||
// copyright-holders:R. Belmont
|
||||
/***************************************************************************
|
||||
|
||||
macpci.c: second-generation Old World PowerMacs based on PCI instead of NuBus
|
||||
macpci.cpp: second-generation Old World PowerMacs based on PCI instead of NuBus
|
||||
|
||||
Preliminary driver by R. Belmont (based on pippin.c skeleton by Angelo Salese)
|
||||
|
||||
|
@ -499,22 +499,22 @@ WRITE8_MEMBER(pc9801_state::ide_ctrl_w)
|
||||
|
||||
READ16_MEMBER(pc9801_state::ide_cs0_r)
|
||||
{
|
||||
return m_ide[m_ide_sel]->read_cs0(offset, mem_mask);
|
||||
return m_ide[m_ide_sel]->cs0_r(offset, mem_mask);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(pc9801_state::ide_cs0_w)
|
||||
{
|
||||
m_ide[m_ide_sel]->write_cs0(offset, data, mem_mask);
|
||||
m_ide[m_ide_sel]->cs0_w(offset, data, mem_mask);
|
||||
}
|
||||
|
||||
READ16_MEMBER(pc9801_state::ide_cs1_r)
|
||||
{
|
||||
return m_ide[m_ide_sel]->read_cs1(offset, mem_mask);
|
||||
return m_ide[m_ide_sel]->cs1_r(offset, mem_mask);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(pc9801_state::ide_cs1_w)
|
||||
{
|
||||
m_ide[m_ide_sel]->write_cs1(offset, data, mem_mask);
|
||||
m_ide[m_ide_sel]->cs1_w(offset, data, mem_mask);
|
||||
}
|
||||
|
||||
READ8_MEMBER( pc9801_state::sasi_data_r )
|
||||
|
@ -224,7 +224,7 @@ void pcw_state::pcw_map(address_map &map)
|
||||
|
||||
|
||||
/* Keyboard is read by the MCU and sent as serial data to the gate array ASIC */
|
||||
READ8_MEMBER(pcw_state::pcw_keyboard_r)
|
||||
uint8_t pcw_state::pcw_keyboard_r(offs_t offset)
|
||||
{
|
||||
return m_iptlines[offset]->read();
|
||||
}
|
||||
@ -753,20 +753,20 @@ TIMER_CALLBACK_MEMBER(pcw_state::pcw_pins_callback)
|
||||
m_printer_p2 |= 0x40;
|
||||
}
|
||||
|
||||
READ8_MEMBER(pcw_state::mcu_printer_p1_r)
|
||||
uint8_t pcw_state::mcu_printer_p1_r()
|
||||
{
|
||||
LOGPRN("PRN: MCU reading data from P1\n");
|
||||
return m_printer_pins & 0x00ff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pcw_state::mcu_printer_p1_w)
|
||||
void pcw_state::mcu_printer_p1_w(uint8_t data)
|
||||
{
|
||||
m_printer_pins = (m_printer_pins & 0x0100) | data;
|
||||
LOGPRN("PRN: Print head position = %i", m_printer_headpos);
|
||||
LOGPRN("PRN: MCU writing %02x to P1 [%03x/%03x]\n", data,m_printer_pins, ~m_printer_pins & 0x1ff);
|
||||
}
|
||||
|
||||
READ8_MEMBER(pcw_state::mcu_printer_p2_r)
|
||||
uint8_t pcw_state::mcu_printer_p2_r()
|
||||
{
|
||||
uint8_t ret = 0x00;
|
||||
LOGPRN("PRN: MCU reading data from P2\n");
|
||||
@ -777,7 +777,7 @@ READ8_MEMBER(pcw_state::mcu_printer_p2_r)
|
||||
return ret;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pcw_state::mcu_printer_p2_w)
|
||||
void pcw_state::mcu_printer_p2_w(uint8_t data)
|
||||
{
|
||||
LOGPRN("PRN: MCU writing %02x to P2\n", data);
|
||||
m_printer_p2 = data & 0x70;
|
||||
@ -862,22 +862,22 @@ void pcw_state::mcu_transmit_serial(uint8_t bit)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(pcw_state::mcu_kb_scan_r)
|
||||
uint8_t pcw_state::mcu_kb_scan_r()
|
||||
{
|
||||
return m_kb_scan_row & 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pcw_state::mcu_kb_scan_w)
|
||||
void pcw_state::mcu_kb_scan_w(uint8_t data)
|
||||
{
|
||||
m_kb_scan_row = (m_kb_scan_row & 0xff00) | data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(pcw_state::mcu_kb_scan_high_r)
|
||||
uint8_t pcw_state::mcu_kb_scan_high_r()
|
||||
{
|
||||
return (m_kb_scan_row & 0xff00) >> 8;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pcw_state::mcu_kb_scan_high_w)
|
||||
void pcw_state::mcu_kb_scan_high_w(uint8_t data)
|
||||
{
|
||||
if((m_mcu_prev & 0x02) && !(data & 0x02)) // bit is transmitted on high-to-low clock transition
|
||||
{
|
||||
@ -896,7 +896,7 @@ WRITE8_MEMBER(pcw_state::mcu_kb_scan_high_w)
|
||||
m_mcu_prev = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(pcw_state::mcu_kb_data_r)
|
||||
uint8_t pcw_state::mcu_kb_data_r()
|
||||
{
|
||||
uint16_t scan_bits = ((m_kb_scan_row & 0xf000) >> 4) | (m_kb_scan_row & 0xff);
|
||||
int x;
|
||||
@ -904,7 +904,7 @@ READ8_MEMBER(pcw_state::mcu_kb_data_r)
|
||||
for(x=0;x<12;x++)
|
||||
{
|
||||
if(!(scan_bits & 1))
|
||||
return pcw_keyboard_r(space,x);
|
||||
return pcw_keyboard_r(x);
|
||||
else
|
||||
scan_bits >>= 1;
|
||||
}
|
||||
|
@ -172,17 +172,17 @@ private:
|
||||
// TODO: wrong, likely PIC protected too
|
||||
READ8_MEMBER( psattack_state::cfcard_regs_r )
|
||||
{
|
||||
return m_ata->read_cs0(offset & 7, 0x000000ff);
|
||||
return m_ata->cs0_r(offset & 7, 0x000000ff);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( psattack_state::cfcard_regs_w )
|
||||
{
|
||||
m_ata->write_cs0(offset & 7, 0x000000ff);
|
||||
m_ata->cs0_w(offset & 7, 0x000000ff);
|
||||
}
|
||||
|
||||
READ16_MEMBER( psattack_state::cfcard_data_r )
|
||||
{
|
||||
return m_ata->read_cs0(0, 0x0000ffff);
|
||||
return m_ata->cs0_r(0, 0x0000ffff);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( psattack_state::output_w )
|
||||
|
@ -2187,7 +2187,7 @@ WRITE8_MEMBER(taitotz_state::tlcs_rtc_w)
|
||||
|
||||
READ16_MEMBER(taitotz_state::tlcs_ide0_r)
|
||||
{
|
||||
uint16_t d = m_ata->read_cs0(offset, mem_mask);
|
||||
uint16_t d = m_ata->cs0_r(offset, mem_mask);
|
||||
if (offset == 7)
|
||||
d &= ~0x2; // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
|
||||
// The status check explicitly checks for 0x50 (drive ready, seek complete).
|
||||
@ -2196,7 +2196,7 @@ READ16_MEMBER(taitotz_state::tlcs_ide0_r)
|
||||
|
||||
READ16_MEMBER(taitotz_state::tlcs_ide1_r)
|
||||
{
|
||||
uint16_t d = m_ata->read_cs1(offset, mem_mask);
|
||||
uint16_t d = m_ata->cs1_r(offset, mem_mask);
|
||||
if (offset == 6)
|
||||
d &= ~0x2; // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
|
||||
// The status check explicitly checks for 0x50 (drive ready, seek complete).
|
||||
|
@ -55,13 +55,13 @@ private:
|
||||
uint8_t m_nvram_address_latch;
|
||||
uint8_t m_nvram_data_latch;
|
||||
|
||||
DECLARE_READ8_MEMBER(upscope_cia_0_portb_r);
|
||||
DECLARE_WRITE8_MEMBER(upscope_cia_0_portb_w);
|
||||
DECLARE_READ8_MEMBER(upscope_cia_1_porta_r);
|
||||
DECLARE_WRITE8_MEMBER(upscope_cia_1_porta_w);
|
||||
uint8_t upscope_cia_0_portb_r();
|
||||
void upscope_cia_0_portb_w(uint8_t data);
|
||||
uint8_t upscope_cia_1_porta_r();
|
||||
void upscope_cia_1_porta_w(uint8_t data);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(lamps_w);
|
||||
DECLARE_WRITE8_MEMBER(coin_counter_w);
|
||||
void lamps_w(uint8_t data);
|
||||
void coin_counter_w(uint8_t data);
|
||||
|
||||
|
||||
void a500_mem(address_map &map);
|
||||
@ -99,12 +99,12 @@ void upscope_state::machine_reset()
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( upscope_state::upscope_cia_0_portb_w )
|
||||
void upscope_state::upscope_cia_0_portb_w(uint8_t data)
|
||||
{
|
||||
m_parallel_data = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER( upscope_state::upscope_cia_0_portb_r )
|
||||
uint8_t upscope_state::upscope_cia_0_portb_r()
|
||||
{
|
||||
return m_nvram_data_latch;
|
||||
}
|
||||
@ -126,12 +126,12 @@ READ8_MEMBER( upscope_state::upscope_cia_0_portb_r )
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ8_MEMBER( upscope_state::upscope_cia_1_porta_r )
|
||||
uint8_t upscope_state::upscope_cia_1_porta_r()
|
||||
{
|
||||
return 0xf8 | (m_prev_cia1_porta & 0x07);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( upscope_state::upscope_cia_1_porta_w )
|
||||
void upscope_state::upscope_cia_1_porta_w(uint8_t data)
|
||||
{
|
||||
/* on a low transition of POUT, we latch stuff for the NVRAM */
|
||||
if ((m_prev_cia1_porta & 2) && !(data & 2))
|
||||
@ -185,7 +185,7 @@ WRITE8_MEMBER( upscope_state::upscope_cia_1_porta_w )
|
||||
m_prev_cia1_porta = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( upscope_state::lamps_w )
|
||||
void upscope_state::lamps_w(uint8_t data)
|
||||
{
|
||||
// 7------- bubble light
|
||||
// -6------ sight
|
||||
@ -197,7 +197,7 @@ WRITE8_MEMBER( upscope_state::lamps_w )
|
||||
// -------0 enemy right
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( upscope_state::coin_counter_w )
|
||||
void upscope_state::coin_counter_w(uint8_t data)
|
||||
{
|
||||
machine().bookkeeping().coin_counter_w(0, data & 1);
|
||||
}
|
||||
|
@ -1422,7 +1422,7 @@ READ64_MEMBER(viper_state::cf_card_data_r)
|
||||
{
|
||||
case 0x8: // Duplicate Even RD Data
|
||||
{
|
||||
r |= m_ata->read_cs0(0, mem_mask >> 16) << 16;
|
||||
r |= m_ata->cs0_r(0, mem_mask >> 16) << 16;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1443,7 +1443,7 @@ WRITE64_MEMBER(viper_state::cf_card_data_w)
|
||||
{
|
||||
case 0x8: // Duplicate Even RD Data
|
||||
{
|
||||
m_ata->write_cs0(0, data >> 16, mem_mask >> 16);
|
||||
m_ata->cs0_w(0, data >> 16, mem_mask >> 16);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1474,7 +1474,7 @@ READ64_MEMBER(viper_state::cf_card_r)
|
||||
case 0x6: // Select Card/Head
|
||||
case 0x7: // Status
|
||||
{
|
||||
r |= m_ata->read_cs0(offset & 7, mem_mask >> 16) << 16;
|
||||
r |= m_ata->cs0_r(offset & 7, mem_mask >> 16) << 16;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1483,13 +1483,13 @@ READ64_MEMBER(viper_state::cf_card_r)
|
||||
|
||||
case 0xd: // Duplicate Error
|
||||
{
|
||||
r |= m_ata->read_cs0(1, mem_mask >> 16) << 16;
|
||||
r |= m_ata->cs0_r(1, mem_mask >> 16) << 16;
|
||||
break;
|
||||
}
|
||||
case 0xe: // Alt Status
|
||||
case 0xf: // Drive Address
|
||||
{
|
||||
r |= m_ata->read_cs1(offset & 7, mem_mask >> 16) << 16;
|
||||
r |= m_ata->cs1_r(offset & 7, mem_mask >> 16) << 16;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1539,7 +1539,7 @@ WRITE64_MEMBER(viper_state::cf_card_w)
|
||||
case 0x6: // Select Card/Head
|
||||
case 0x7: // Command
|
||||
{
|
||||
m_ata->write_cs0(offset & 7, data >> 16, mem_mask >> 16);
|
||||
m_ata->cs0_w(offset & 7, data >> 16, mem_mask >> 16);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1548,13 +1548,13 @@ WRITE64_MEMBER(viper_state::cf_card_w)
|
||||
|
||||
case 0xd: // Duplicate Features
|
||||
{
|
||||
m_ata->write_cs0(1, data >> 16, mem_mask >> 16);
|
||||
m_ata->cs0_w(1, data >> 16, mem_mask >> 16);
|
||||
break;
|
||||
}
|
||||
case 0xe: // Device Ctl
|
||||
case 0xf: // Reserved
|
||||
{
|
||||
m_ata->write_cs1(offset & 7, data >> 16, mem_mask >> 16);
|
||||
m_ata->cs1_w(offset & 7, data >> 16, mem_mask >> 16);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1609,10 +1609,10 @@ READ64_MEMBER(viper_state::ata_r)
|
||||
switch(offset & 0x80)
|
||||
{
|
||||
case 0x00:
|
||||
r |= m_ata->read_cs0(reg, mem_mask >> 16) << 16;
|
||||
r |= m_ata->cs0_r(reg, mem_mask >> 16) << 16;
|
||||
break;
|
||||
case 0x80:
|
||||
r |= m_ata->read_cs1(reg, mem_mask >> 16) << 16;
|
||||
r |= m_ata->cs1_r(reg, mem_mask >> 16) << 16;
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -1629,10 +1629,10 @@ WRITE64_MEMBER(viper_state::ata_w)
|
||||
switch(offset & 0x80)
|
||||
{
|
||||
case 0x00:
|
||||
m_ata->write_cs0(reg, data >> 16, mem_mask >> 16);
|
||||
m_ata->cs0_w(reg, data >> 16, mem_mask >> 16);
|
||||
break;
|
||||
case 0x80:
|
||||
m_ata->write_cs1(reg, data >> 16, mem_mask >> 16);
|
||||
m_ata->cs1_w(reg, data >> 16, mem_mask >> 16);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -436,10 +436,10 @@ public:
|
||||
DECLARE_READ16_MEMBER( cia_r );
|
||||
DECLARE_WRITE16_MEMBER( cia_w );
|
||||
DECLARE_WRITE16_MEMBER( gayle_cia_w );
|
||||
DECLARE_WRITE8_MEMBER( cia_0_port_a_write );
|
||||
void cia_0_port_a_write(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER( cia_0_irq );
|
||||
DECLARE_READ8_MEMBER( cia_1_port_a_read );
|
||||
DECLARE_WRITE8_MEMBER( cia_1_port_a_write );
|
||||
uint8_t cia_1_port_a_read();
|
||||
void cia_1_port_a_write(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER( cia_1_irq );
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( rs232_rx_w );
|
||||
|
@ -193,14 +193,14 @@ public:
|
||||
unsigned char m_Psg_FunctionSelected;
|
||||
int m_previous_ppi_portc_w;
|
||||
uint8_t m_amx_mouse_data;
|
||||
DECLARE_WRITE8_MEMBER(amstrad_plus_asic_4000_w);
|
||||
DECLARE_WRITE8_MEMBER(amstrad_plus_asic_6000_w);
|
||||
DECLARE_READ8_MEMBER(amstrad_plus_asic_4000_r);
|
||||
DECLARE_READ8_MEMBER(amstrad_plus_asic_6000_r);
|
||||
DECLARE_WRITE8_MEMBER(aleste_msx_mapper);
|
||||
DECLARE_READ8_MEMBER(amstrad_cpc_io_r);
|
||||
DECLARE_WRITE8_MEMBER(amstrad_cpc_io_w);
|
||||
DECLARE_READ8_MEMBER(amstrad_psg_porta_read);
|
||||
void amstrad_plus_asic_4000_w(offs_t offset, uint8_t data);
|
||||
void amstrad_plus_asic_6000_w(offs_t offset, uint8_t data);
|
||||
uint8_t amstrad_plus_asic_4000_r(offs_t offset);
|
||||
uint8_t amstrad_plus_asic_6000_r(offs_t offset);
|
||||
void aleste_msx_mapper(offs_t offset, uint8_t data);
|
||||
uint8_t amstrad_cpc_io_r(offs_t offset);
|
||||
void amstrad_cpc_io_w(offs_t offset, uint8_t data);
|
||||
uint8_t amstrad_psg_porta_read();
|
||||
void amstrad_plus_seqcheck(int data);
|
||||
DECLARE_MACHINE_START(amstrad);
|
||||
DECLARE_MACHINE_RESET(amstrad);
|
||||
@ -230,13 +230,13 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(amstrad_plus_vsync_changed);
|
||||
DECLARE_WRITE_LINE_MEMBER(amstrad_de_changed);
|
||||
DECLARE_WRITE_LINE_MEMBER(amstrad_plus_de_changed);
|
||||
DECLARE_READ8_MEMBER(amstrad_ppi_porta_r);
|
||||
DECLARE_WRITE8_MEMBER(amstrad_ppi_porta_w);
|
||||
DECLARE_READ8_MEMBER(amstrad_ppi_portb_r);
|
||||
DECLARE_WRITE8_MEMBER(amstrad_ppi_portc_w);
|
||||
uint8_t amstrad_ppi_porta_r();
|
||||
void amstrad_ppi_porta_w(uint8_t data);
|
||||
uint8_t amstrad_ppi_portb_r();
|
||||
void amstrad_ppi_portc_w(uint8_t data);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( cpc_romdis );
|
||||
DECLARE_WRITE8_MEMBER(rom_select);
|
||||
void rom_select(uint8_t data);
|
||||
|
||||
DECLARE_FLOPPY_FORMATS( aleste_floppy_formats );
|
||||
|
||||
|
@ -167,10 +167,10 @@ public:
|
||||
DECLARE_READ8_MEMBER(apollo_dma_page_register_r);
|
||||
DECLARE_WRITE16_MEMBER(apollo_address_translation_map_w);
|
||||
DECLARE_READ16_MEMBER(apollo_address_translation_map_r);
|
||||
DECLARE_READ8_MEMBER(apollo_dma_read_byte);
|
||||
DECLARE_WRITE8_MEMBER(apollo_dma_write_byte);
|
||||
DECLARE_READ8_MEMBER(apollo_dma_read_word);
|
||||
DECLARE_WRITE8_MEMBER(apollo_dma_write_word);
|
||||
uint8_t apollo_dma_read_byte(offs_t offset);
|
||||
void apollo_dma_write_byte(offs_t offset, uint8_t data);
|
||||
uint8_t apollo_dma_read_word(offs_t offset);
|
||||
void apollo_dma_write_word(offs_t offset, uint8_t data);
|
||||
DECLARE_WRITE8_MEMBER(apollo_rtc_w);
|
||||
DECLARE_READ8_MEMBER(apollo_rtc_r);
|
||||
DECLARE_WRITE8_MEMBER(cache_control_register_w);
|
||||
@ -226,27 +226,27 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER( apollo_pic8259_master_set_int_line );
|
||||
DECLARE_WRITE_LINE_MEMBER( apollo_pic8259_slave_set_int_line );
|
||||
DECLARE_WRITE_LINE_MEMBER( sio_irq_handler );
|
||||
DECLARE_WRITE8_MEMBER( sio_output );
|
||||
void sio_output(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER( sio2_irq_handler );
|
||||
DECLARE_WRITE_LINE_MEMBER( apollo_ptm_irq_function );
|
||||
DECLARE_WRITE_LINE_MEMBER( apollo_ptm_timer_tick );
|
||||
DECLARE_READ8_MEMBER( apollo_pic8259_get_slave_ack );
|
||||
uint8_t apollo_pic8259_get_slave_ack(offs_t offset);
|
||||
DECLARE_WRITE_LINE_MEMBER( apollo_rtc_irq_function );
|
||||
|
||||
DECLARE_READ8_MEMBER(pc_dma8237_0_dack_r);
|
||||
DECLARE_READ8_MEMBER(pc_dma8237_1_dack_r);
|
||||
DECLARE_READ8_MEMBER(pc_dma8237_2_dack_r);
|
||||
DECLARE_READ8_MEMBER(pc_dma8237_3_dack_r);
|
||||
DECLARE_READ8_MEMBER(pc_dma8237_5_dack_r);
|
||||
DECLARE_READ8_MEMBER(pc_dma8237_6_dack_r);
|
||||
DECLARE_READ8_MEMBER(pc_dma8237_7_dack_r);
|
||||
DECLARE_WRITE8_MEMBER(pc_dma8237_0_dack_w);
|
||||
DECLARE_WRITE8_MEMBER(pc_dma8237_1_dack_w);
|
||||
DECLARE_WRITE8_MEMBER(pc_dma8237_2_dack_w);
|
||||
DECLARE_WRITE8_MEMBER(pc_dma8237_3_dack_w);
|
||||
DECLARE_WRITE8_MEMBER(pc_dma8237_5_dack_w);
|
||||
DECLARE_WRITE8_MEMBER(pc_dma8237_6_dack_w);
|
||||
DECLARE_WRITE8_MEMBER(pc_dma8237_7_dack_w);
|
||||
uint8_t pc_dma8237_0_dack_r();
|
||||
uint8_t pc_dma8237_1_dack_r();
|
||||
uint8_t pc_dma8237_2_dack_r();
|
||||
uint8_t pc_dma8237_3_dack_r();
|
||||
uint8_t pc_dma8237_5_dack_r();
|
||||
uint8_t pc_dma8237_6_dack_r();
|
||||
uint8_t pc_dma8237_7_dack_r();
|
||||
void pc_dma8237_0_dack_w(uint8_t data);
|
||||
void pc_dma8237_1_dack_w(uint8_t data);
|
||||
void pc_dma8237_2_dack_w(uint8_t data);
|
||||
void pc_dma8237_3_dack_w(uint8_t data);
|
||||
void pc_dma8237_5_dack_w(uint8_t data);
|
||||
void pc_dma8237_6_dack_w(uint8_t data);
|
||||
void pc_dma8237_7_dack_w(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack0_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack1_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
|
||||
|
@ -230,9 +230,9 @@ private:
|
||||
TIMER_CALLBACK_MEMBER(handle_mouse);
|
||||
TIMER_CALLBACK_MEMBER(read_COPS_command);
|
||||
TIMER_CALLBACK_MEMBER(set_COPS_ready);
|
||||
DECLARE_WRITE8_MEMBER(COPS_via_out_a);
|
||||
void COPS_via_out_a(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(COPS_via_out_ca2);
|
||||
DECLARE_WRITE8_MEMBER(COPS_via_out_b);
|
||||
void COPS_via_out_b(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(COPS_via_out_cb2);
|
||||
|
||||
void field_interrupts();
|
||||
|
@ -568,28 +568,28 @@ private:
|
||||
TIMER_CALLBACK_MEMBER(mac_pmu_tick); // macadb.c
|
||||
DECLARE_WRITE_LINE_MEMBER(mac_via_out_cb2);
|
||||
DECLARE_WRITE_LINE_MEMBER(mac_adb_via_out_cb2);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_a);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_b);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_b_ii);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_a);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_b);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_a_pmu);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_b_pmu);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_a_pmu);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_b_pmu);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_b_bbadb);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_b_egadb);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_b_cdadb);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_b_via2pmu);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_b_via2pmu);
|
||||
DECLARE_READ8_MEMBER(mac_via2_in_a);
|
||||
DECLARE_READ8_MEMBER(mac_via2_in_b);
|
||||
DECLARE_WRITE8_MEMBER(mac_via2_out_a);
|
||||
DECLARE_WRITE8_MEMBER(mac_via2_out_b);
|
||||
DECLARE_READ8_MEMBER(mac_via2_in_a_pmu);
|
||||
DECLARE_READ8_MEMBER(mac_via2_in_b_pmu);
|
||||
DECLARE_WRITE8_MEMBER(mac_via2_out_a_pmu);
|
||||
DECLARE_WRITE8_MEMBER(mac_via2_out_b_pmu);
|
||||
uint8_t mac_via_in_a();
|
||||
uint8_t mac_via_in_b();
|
||||
uint8_t mac_via_in_b_ii();
|
||||
void mac_via_out_a(uint8_t data);
|
||||
void mac_via_out_b(uint8_t data);
|
||||
uint8_t mac_via_in_a_pmu();
|
||||
uint8_t mac_via_in_b_pmu();
|
||||
void mac_via_out_a_pmu(uint8_t data);
|
||||
void mac_via_out_b_pmu(uint8_t data);
|
||||
void mac_via_out_b_bbadb(uint8_t data);
|
||||
void mac_via_out_b_egadb(uint8_t data);
|
||||
void mac_via_out_b_cdadb(uint8_t data);
|
||||
uint8_t mac_via_in_b_via2pmu();
|
||||
void mac_via_out_b_via2pmu(uint8_t data);
|
||||
uint8_t mac_via2_in_a();
|
||||
uint8_t mac_via2_in_b();
|
||||
void mac_via2_out_a(uint8_t data);
|
||||
void mac_via2_out_b(uint8_t data);
|
||||
uint8_t mac_via2_in_a_pmu();
|
||||
uint8_t mac_via2_in_b_pmu();
|
||||
void mac_via2_out_a_pmu(uint8_t data);
|
||||
void mac_via2_out_b_pmu(uint8_t data);
|
||||
void mac_state_load();
|
||||
DECLARE_WRITE_LINE_MEMBER(mac_via_irq);
|
||||
DECLARE_WRITE_LINE_MEMBER(mac_via2_irq);
|
||||
|
@ -154,10 +154,10 @@ private:
|
||||
emu_timer *m_scanline_timer;
|
||||
uint32_t screen_update_pippin(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
TIMER_CALLBACK_MEMBER(mac_6015_tick);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_a);
|
||||
DECLARE_READ8_MEMBER(mac_via_in_b);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_a);
|
||||
DECLARE_WRITE8_MEMBER(mac_via_out_b);
|
||||
uint8_t mac_via_in_a();
|
||||
uint8_t mac_via_in_b();
|
||||
void mac_via_out_a(uint8_t data);
|
||||
void mac_via_out_b(uint8_t data);
|
||||
DECLARE_READ_LINE_MEMBER(mac_adb_via_in_cb2);
|
||||
DECLARE_WRITE_LINE_MEMBER(mac_adb_via_out_cb2);
|
||||
DECLARE_WRITE_LINE_MEMBER(mac_via_irq);
|
||||
|
@ -84,7 +84,7 @@ public:
|
||||
emu_timer *m_prn_pins;
|
||||
emu_timer *m_pulse_timer;
|
||||
emu_timer *m_beep_setup_timer;
|
||||
DECLARE_READ8_MEMBER(pcw_keyboard_r);
|
||||
uint8_t pcw_keyboard_r(offs_t offset);
|
||||
DECLARE_READ8_MEMBER(pcw_keyboard_data_r);
|
||||
DECLARE_READ8_MEMBER(pcw_interrupt_counter_r);
|
||||
DECLARE_WRITE8_MEMBER(pcw_bank_select_w);
|
||||
@ -100,17 +100,17 @@ public:
|
||||
DECLARE_WRITE8_MEMBER(pcw_printer_command_w);
|
||||
DECLARE_READ8_MEMBER(pcw_printer_data_r);
|
||||
DECLARE_READ8_MEMBER(pcw_printer_status_r);
|
||||
DECLARE_READ8_MEMBER(mcu_printer_p1_r);
|
||||
DECLARE_WRITE8_MEMBER(mcu_printer_p1_w);
|
||||
DECLARE_READ8_MEMBER(mcu_printer_p2_r);
|
||||
DECLARE_WRITE8_MEMBER(mcu_printer_p2_w);
|
||||
uint8_t mcu_printer_p1_r();
|
||||
void mcu_printer_p1_w(uint8_t data);
|
||||
uint8_t mcu_printer_p2_r();
|
||||
void mcu_printer_p2_w(uint8_t data);
|
||||
DECLARE_READ_LINE_MEMBER(mcu_printer_t1_r);
|
||||
DECLARE_READ_LINE_MEMBER(mcu_printer_t0_r);
|
||||
DECLARE_READ8_MEMBER(mcu_kb_scan_r);
|
||||
DECLARE_WRITE8_MEMBER(mcu_kb_scan_w);
|
||||
DECLARE_READ8_MEMBER(mcu_kb_scan_high_r);
|
||||
DECLARE_WRITE8_MEMBER(mcu_kb_scan_high_w);
|
||||
DECLARE_READ8_MEMBER(mcu_kb_data_r);
|
||||
uint8_t mcu_kb_scan_r();
|
||||
void mcu_kb_scan_w(uint8_t data);
|
||||
uint8_t mcu_kb_scan_high_r();
|
||||
void mcu_kb_scan_high_w(uint8_t data);
|
||||
uint8_t mcu_kb_data_r();
|
||||
DECLARE_READ_LINE_MEMBER(mcu_kb_t1_r);
|
||||
DECLARE_READ_LINE_MEMBER(mcu_kb_t0_r);
|
||||
DECLARE_READ8_MEMBER(pcw9512_parallel_r);
|
||||
|
@ -1073,7 +1073,7 @@ CUSTOM_INPUT_MEMBER( amiga_state::floppy_drive_status )
|
||||
return m_fdc->ciaapra_r();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( amiga_state::cia_0_port_a_write )
|
||||
void amiga_state::cia_0_port_a_write(uint8_t data)
|
||||
{
|
||||
// bit 0, kickstart overlay
|
||||
m_overlay->set_bank(BIT(data, 0));
|
||||
@ -1091,7 +1091,7 @@ WRITE_LINE_MEMBER( amiga_state::cia_0_irq )
|
||||
update_int2();
|
||||
}
|
||||
|
||||
READ8_MEMBER( amiga_state::cia_1_port_a_read )
|
||||
uint8_t amiga_state::cia_1_port_a_read()
|
||||
{
|
||||
uint8_t data = 0;
|
||||
|
||||
@ -1109,7 +1109,7 @@ READ8_MEMBER( amiga_state::cia_1_port_a_read )
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( amiga_state::cia_1_port_a_write )
|
||||
void amiga_state::cia_1_port_a_write(uint8_t data)
|
||||
{
|
||||
if (m_rs232)
|
||||
{
|
||||
|
@ -1160,10 +1160,10 @@ void amstrad_state::amstrad_setLowerRom()
|
||||
|
||||
/* if ( m_asic.enabled && ( m_asic.rmr2 & 0x18 ) == 0x18 )
|
||||
{
|
||||
space.install_read_handler(0x4000, 0x5fff, read8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_r)));
|
||||
space.install_read_handler(0x6000, 0x7fff, read8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_r)));
|
||||
space.install_write_handler(0x4000, 0x5fff, write8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_w)));
|
||||
space.install_write_handler(0x6000, 0x7fff, write8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_w)));
|
||||
space.install_read_handler(0x4000, 0x5fff, read8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_r)));
|
||||
space.install_read_handler(0x6000, 0x7fff, read8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_r)));
|
||||
space.install_write_handler(0x4000, 0x5fff, write8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_w)));
|
||||
space.install_write_handler(0x6000, 0x7fff, write8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_w)));
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -1383,7 +1383,7 @@ void amstrad_state::AmstradCPC_GA_SetRamConfiguration()
|
||||
|
||||
*/
|
||||
|
||||
WRITE8_MEMBER(amstrad_state::amstrad_plus_asic_4000_w)
|
||||
void amstrad_state::amstrad_plus_asic_4000_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
// logerror("ASIC: Write to register at &%04x\n",offset+0x4000);
|
||||
if ( m_asic.enabled && ( m_asic.rmr2 & 0x18 ) == 0x18 )
|
||||
@ -1396,7 +1396,7 @@ WRITE8_MEMBER(amstrad_state::amstrad_plus_asic_4000_w)
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(amstrad_state::amstrad_plus_asic_6000_w)
|
||||
void amstrad_state::amstrad_plus_asic_6000_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
if ( m_asic.enabled && ( m_asic.rmr2 & 0x18 ) == 0x18 )
|
||||
{
|
||||
@ -1499,7 +1499,7 @@ WRITE8_MEMBER(amstrad_state::amstrad_plus_asic_6000_w)
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER(amstrad_state::amstrad_plus_asic_4000_r)
|
||||
uint8_t amstrad_state::amstrad_plus_asic_4000_r(offs_t offset)
|
||||
{
|
||||
// logerror("RAM: read from &%04x\n",offset+0x4000);
|
||||
if ( m_asic.enabled && ( m_asic.rmr2 & 0x18 ) == 0x18 )
|
||||
@ -1512,7 +1512,7 @@ READ8_MEMBER(amstrad_state::amstrad_plus_asic_4000_r)
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER(amstrad_state::amstrad_plus_asic_6000_r)
|
||||
uint8_t amstrad_state::amstrad_plus_asic_6000_r(offs_t offset)
|
||||
{
|
||||
// logerror("RAM: read from &%04x\n",offset+0x6000);
|
||||
if ( m_asic.enabled && ( m_asic.rmr2 & 0x18 ) == 0x18 )
|
||||
@ -1711,7 +1711,7 @@ In the 464+ and 6128+ this function is performed by the ASIC or a memory expansi
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(amstrad_state::aleste_msx_mapper)
|
||||
void amstrad_state::aleste_msx_mapper(offs_t offset, uint8_t data)
|
||||
{
|
||||
int page = (offset & 0x0300) >> 8;
|
||||
int ramptr = (data & 0x3f) * 0x4000;
|
||||
@ -1837,7 +1837,7 @@ Expansion Peripherals Read/Write - - - - - 0 - - - - - -
|
||||
|
||||
*/
|
||||
|
||||
READ8_MEMBER(amstrad_state::amstrad_cpc_io_r)
|
||||
uint8_t amstrad_state::amstrad_cpc_io_r(offs_t offset)
|
||||
{
|
||||
uint8_t data = 0xFF;
|
||||
unsigned int r1r0 = (unsigned int)((offset & 0x0300) >> 8);
|
||||
@ -1987,7 +1987,7 @@ void amstrad_state::amstrad_plus_seqcheck(int data)
|
||||
m_prev_data = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(amstrad_state::rom_select)
|
||||
void amstrad_state::rom_select(uint8_t data)
|
||||
{
|
||||
m_gate_array.upper_bank = data;
|
||||
// expansion devices know the selected ROM by monitoring I/O writes to DFxx
|
||||
@ -2015,7 +2015,7 @@ WRITE8_MEMBER(amstrad_state::rom_select)
|
||||
}
|
||||
|
||||
/* Offset handler for write */
|
||||
WRITE8_MEMBER(amstrad_state::amstrad_cpc_io_w)
|
||||
void amstrad_state::amstrad_cpc_io_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
cpc_multiface2_device* mface2;
|
||||
|
||||
@ -2023,7 +2023,7 @@ WRITE8_MEMBER(amstrad_state::amstrad_cpc_io_w)
|
||||
{
|
||||
if(m_aleste_mode & 0x04) // Aleste mode
|
||||
{
|
||||
aleste_msx_mapper(space, offset, data);
|
||||
aleste_msx_mapper(offset, data);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -2080,7 +2080,7 @@ WRITE8_MEMBER(amstrad_state::amstrad_cpc_io_w)
|
||||
/* b13 = 0 : ROM select Write Selected*/
|
||||
if ((offset & (1<<13)) == 0)
|
||||
{
|
||||
rom_select(space,0,data);
|
||||
rom_select(data);
|
||||
}
|
||||
|
||||
/* b12 = 0 : Printer port Write Selected*/
|
||||
@ -2534,14 +2534,14 @@ void amstrad_state::update_psg()
|
||||
|
||||
|
||||
/* Read/Write 8255 PPI port A (connected to AY-3-8912 databus) */
|
||||
READ8_MEMBER(amstrad_state::amstrad_ppi_porta_r)
|
||||
uint8_t amstrad_state::amstrad_ppi_porta_r()
|
||||
{
|
||||
update_psg();
|
||||
return m_ppi_port_inputs[amstrad_ppi_PortA];
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(amstrad_state::amstrad_ppi_porta_w)
|
||||
void amstrad_state::amstrad_ppi_porta_w(uint8_t data)
|
||||
{
|
||||
m_ppi_port_outputs[amstrad_ppi_PortA] = data;
|
||||
update_psg();
|
||||
@ -2578,7 +2578,7 @@ WRITE_LINE_MEMBER(amstrad_state::write_centronics_busy)
|
||||
m_centronics_busy = state;
|
||||
}
|
||||
|
||||
READ8_MEMBER(amstrad_state::amstrad_ppi_portb_r)
|
||||
uint8_t amstrad_state::amstrad_ppi_portb_r()
|
||||
{
|
||||
int data = 0;
|
||||
/* Set b7 with cassette tape input */
|
||||
@ -2630,7 +2630,7 @@ Bit Description Usage
|
||||
|
||||
/* previous_ppi_portc_w value */
|
||||
|
||||
WRITE8_MEMBER(amstrad_state::amstrad_ppi_portc_w)
|
||||
void amstrad_state::amstrad_ppi_portc_w(uint8_t data)
|
||||
{
|
||||
int changed_data;
|
||||
|
||||
@ -2679,7 +2679,7 @@ When port B is defined as input (bit 7 of register 7 is set to "0"), a read of t
|
||||
*/
|
||||
|
||||
/* read PSG port A */
|
||||
READ8_MEMBER(amstrad_state::amstrad_psg_porta_read)
|
||||
uint8_t amstrad_state::amstrad_psg_porta_read()
|
||||
{
|
||||
/* Read CPC Keyboard
|
||||
If keyboard matrix line 11-15 are selected, the byte is always &ff.
|
||||
@ -3144,10 +3144,10 @@ MACHINE_RESET_MEMBER(amstrad_state,plus)
|
||||
AmstradCPC_GA_SetRamConfiguration();
|
||||
amstrad_GateArray_write(0x081); // Epyx World of Sports requires upper ROM to be enabled by default
|
||||
|
||||
space.install_read_handler(0x4000, 0x5fff, read8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_r)));
|
||||
space.install_read_handler(0x6000, 0x7fff, read8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_r)));
|
||||
space.install_write_handler(0x4000, 0x5fff, write8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_w)));
|
||||
space.install_write_handler(0x6000, 0x7fff, write8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_w)));
|
||||
space.install_read_handler(0x4000, 0x5fff, read8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_r)));
|
||||
space.install_read_handler(0x6000, 0x7fff, read8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_r)));
|
||||
space.install_write_handler(0x4000, 0x5fff, write8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_w)));
|
||||
space.install_write_handler(0x6000, 0x7fff, write8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_w)));
|
||||
|
||||
// multiface_init();
|
||||
timer_set(attotime::zero, TIMER_SET_RESOLUTION);
|
||||
@ -3187,10 +3187,10 @@ MACHINE_RESET_MEMBER(amstrad_state,gx4000)
|
||||
AmstradCPC_GA_SetRamConfiguration();
|
||||
amstrad_GateArray_write(0x081); // Epyx World of Sports requires upper ROM to be enabled by default
|
||||
// multiface_init();
|
||||
space.install_read_handler(0x4000, 0x5fff, read8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_r)));
|
||||
space.install_read_handler(0x6000, 0x7fff, read8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_r)));
|
||||
space.install_write_handler(0x4000, 0x5fff, write8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_w)));
|
||||
space.install_write_handler(0x6000, 0x7fff, write8_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_w)));
|
||||
space.install_read_handler(0x4000, 0x5fff, read8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_r)));
|
||||
space.install_read_handler(0x6000, 0x7fff, read8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_r)));
|
||||
space.install_write_handler(0x4000, 0x5fff, write8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_4000_w)));
|
||||
space.install_write_handler(0x6000, 0x7fff, write8sm_delegate(*this, FUNC(amstrad_state::amstrad_plus_asic_6000_w)));
|
||||
|
||||
timer_set(attotime::zero, TIMER_SET_RESOLUTION);
|
||||
}
|
||||
|
@ -386,7 +386,7 @@ READ16_MEMBER(apollo_state::apollo_address_translation_map_r){
|
||||
return data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(apollo_state::apollo_dma_read_byte){
|
||||
uint8_t apollo_state::apollo_dma_read_byte(offs_t offset){
|
||||
uint8_t data;
|
||||
offs_t page_offset;
|
||||
|
||||
@ -408,7 +408,7 @@ READ8_MEMBER(apollo_state::apollo_dma_read_byte){
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(apollo_state::apollo_dma_write_byte){
|
||||
void apollo_state::apollo_dma_write_byte(offs_t offset, uint8_t data){
|
||||
offs_t page_offset;
|
||||
if (apollo_is_dn3000()) {
|
||||
page_offset = dma_page_register[channel2page_register[dn3000_dma_channel1]] << 16;
|
||||
@ -427,7 +427,7 @@ WRITE8_MEMBER(apollo_state::apollo_dma_write_byte){
|
||||
// logerror(" %02x", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(apollo_state::apollo_dma_read_word){
|
||||
uint8_t apollo_state::apollo_dma_read_word(offs_t offset){
|
||||
uint16_t data;
|
||||
offs_t page_offset;
|
||||
|
||||
@ -448,7 +448,7 @@ READ8_MEMBER(apollo_state::apollo_dma_read_word){
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(apollo_state::apollo_dma_write_word){
|
||||
void apollo_state::apollo_dma_write_word(offs_t offset, uint8_t data){
|
||||
offs_t page_offset;
|
||||
|
||||
SLOG1(("dma write word at offset %x = %02x", offset, data));
|
||||
@ -495,21 +495,21 @@ WRITE_LINE_MEMBER(apollo_state::apollo_dma_2_hrq_changed ) {
|
||||
m_dma8237_2->hack_w(state);
|
||||
}
|
||||
|
||||
READ8_MEMBER( apollo_state::pc_dma8237_0_dack_r ) { return m_isa->dack_r(0); }
|
||||
READ8_MEMBER( apollo_state::pc_dma8237_1_dack_r ) { return m_isa->dack_r(1); }
|
||||
READ8_MEMBER( apollo_state::pc_dma8237_2_dack_r ) { return m_isa->dack_r(2); }
|
||||
READ8_MEMBER( apollo_state::pc_dma8237_3_dack_r ) { return m_isa->dack_r(3); }
|
||||
READ8_MEMBER( apollo_state::pc_dma8237_5_dack_r ) { return m_isa->dack_r(5); }
|
||||
READ8_MEMBER( apollo_state::pc_dma8237_6_dack_r ) { return m_isa->dack_r(6); }
|
||||
READ8_MEMBER( apollo_state::pc_dma8237_7_dack_r ) { return m_isa->dack_r(7); }
|
||||
uint8_t apollo_state::pc_dma8237_0_dack_r() { return m_isa->dack_r(0); }
|
||||
uint8_t apollo_state::pc_dma8237_1_dack_r() { return m_isa->dack_r(1); }
|
||||
uint8_t apollo_state::pc_dma8237_2_dack_r() { return m_isa->dack_r(2); }
|
||||
uint8_t apollo_state::pc_dma8237_3_dack_r() { return m_isa->dack_r(3); }
|
||||
uint8_t apollo_state::pc_dma8237_5_dack_r() { return m_isa->dack_r(5); }
|
||||
uint8_t apollo_state::pc_dma8237_6_dack_r() { return m_isa->dack_r(6); }
|
||||
uint8_t apollo_state::pc_dma8237_7_dack_r() { return m_isa->dack_r(7); }
|
||||
|
||||
WRITE8_MEMBER( apollo_state::pc_dma8237_0_dack_w ){ m_isa->dack_w(0, data); }
|
||||
WRITE8_MEMBER( apollo_state::pc_dma8237_1_dack_w ){ m_isa->dack_w(1, data); }
|
||||
WRITE8_MEMBER( apollo_state::pc_dma8237_2_dack_w ){ m_isa->dack_w(2, data); }
|
||||
WRITE8_MEMBER( apollo_state::pc_dma8237_3_dack_w ){ m_isa->dack_w(3, data); }
|
||||
WRITE8_MEMBER( apollo_state::pc_dma8237_5_dack_w ){ m_isa->dack_w(5, data); }
|
||||
WRITE8_MEMBER( apollo_state::pc_dma8237_6_dack_w ){ m_isa->dack_w(6, data); }
|
||||
WRITE8_MEMBER( apollo_state::pc_dma8237_7_dack_w ){ m_isa->dack_w(7, data); }
|
||||
void apollo_state::pc_dma8237_0_dack_w(uint8_t data){ m_isa->dack_w(0, data); }
|
||||
void apollo_state::pc_dma8237_1_dack_w(uint8_t data){ m_isa->dack_w(1, data); }
|
||||
void apollo_state::pc_dma8237_2_dack_w(uint8_t data){ m_isa->dack_w(2, data); }
|
||||
void apollo_state::pc_dma8237_3_dack_w(uint8_t data){ m_isa->dack_w(3, data); }
|
||||
void apollo_state::pc_dma8237_5_dack_w(uint8_t data){ m_isa->dack_w(5, data); }
|
||||
void apollo_state::pc_dma8237_6_dack_w(uint8_t data){ m_isa->dack_w(6, data); }
|
||||
void apollo_state::pc_dma8237_7_dack_w(uint8_t data){ m_isa->dack_w(7, data); }
|
||||
|
||||
WRITE_LINE_MEMBER( apollo_state::pc_dack0_w ) { select_dma_channel(0, state); }
|
||||
WRITE_LINE_MEMBER( apollo_state::pc_dack1_w ) { select_dma_channel(1, state); }
|
||||
@ -591,7 +591,7 @@ u16 apollo_state::apollo_pic_get_vector()
|
||||
* pic8259 configuration
|
||||
*************************************************************/
|
||||
|
||||
READ8_MEMBER( apollo_state::apollo_pic8259_get_slave_ack )
|
||||
uint8_t apollo_state::apollo_pic8259_get_slave_ack(offs_t offset)
|
||||
{
|
||||
MLOG1(("apollo_pic8259_get_slave_ack: offset=%x", offset));
|
||||
|
||||
@ -799,7 +799,7 @@ WRITE_LINE_MEMBER(apollo_state::sio_irq_handler)
|
||||
apollo_pic_set_irq_line(APOLLO_IRQ_SIO1, state);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(apollo_state::sio_output)
|
||||
void apollo_state::sio_output(uint8_t data)
|
||||
{
|
||||
// CLOG2(("apollo_sio - sio_output %02x", data));
|
||||
|
||||
|
@ -633,7 +633,7 @@ void lisa_state::init_COPS()
|
||||
CA1 (I) : COPS sending valid data
|
||||
CA2 (O) : VIA -> COPS handshake
|
||||
*/
|
||||
WRITE8_MEMBER(lisa_state::COPS_via_out_a)
|
||||
void lisa_state::COPS_via_out_a(uint8_t data)
|
||||
{
|
||||
// printf("VIA A = %02x\n", data);
|
||||
m_COPS_command = data;
|
||||
@ -664,7 +664,7 @@ WRITE_LINE_MEMBER(lisa_state::COPS_via_out_ca2)
|
||||
CB2 (O) : sound output
|
||||
*/
|
||||
|
||||
WRITE8_MEMBER(lisa_state::COPS_via_out_b)
|
||||
void lisa_state::COPS_via_out_b(uint8_t data)
|
||||
{
|
||||
/* pull-up */
|
||||
data |= (~ m_via0->read(via6522_device::VIA_DDRA)) & 0x01;
|
||||
|
@ -1279,7 +1279,7 @@ WRITE_LINE_MEMBER(mac_state::mac_adb_via_out_cb2)
|
||||
#define PA2 0x04
|
||||
#define PA1 0x02
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via_in_a)
|
||||
uint8_t mac_state::mac_via_in_a()
|
||||
{
|
||||
// printf("%s VIA1 IN_A\n", machine().describe_context().c_str());
|
||||
|
||||
@ -1335,7 +1335,7 @@ READ8_MEMBER(mac_state::mac_via_in_a)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via_in_a_pmu)
|
||||
uint8_t mac_state::mac_via_in_a_pmu()
|
||||
{
|
||||
// printf("%s VIA1 IN_A\n", machine().describe_context().c_str());
|
||||
|
||||
@ -1345,7 +1345,7 @@ READ8_MEMBER(mac_state::mac_via_in_a_pmu)
|
||||
return m_pm_data_recv;
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via_in_b)
|
||||
uint8_t mac_state::mac_via_in_b()
|
||||
{
|
||||
int val = 0;
|
||||
/* video beam in display (! VBLANK && ! HBLANK basically) */
|
||||
@ -1388,7 +1388,7 @@ READ8_MEMBER(mac_state::mac_via_in_b)
|
||||
return val;
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via_in_b_ii)
|
||||
uint8_t mac_state::mac_via_in_b_ii()
|
||||
{
|
||||
int val = 0;
|
||||
|
||||
@ -1417,7 +1417,7 @@ READ8_MEMBER(mac_state::mac_via_in_b_ii)
|
||||
return val;
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via_in_b_via2pmu)
|
||||
uint8_t mac_state::mac_via_in_b_via2pmu()
|
||||
{
|
||||
int val = 0;
|
||||
// TODO: is this valid for VIA2 PMU machines?
|
||||
@ -1432,7 +1432,7 @@ READ8_MEMBER(mac_state::mac_via_in_b_via2pmu)
|
||||
return val;
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via_in_b_pmu)
|
||||
uint8_t mac_state::mac_via_in_b_pmu()
|
||||
{
|
||||
int val = 0;
|
||||
// printf("Read VIA B: PM_ACK %x\n", m_pm_ack);
|
||||
@ -1443,7 +1443,7 @@ READ8_MEMBER(mac_state::mac_via_in_b_pmu)
|
||||
return val;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via_out_a)
|
||||
void mac_state::mac_via_out_a(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT A: %02x\n", machine().describe_context().c_str(), data);
|
||||
|
||||
@ -1475,7 +1475,7 @@ WRITE8_MEMBER(mac_state::mac_via_out_a)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via_out_a_pmu)
|
||||
void mac_state::mac_via_out_a_pmu(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT A: %02x\n", machine().describe_context().c_str(), data);
|
||||
|
||||
@ -1485,7 +1485,7 @@ WRITE8_MEMBER(mac_state::mac_via_out_a_pmu)
|
||||
m_pm_data_send = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via_out_b)
|
||||
void mac_state::mac_via_out_b(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT B: %02x\n", machine().describe_context().c_str(), data);
|
||||
|
||||
@ -1520,7 +1520,7 @@ void mac_state::update_volume(void)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via_out_b_bbadb)
|
||||
void mac_state::mac_via_out_b_bbadb(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT B: %02x\n", machine().describe_context().c_str(), data);
|
||||
|
||||
@ -1556,7 +1556,7 @@ WRITE8_MEMBER(mac_state::mac_via_out_b_bbadb)
|
||||
m_rtc->clk_w((data >> 1) & 0x01);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via_out_b_egadb)
|
||||
void mac_state::mac_via_out_b_egadb(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT B: %02x\n", machine().describe_context().c_str(), data);
|
||||
|
||||
@ -1567,7 +1567,7 @@ WRITE8_MEMBER(mac_state::mac_via_out_b_egadb)
|
||||
m_egret->set_sys_session((data&0x20) ? 1 : 0);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via_out_b_cdadb)
|
||||
void mac_state::mac_via_out_b_cdadb(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT B: %02x\n", machine().describe_context().c_str(), data);
|
||||
|
||||
@ -1578,12 +1578,12 @@ WRITE8_MEMBER(mac_state::mac_via_out_b_cdadb)
|
||||
m_cuda->set_tip((data&0x20) ? 1 : 0);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via_out_b_via2pmu)
|
||||
void mac_state::mac_via_out_b_via2pmu(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT B: %02x\n", machine().describe_context().c_str(), data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via_out_b_pmu)
|
||||
void mac_state::mac_via_out_b_pmu(uint8_t data)
|
||||
{
|
||||
// printf("%s VIA1 OUT B: %02x\n", machine().describe_context().c_str(), data);
|
||||
|
||||
@ -1723,7 +1723,7 @@ WRITE16_MEMBER ( mac_state::mac_via2_w )
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via2_in_a)
|
||||
uint8_t mac_state::mac_via2_in_a()
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
@ -1739,12 +1739,12 @@ READ8_MEMBER(mac_state::mac_via2_in_a)
|
||||
return result;
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via2_in_a_pmu)
|
||||
uint8_t mac_state::mac_via2_in_a_pmu()
|
||||
{
|
||||
return m_pm_data_recv;
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via2_in_b)
|
||||
uint8_t mac_state::mac_via2_in_b()
|
||||
{
|
||||
// logerror("%s VIA2 IN B\n", machine().describe_context());
|
||||
|
||||
@ -1761,7 +1761,7 @@ READ8_MEMBER(mac_state::mac_via2_in_b)
|
||||
return 0xcf; // indicate no NuBus transaction error
|
||||
}
|
||||
|
||||
READ8_MEMBER(mac_state::mac_via2_in_b_pmu)
|
||||
uint8_t mac_state::mac_via2_in_b_pmu()
|
||||
{
|
||||
// logerror("%s VIA2 IN B\n", machine().describe_context());
|
||||
|
||||
@ -1775,18 +1775,18 @@ READ8_MEMBER(mac_state::mac_via2_in_b_pmu)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via2_out_a)
|
||||
void mac_state::mac_via2_out_a(uint8_t data)
|
||||
{
|
||||
// logerror("%s VIA2 OUT A: %02x\n", machine().describe_context(), data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via2_out_a_pmu)
|
||||
void mac_state::mac_via2_out_a_pmu(uint8_t data)
|
||||
{
|
||||
// logerror("%s VIA2 OUT A: %02x\n", machine().describe_context(), data);
|
||||
m_pm_data_send = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via2_out_b)
|
||||
void mac_state::mac_via2_out_b(uint8_t data)
|
||||
{
|
||||
// logerror("%s VIA2 OUT B: %02x\n", machine().describe_context(), data);
|
||||
|
||||
@ -1800,7 +1800,7 @@ WRITE8_MEMBER(mac_state::mac_via2_out_b)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mac_state::mac_via2_out_b_pmu)
|
||||
void mac_state::mac_via2_out_b_pmu(uint8_t data)
|
||||
{
|
||||
// logerror("%s VIA2 OUT B PMU: %02x\n", machine().describe_context(), data);
|
||||
|
||||
|
@ -30,14 +30,14 @@ WRITE_LINE_MEMBER(macpci_state::mac_via_irq)
|
||||
{
|
||||
}
|
||||
|
||||
READ8_MEMBER(macpci_state::mac_via_in_a)
|
||||
uint8_t macpci_state::mac_via_in_a()
|
||||
{
|
||||
// printf("VIA1 IN_A (PC %x)\n", mac->m_maincpu->pc());
|
||||
|
||||
return 0x80;
|
||||
}
|
||||
|
||||
READ8_MEMBER(macpci_state::mac_via_in_b)
|
||||
uint8_t macpci_state::mac_via_in_b()
|
||||
{
|
||||
int val = 0;
|
||||
val |= m_cuda->get_treq()<<3;
|
||||
@ -47,12 +47,12 @@ READ8_MEMBER(macpci_state::mac_via_in_b)
|
||||
return val;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(macpci_state::mac_via_out_a)
|
||||
void macpci_state::mac_via_out_a(uint8_t data)
|
||||
{
|
||||
// printf("VIA1 OUT A: %02x (PC %x)\n", data, m_maincpu->pc());
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(macpci_state::mac_via_out_b)
|
||||
void macpci_state::mac_via_out_b(uint8_t data)
|
||||
{
|
||||
// printf("VIA1 OUT B: %02x (PC %x)\n", data, m_maincpu->pc());
|
||||
|
||||
|
@ -312,7 +312,7 @@ WRITE32_MEMBER( turrett_state::dma_w )
|
||||
|
||||
while (words--)
|
||||
{
|
||||
ram[addr & DIMM_BANK_MASK] = m_ata->read_cs0(0);
|
||||
ram[addr & DIMM_BANK_MASK] = m_ata->cs0_r(0);
|
||||
++addr;
|
||||
}
|
||||
|
||||
@ -324,7 +324,7 @@ WRITE32_MEMBER( turrett_state::dma_w )
|
||||
{
|
||||
while (words--)
|
||||
{
|
||||
uint16_t data = m_ata->read_cs0(0);
|
||||
uint16_t data = m_ata->cs0_r(0);
|
||||
|
||||
// TODO: Verify if this is correct
|
||||
if ((data & 0xc400) == 0xc400)
|
||||
|
Loading…
Reference in New Issue
Block a user