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(MESS) nes.c: moved bankswitch functions into nes_carts_state. no whatsnew.

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among other things, this  allowed to remove around a thousand of machine() parameters 
passed to re-get the state class at each bankswitch operation. readability says thanks.
This commit is contained in:
Fabio Priuli 2012-09-23 09:18:37 +00:00
parent 7ad98c13be
commit 326c860ac7
6 changed files with 1357 additions and 1385 deletions
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22
src/mess/includes/nes.h
View File

@ -67,7 +67,7 @@ public:
void init_nes_core();
void pcb_handlers_setup();
int pcb_initialize(int idx);
DECLARE_WRITE8_MEMBER(nes_chr_w);
DECLARE_READ8_MEMBER(nes_chr_r);
DECLARE_WRITE8_MEMBER(nes_nt_w);
@ -82,22 +82,14 @@ public:
read8_delegate m_mmc_read_low;
read8_delegate m_mmc_read_mid;
read8_delegate m_mmc_read;
/* devices */
// cpu_device *m_maincpu;
// ppu2c0x_device *m_ppu;
// device_t *m_sound;
// cpu_device *m_maincpu;
// ppu2c0x_device *m_ppu;
// device_t *m_sound;
device_t *m_cart;
// emu_timer *m_irq_timer;
/* misc region to be allocated at init */
// variables which don't change at run-time
UINT8 *m_rom;
UINT8 *m_prg;
UINT8 *m_vrom;
UINT8 *m_vram;
UINT8 *m_ciram; //PPU nametable RAM - external to PPU!
// emu_timer *m_irq_timer;
/***** FDS-floppy related *****/
int m_disk_expansion;

103
src/mess/includes/nes_mmc.h
View File

@ -152,27 +152,28 @@ class nes_carts_state : public driver_device
public:
nes_carts_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag) { }
int m_prg_bank[5];
chr_bank m_chr_map[8]; //quick banking structure, because some of this changes multiple times per scanline!
name_table m_nt_page[4]; //quick banking structure for a maximum of 4K of RAM/ROM/ExRAM
nes_prg_callback m_mmc3_prg_cb; // these are used to simplify a lot emulation of some MMC3 pirate clones
nes_chr_callback m_mmc3_chr_cb;
// mapper variables (to be sorted out at some point, to split more complex mappers as separate devices)
int m_chr_open_bus;
int m_prgram_bank5_start, m_battery_bank5_start, m_empty_bank5_start;
UINT8 m_ce_mask, m_ce_state;
UINT8 m_vrc_ls_prg_a, m_vrc_ls_prg_b, m_vrc_ls_chr;
int m_MMC5_floodtile;
int m_MMC5_floodattr;
int m_mmc5_vram_control;
UINT8 m_mmc5_high_chr;
UINT8 m_mmc5_split_scr;
UINT8 *m_extended_ntram;
UINT8 m_mmc5_last_chr_a;
UINT16 m_mmc5_vrom_regA[8];
UINT16 m_mmc5_vrom_regB[4];
@ -184,9 +185,9 @@ public:
UINT8 m_mmc5_split_ctrl;
UINT8 m_mmc5_split_yst;
UINT8 m_mmc5_split_bank;
/***** Mapper-related variables *****/
// common ones
int m_IRQ_enable, m_IRQ_enable_latch;
UINT16 m_IRQ_count, m_IRQ_count_latch;
@ -196,37 +197,37 @@ public:
UINT8 m_IRQ_mode;
UINT8 m_IRQ_clear;
int m_mult1, m_mult2;
UINT8 m_mmc_chr_source; // This is set at init to CHRROM or CHRRAM. a few mappers can swap between
// the two (this is done in the specific handlers).
UINT8 m_mmc_cmd1, m_mmc_cmd2; // These represent registers where the mapper writes important values
UINT8 m_mmc_count; // This is used as counter in mappers like 1 and 45
int m_mmc_prg_base, m_mmc_prg_mask; // MMC3 based multigame carts select a block of banks by using these (and then act like normal MMC3),
int m_mmc_chr_base, m_mmc_chr_mask; // while MMC3 and clones (mapper 118 & 119) simply set them as 0 and 0xff resp.
UINT8 m_mmc_prg_bank[6]; // Many mappers writes only some bits of the selected bank (for both PRG and CHR),
UINT8 m_mmc_vrom_bank[16]; // hence these are handy to latch bank values.
UINT16 m_MMC5_vrom_bank[12]; // MMC5 has 10bit wide VROM regs!
UINT8 m_mmc_extra_bank[16]; // some MMC3 clone have 2 series of PRG/CHR banks...
// we collect them all here: first 4 elements PRG banks, then 6/8 CHR banks
UINT8 m_mmc_latch1, m_mmc_latch2;
UINT8 m_mmc_reg[16];
UINT8 m_mmc_dipsetting;
// misc mapper related variables which should be merged with the above one, where possible
int m_mmc1_reg_write_enable;
int m_mmc1_latch;
int m_mmc1_count;
int m_mmc3_latch;
int m_mmc3_wram_protect;
int m_mmc3_alt_irq;
int m_MMC5_rom_bank_mode;
int m_MMC5_vrom_bank_mode;
int m_MMC5_vram_protect;
@ -234,9 +235,9 @@ public:
int m_vrom_page_a;
int m_vrom_page_b;
// int vrom_next[4];
UINT8 m_mmc6_reg;
// these might be unified in single mmc_reg[] array, together with state->m_mmc_cmd1 & state->m_mmc_cmd2
// but be careful that MMC3 clones often use state->m_mmc_cmd1/state->m_mmc_cmd2 (from base MMC3) AND additional regs below!
UINT8 m_mapper83_reg[10];
@ -246,7 +247,7 @@ public:
UINT8 m_sachen_reg[8]; // used by mappers 137, 138, 139 & 141
UINT8 m_map52_reg_written;
UINT8 m_map114_reg, m_map114_reg_enabled;
// i/o handlers
DECLARE_WRITE8_MEMBER(mapper6_l_w);
DECLARE_WRITE8_MEMBER(mapper6_w);
@ -522,15 +523,23 @@ public:
DECLARE_WRITE8_MEMBER(dummy_w);
DECLARE_READ8_MEMBER(dummy_l_r);
DECLARE_READ8_MEMBER(dummy_m_r);
DECLARE_READ8_MEMBER(dummy_r);
DECLARE_READ8_MEMBER(dummy_r);
/* misc region to be allocated at init */
// variables which don't change at run-time
UINT8 *m_rom;
UINT8 *m_prg;
UINT8 *m_vrom;
UINT8 *m_vram;
UINT8 *m_ciram; //PPU nametable RAM - external to PPU!
UINT8 *m_wram;
UINT8 *m_battery_ram;
UINT8 *m_mapper_ram;
UINT8 *m_mapper_bram;
UINT32 m_mapper_ram_size;
UINT32 m_mapper_bram_size;
/* load-time cart variables which remain constant */
UINT16 m_prg_chunks; // iNES 2.0 allows for more chunks (a recently dumped multigame cart has 256 chunks of both PRG & CHR!)
UINT16 m_chr_chunks;
@ -540,7 +549,7 @@ public:
UINT32 m_battery_size;
UINT8 m_prg_ram; // if there is PRG RAM with no backup
UINT32 m_wram_size;
/* system variables which don't change at run-time */
UINT16 m_mapper; // for iNES
UINT16 m_pcb_id; // for UNIF & xml
@ -556,7 +565,49 @@ public:
cpu_device *m_maincpu;
ppu2c0x_device *m_ppu;
device_t *m_sound;
emu_timer *m_irq_timer;
emu_timer *m_irq_timer;
//private:
// banking helpers
// WRAM bankswitch
void wram_bank(int bank, int source);
// PRG bankswitch
void prg32(int bank);
void prg16_89ab(int bank);
void prg16_cdef(int bank);
void prg8_89(int bank);
void prg8_ab(int bank);
void prg8_cd(int bank);
void prg8_ef(int bank);
void prg8_67(int bank); // a bunch of pcbs can bank ROM in WRAM area!
void prg8_x(int start, int bank);
// CHR 8k bankswitch
void chr8(int bank, int source);
// CHR 4k bankswitch
void chr4_x(int start, int bank, int source);
void chr4_0(int bank, int source){ chr4_x(0, bank, source); };
void chr4_4(int bank, int source){ chr4_x(4, bank, source); };
// CHR 2k bankswitch
void chr2_x(int start, int bank, int source);
void chr2_0(int bank, int source) { chr2_x(0, bank, source); };
void chr2_2(int bank, int source) { chr2_x(2, bank, source); };
void chr2_4(int bank, int source) { chr2_x(4, bank, source); };
void chr2_6(int bank, int source) { chr2_x(6, bank, source); };
// CHR 1k bankswitch
void chr1_x(int start, int bank, int source);
void chr1_0(int bank, int source) { chr1_x(0, bank, source); };
void chr1_1(int bank, int source) { chr1_x(1, bank, source); };
void chr1_2(int bank, int source) { chr1_x(2, bank, source); };
void chr1_3(int bank, int source) { chr1_x(3, bank, source); };
void chr1_4(int bank, int source) { chr1_x(4, bank, source); };
void chr1_5(int bank, int source) { chr1_x(5, bank, source); };
void chr1_6(int bank, int source) { chr1_x(6, bank, source); };
void chr1_7(int bank, int source) { chr1_x(7, bank, source); };
// NT bankswitch
void set_nt_page(int page, int source, int bank, int writable);
void set_nt_mirroring(int mirroring);
};

8
src/mess/machine/nes.c
View File

@ -140,7 +140,7 @@ void nes_state::init_nes_core()
}
if (m_four_screen_vram)
set_nt_mirroring(machine(), PPU_MIRROR_4SCREEN);
set_nt_mirroring(PPU_MIRROR_4SCREEN);
else
{
switch (m_hard_mirroring)
@ -149,10 +149,10 @@ void nes_state::init_nes_core()
case PPU_MIRROR_VERT:
case PPU_MIRROR_HIGH:
case PPU_MIRROR_LOW:
set_nt_mirroring(machine(), m_hard_mirroring);
set_nt_mirroring(m_hard_mirroring);
break;
default:
set_nt_mirroring(machine(), PPU_MIRROR_NONE);
set_nt_mirroring(PPU_MIRROR_NONE);
break;
}
}
@ -1633,7 +1633,7 @@ WRITE8_MEMBER(nes_state::nes_fds_w)
m_fds_head_position = 0;
m_fds_read_mode = BIT(data, 2);
set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
if ((!(data & 0x40)) && (m_fds_write_reg & 0x40))
m_fds_head_position -= 2; // ???

30
src/mess/machine/nes_ines.c
View File

@ -53,10 +53,10 @@ WRITE8_MEMBER(nes_carts_state::mapper6_l_w)
{
case 0x1fe:
m_mmc_latch1 = data & 0x80;
set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
break;
case 0x1ff:
set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
break;
case 0x401:
@ -78,14 +78,14 @@ WRITE8_MEMBER(nes_carts_state::mapper6_w)
if (!m_mmc_latch1) // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
{
prg16_89ab(machine(), data >> 2);
// chr8(machine(), data & 0x03, ???);
prg16_89ab(data >> 2);
// chr8(data & 0x03, ???);
// due to lack of info on the exact behavior, we simply act as if mmc_latch1=1
if (m_mmc_chr_source == CHRROM)
chr8(machine(), data & 0x03, CHRROM);
chr8(data & 0x03, CHRROM);
}
else if (m_mmc_chr_source == CHRROM) // otherwise, we can use CHRROM (when present)
chr8(machine(), data, CHRROM);
chr8(data, CHRROM);
}
/*************************************************************
@ -103,8 +103,8 @@ WRITE8_MEMBER(nes_carts_state::mapper8_w)
{
LOG_MMC(("mapper8_w, offset: %04x, data: %02x\n", offset, data));
chr8(machine(), data & 0x07, CHRROM);
prg16_89ab(machine(), data >> 3);
chr8(data & 0x07, CHRROM);
prg16_89ab(data >> 3);
}
/*************************************************************
@ -126,10 +126,10 @@ WRITE8_MEMBER(nes_carts_state::mapper17_l_w)
switch (offset)
{
case 0x1fe:
set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
break;
case 0x1ff:
set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
break;
case 0x401:
@ -144,16 +144,16 @@ WRITE8_MEMBER(nes_carts_state::mapper17_l_w)
break;
case 0x404:
prg8_89(machine(), data);
prg8_89(data);
break;
case 0x405:
prg8_ab(machine(), data);
prg8_ab(data);
break;
case 0x406:
prg8_cd(machine(), data);
prg8_cd(data);
break;
case 0x407:
prg8_ef(machine(), data);
prg8_ef(data);
break;
case 0x410:
@ -164,7 +164,7 @@ WRITE8_MEMBER(nes_carts_state::mapper17_l_w)
case 0x415:
case 0x416:
case 0x417:
chr1_x(machine(), offset & 7, data, CHRROM);
chr1_x(offset & 7, data, CHRROM);
break;
}
}

352
src/mess/machine/nes_mmc.c
View File

@ -235,22 +235,20 @@ READ8_MEMBER(nes_state::nes_low_mapper_r)
*************************************************************/
static void wram_bank( running_machine &machine, int bank, int source )
void nes_carts_state::wram_bank(int bank, int source)
{
nes_state *state = machine.driver_data<nes_state>();
assert(state->m_battery || state->m_prg_ram);
assert(m_battery || m_prg_ram);
if (source == NES_BATTERY)
{
bank &= (state->m_battery_size / 0x2000) - 1;
state->m_prg_bank[4] = state->m_battery_bank5_start + bank;
bank &= (m_battery_size / 0x2000) - 1;
m_prg_bank[4] = m_battery_bank5_start + bank;
}
else
{
bank &= (state->m_wram_size / 0x2000) - 1;
state->m_prg_bank[4] = state->m_prgram_bank5_start + bank;
bank &= (m_wram_size / 0x2000) - 1;
m_prg_bank[4] = m_prgram_bank5_start + bank;
}
state->membank("bank5")->set_entry(state->m_prg_bank[4]);
membank("bank5")->set_entry(m_prg_bank[4]);
}
INLINE void prg_bank_refresh( running_machine &machine )
@ -264,118 +262,100 @@ INLINE void prg_bank_refresh( running_machine &machine )
/* PRG ROM in 8K, 16K or 32K blocks */
static void prg32( running_machine &machine, int bank )
void nes_carts_state::prg32(int bank)
{
nes_state *state = machine.driver_data<nes_state>();
/* if there is only 16k PRG, return */
if (!(state->m_prg_chunks >> 1))
if (!(m_prg_chunks >> 1))
return;
/* assumes that bank references a 32k chunk */
bank &= ((state->m_prg_chunks >> 1) - 1);
bank &= ((m_prg_chunks >> 1) - 1);
state->m_prg_bank[0] = bank * 4 + 0;
state->m_prg_bank[1] = bank * 4 + 1;
state->m_prg_bank[2] = bank * 4 + 2;
state->m_prg_bank[3] = bank * 4 + 3;
prg_bank_refresh(machine);
m_prg_bank[0] = bank * 4 + 0;
m_prg_bank[1] = bank * 4 + 1;
m_prg_bank[2] = bank * 4 + 2;
m_prg_bank[3] = bank * 4 + 3;
prg_bank_refresh(machine());
}
static void prg16_89ab( running_machine &machine, int bank )
void nes_carts_state::prg16_89ab(int bank)
{
nes_state *state = machine.driver_data<nes_state>();
/* assumes that bank references a 16k chunk */
bank &= (state->m_prg_chunks - 1);
bank &= (m_prg_chunks - 1);
state->m_prg_bank[0] = bank * 2 + 0;
state->m_prg_bank[1] = bank * 2 + 1;
prg_bank_refresh(machine);
m_prg_bank[0] = bank * 2 + 0;
m_prg_bank[1] = bank * 2 + 1;
prg_bank_refresh(machine());
}
static void prg16_cdef( running_machine &machine, int bank )
void nes_carts_state::prg16_cdef(int bank)
{
nes_state *state = machine.driver_data<nes_state>();
/* assumes that bank references a 16k chunk */
bank &= (state->m_prg_chunks - 1);
bank &= (m_prg_chunks - 1);
state->m_prg_bank[2] = bank * 2 + 0;
state->m_prg_bank[3] = bank * 2 + 1;
prg_bank_refresh(machine);
m_prg_bank[2] = bank * 2 + 0;
m_prg_bank[3] = bank * 2 + 1;
prg_bank_refresh(machine());
}
static void prg8_89( running_machine &machine, int bank )
void nes_carts_state::prg8_89(int bank)
{
nes_state *state = machine.driver_data<nes_state>();
/* assumes that bank references an 8k chunk */
bank &= ((state->m_prg_chunks << 1) - 1);
bank &= ((m_prg_chunks << 1) - 1);
state->m_prg_bank[0] = bank;
prg_bank_refresh(machine);
m_prg_bank[0] = bank;
prg_bank_refresh(machine());
}
static void prg8_ab( running_machine &machine, int bank )
void nes_carts_state::prg8_ab(int bank)
{
nes_state *state = machine.driver_data<nes_state>();
/* assumes that bank references an 8k chunk */
bank &= ((state->m_prg_chunks << 1) - 1);
bank &= ((m_prg_chunks << 1) - 1);
state->m_prg_bank[1] = bank;
prg_bank_refresh(machine);
m_prg_bank[1] = bank;
prg_bank_refresh(machine());
}
static void prg8_cd( running_machine &machine, int bank )
void nes_carts_state::prg8_cd(int bank)
{
nes_state *state = machine.driver_data<nes_state>();
/* assumes that bank references an 8k chunk */
bank &= ((state->m_prg_chunks << 1) - 1);
bank &= ((m_prg_chunks << 1) - 1);
state->m_prg_bank[2] = bank;
prg_bank_refresh(machine);
m_prg_bank[2] = bank;
prg_bank_refresh(machine());
}
static void prg8_ef( running_machine &machine, int bank )
void nes_carts_state::prg8_ef(int bank)
{
nes_state *state = machine.driver_data<nes_state>();
/* assumes that bank references an 8k chunk */
bank &= ((state->m_prg_chunks << 1) - 1);
bank &= ((m_prg_chunks << 1) - 1);
state->m_prg_bank[3] = bank;
prg_bank_refresh(machine);
m_prg_bank[3] = bank;
prg_bank_refresh(machine());
}
/* We define an additional helper to map PRG-ROM to 0x6000-0x7000 */
// TODO: are we implementing this correctly in the mappers which uses it? check!
static void prg8_67( running_machine &machine, int bank )
void nes_carts_state::prg8_67(int bank)
{
nes_state *state = machine.driver_data<nes_state>();
/* assumes that bank references an 8k chunk */
bank &= ((state->m_prg_chunks << 1) - 1);
bank &= ((m_prg_chunks << 1) - 1);
state->m_prg_bank[4] = bank;
state->membank("bank5")->set_entry(state->m_prg_bank[4]);
m_prg_bank[4] = bank;
membank("bank5")->set_entry(m_prg_bank[4]);
}
/* We also define an additional helper to map 8k PRG-ROM to one of the banks (passed as parameter) */
static void prg8_x( running_machine &machine, int start, int bank )
void nes_carts_state::prg8_x(int start, int bank)
{
nes_state *state = machine.driver_data<nes_state>();
assert(start < 4);
/* assumes that bank references an 8k chunk */
bank &= ((state->m_prg_chunks << 1) - 1);
bank &= ((m_prg_chunks << 1) - 1);
state->m_prg_bank[start] = bank;
prg_bank_refresh(machine);
m_prg_bank[start] = bank;
prg_bank_refresh(machine());
}
/* CHR ROM in 1K, 2K, 4K or 8K blocks */
@ -392,256 +372,174 @@ INLINE void chr_sanity_check( running_machine &machine, int source )
fatalerror("CHRROM bankswitch with no VROM\n");
}
static void chr8( running_machine &machine, int bank, int source )
void nes_carts_state::chr8(int bank, int source)
{
nes_state *state = machine.driver_data<nes_state>();
int i;
chr_sanity_check(machine, source);
chr_sanity_check(machine(), source);
if (source == CHRRAM)
{
bank &= (state->m_vram_chunks - 1);
for (i = 0; i < 8; i++)
bank &= (m_vram_chunks - 1);
for (int i = 0; i < 8; i++)
{
state->m_chr_map[i].source = source;
state->m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
state->m_chr_map[i].access = &state->m_vram[state->m_chr_map[i].origin];
m_chr_map[i].source = source;
m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
m_chr_map[i].access = &m_vram[m_chr_map[i].origin];
}
}
else
{
bank &= (state->m_chr_chunks - 1);
for (i = 0; i < 8; i++)
bank &= (m_chr_chunks - 1);
for (int i = 0; i < 8; i++)
{
state->m_chr_map[i].source = source;
state->m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
state->m_chr_map[i].access = &state->m_vrom[state->m_chr_map[i].origin];
m_chr_map[i].source = source;
m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
m_chr_map[i].access = &m_vrom[m_chr_map[i].origin];
}
}
}
static void chr4_x( running_machine &machine, int start, int bank, int source )
void nes_carts_state::chr4_x(int start, int bank, int source)
{
nes_state *state = machine.driver_data<nes_state>();
int i;
chr_sanity_check(machine, source);
chr_sanity_check(machine(), source);
if (source == CHRRAM)
{
bank &= ((state->m_vram_chunks << 1) - 1);
for (i = 0; i < 4; i++)
bank &= ((m_vram_chunks << 1) - 1);
for (int i = 0; i < 4; i++)
{
state->m_chr_map[i + start].source = source;
state->m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
state->m_chr_map[i + start].access = &state->m_vram[state->m_chr_map[i + start].origin];
m_chr_map[i + start].source = source;
m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
m_chr_map[i + start].access = &m_vram[m_chr_map[i + start].origin];
}
}
else
{
bank &= ((state->m_chr_chunks << 1) - 1);
for (i = 0; i < 4; i++)
bank &= ((m_chr_chunks << 1) - 1);
for (int i = 0; i < 4; i++)
{
state->m_chr_map[i + start].source = source;
state->m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
state->m_chr_map[i + start].access = &state->m_vrom[state->m_chr_map[i + start].origin];
m_chr_map[i + start].source = source;
m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
m_chr_map[i + start].access = &m_vrom[m_chr_map[i + start].origin];
}
}
}
static void chr4_0( running_machine &machine, int bank, int source )
void nes_carts_state::chr2_x(int start, int bank, int source)
{
chr4_x(machine, 0, bank, source);
}
static void chr4_4( running_machine &machine, int bank, int source )
{
chr4_x(machine, 4, bank, source);
}
static void chr2_x( running_machine &machine, int start, int bank, int source )
{
nes_state *state = machine.driver_data<nes_state>();
int i;
chr_sanity_check(machine, source);
chr_sanity_check(machine(), source);
if (source == CHRRAM)
{
bank &= ((state->m_vram_chunks << 2) - 1);
for (i = 0; i < 2; i++)
bank &= ((m_vram_chunks << 2) - 1);
for (int i = 0; i < 2; i++)
{
state->m_chr_map[i + start].source = source;
state->m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
state->m_chr_map[i + start].access = &state->m_vram[state->m_chr_map[i + start].origin];
m_chr_map[i + start].source = source;
m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
m_chr_map[i + start].access = &m_vram[m_chr_map[i + start].origin];
}
}
else
{
bank &= ((state->m_chr_chunks << 2) - 1);
for (i = 0; i < 2; i++)
bank &= ((m_chr_chunks << 2) - 1);
for (int i = 0; i < 2; i++)
{
state->m_chr_map[i + start].source = source;
state->m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
state->m_chr_map[i + start].access = &state->m_vrom[state->m_chr_map[i + start].origin];
m_chr_map[i + start].source = source;
m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
m_chr_map[i + start].access = &m_vrom[m_chr_map[i + start].origin];
}
}
}
static void chr2_0( running_machine &machine, int bank, int source )
void nes_carts_state::chr1_x(int start, int bank, int source)
{
chr2_x(machine, 0, bank, source);
}
static void chr2_2( running_machine &machine, int bank, int source )
{
chr2_x(machine, 2, bank, source);
}
static void chr2_4( running_machine &machine, int bank, int source )
{
chr2_x(machine, 4, bank, source);
}
static void chr2_6( running_machine &machine, int bank, int source )
{
chr2_x(machine, 6, bank, source);
}
static void chr1_x( running_machine &machine, int start, int bank, int source )
{
nes_state *state = machine.driver_data<nes_state>();
chr_sanity_check(machine, source);
chr_sanity_check(machine(), source);
if (source == CHRRAM)
{
bank &= ((state->m_vram_chunks << 3) - 1);
state->m_chr_map[start].source = source;
state->m_chr_map[start].origin = (bank * 0x400); // for save state uses!
state->m_chr_map[start].access = &state->m_vram[state->m_chr_map[start].origin];
bank &= ((m_vram_chunks << 3) - 1);
m_chr_map[start].source = source;
m_chr_map[start].origin = (bank * 0x400); // for save state uses!
m_chr_map[start].access = &m_vram[m_chr_map[start].origin];
}
else
{
bank &= ((state->m_chr_chunks << 3) - 1);
state->m_chr_map[start].source = source;
state->m_chr_map[start].origin = (bank * 0x400); // for save state uses!
state->m_chr_map[start].access = &state->m_vrom[state->m_chr_map[start].origin];
bank &= ((m_chr_chunks << 3) - 1);
m_chr_map[start].source = source;
m_chr_map[start].origin = (bank * 0x400); // for save state uses!
m_chr_map[start].access = &m_vrom[m_chr_map[start].origin];
}
}
static void chr1_0 (running_machine &machine, int bank, int source)
{
chr1_x(machine, 0, bank, source);
}
static void chr1_1( running_machine &machine, int bank, int source )
{
chr1_x(machine, 1, bank, source);
}
static void chr1_2( running_machine &machine, int bank, int source )
{
chr1_x(machine, 2, bank, source);
}
static void chr1_3( running_machine &machine, int bank, int source )
{
chr1_x(machine, 3, bank, source);
}
static void chr1_4( running_machine &machine, int bank, int source )
{
chr1_x(machine, 4, bank, source);
}
static void chr1_5( running_machine &machine, int bank, int source )
{
chr1_x(machine, 5, bank, source);
}
static void chr1_6( running_machine &machine, int bank, int source )
{
chr1_x(machine, 6, bank, source);
}
static void chr1_7( running_machine &machine, int bank, int source )
{
chr1_x(machine, 7, bank, source);
}
/* NameTable paging and mirroring */
static void set_nt_page( running_machine &machine, int page, int source, int bank, int writable )
void nes_carts_state::set_nt_page(int page, int source, int bank, int writable)
{
nes_state *state = machine.driver_data<nes_state>();
UINT8* base_ptr;
switch (source)
{
case CART_NTRAM:
base_ptr = state->m_extended_ntram;
base_ptr = m_extended_ntram;
break;
case MMC5FILL:
base_ptr = NULL;
break;
case ROM:
base_ptr = state->m_vrom;
base_ptr = m_vrom;
break;
case EXRAM:
base_ptr = state->m_mapper_ram;
base_ptr = m_mapper_ram;
break;
case CIRAM:
default:
base_ptr = state->m_ciram;
base_ptr = m_ciram;
break;
}
page &= 3; /* mask down to the 4 logical pages */
state->m_nt_page[page].source = source;
m_nt_page[page].source = source;
if (base_ptr != NULL)
{
state->m_nt_page[page].origin = bank * 0x400;
state->m_nt_page[page].access = base_ptr + state->m_nt_page[page].origin;
m_nt_page[page].origin = bank * 0x400;
m_nt_page[page].access = base_ptr + m_nt_page[page].origin;
}
state->m_nt_page[page].writable = writable;
m_nt_page[page].writable = writable;
}
void set_nt_mirroring( running_machine &machine, int mirroring )
void nes_carts_state::set_nt_mirroring(int mirroring)
{
/* setup our videomem handlers based on mirroring */
switch (mirroring)
{
case PPU_MIRROR_VERT:
set_nt_page(machine, 0, CIRAM, 0, 1);
set_nt_page(machine, 1, CIRAM, 1, 1);
set_nt_page(machine, 2, CIRAM, 0, 1);
set_nt_page(machine, 3, CIRAM, 1, 1);
set_nt_page(0, CIRAM, 0, 1);
set_nt_page(1, CIRAM, 1, 1);
set_nt_page(2, CIRAM, 0, 1);
set_nt_page(3, CIRAM, 1, 1);
break;
case PPU_MIRROR_HORZ:
set_nt_page(machine, 0, CIRAM, 0, 1);
set_nt_page(machine, 1, CIRAM, 0, 1);
set_nt_page(machine, 2, CIRAM, 1, 1);
set_nt_page(machine, 3, CIRAM, 1, 1);
set_nt_page(0, CIRAM, 0, 1);
set_nt_page(1, CIRAM, 0, 1);
set_nt_page(2, CIRAM, 1, 1);
set_nt_page(3, CIRAM, 1, 1);
break;
case PPU_MIRROR_HIGH:
set_nt_page(machine, 0, CIRAM, 1, 1);
set_nt_page(machine, 1, CIRAM, 1, 1);
set_nt_page(machine, 2, CIRAM, 1, 1);
set_nt_page(machine, 3, CIRAM, 1, 1);
set_nt_page(0, CIRAM, 1, 1);
set_nt_page(1, CIRAM, 1, 1);
set_nt_page(2, CIRAM, 1, 1);
set_nt_page(3, CIRAM, 1, 1);
break;
case PPU_MIRROR_LOW:
set_nt_page(machine, 0, CIRAM, 0, 1);
set_nt_page(machine, 1, CIRAM, 0, 1);
set_nt_page(machine, 2, CIRAM, 0, 1);
set_nt_page(machine, 3, CIRAM, 0, 1);
set_nt_page(0, CIRAM, 0, 1);
set_nt_page(1, CIRAM, 0, 1);
set_nt_page(2, CIRAM, 0, 1);
set_nt_page(3, CIRAM, 0, 1);
break;
case PPU_MIRROR_NONE:
@ -653,10 +551,10 @@ void set_nt_mirroring( running_machine &machine, int mirroring )
logerror("Mapper set 4-screen mirroring without supplying external nametable memory!\n");
set_nt_page(machine, 0, CIRAM, 0, 1);
set_nt_page(machine, 1, CIRAM, 0, 1);
set_nt_page(machine, 2, CIRAM, 1, 1);
set_nt_page(machine, 3, CIRAM, 1, 1);
set_nt_page(0, CIRAM, 0, 1);
set_nt_page(1, CIRAM, 0, 1);
set_nt_page(2, CIRAM, 1, 1);
set_nt_page(3, CIRAM, 1, 1);
break;
}
}

2227
src/mess/machine/nes_pcb.c
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