(MESS) nes.c: moved bankswitch functions into nes_carts_state. no whatsnew.
among other things, this allowed to remove around a thousand of machine() parameters passed to re-get the state class at each bankswitch operation. readability says thanks.
This commit is contained in:
Fabio Priuli
parent
7ad98c13be
commit
326c860ac7
@ -90,14 +90,6 @@ public:
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device_t *m_cart;
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// emu_timer *m_irq_timer;
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/* misc region to be allocated at init */
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// variables which don't change at run-time
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UINT8 *m_rom;
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UINT8 *m_prg;
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UINT8 *m_vrom;
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UINT8 *m_vram;
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UINT8 *m_ciram; //PPU nametable RAM - external to PPU!
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/***** FDS-floppy related *****/
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int m_disk_expansion;
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@ -160,6 +160,7 @@ public:
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nes_prg_callback m_mmc3_prg_cb; // these are used to simplify a lot emulation of some MMC3 pirate clones
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nes_chr_callback m_mmc3_chr_cb;
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// mapper variables (to be sorted out at some point, to split more complex mappers as separate devices)
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int m_chr_open_bus;
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int m_prgram_bank5_start, m_battery_bank5_start, m_empty_bank5_start;
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@ -524,6 +525,14 @@ public:
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DECLARE_READ8_MEMBER(dummy_m_r);
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DECLARE_READ8_MEMBER(dummy_r);
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/* misc region to be allocated at init */
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// variables which don't change at run-time
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UINT8 *m_rom;
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UINT8 *m_prg;
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UINT8 *m_vrom;
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UINT8 *m_vram;
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UINT8 *m_ciram; //PPU nametable RAM - external to PPU!
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UINT8 *m_wram;
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UINT8 *m_battery_ram;
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UINT8 *m_mapper_ram;
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@ -557,6 +566,48 @@ public:
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ppu2c0x_device *m_ppu;
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device_t *m_sound;
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emu_timer *m_irq_timer;
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//private:
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// banking helpers
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// WRAM bankswitch
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void wram_bank(int bank, int source);
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// PRG bankswitch
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void prg32(int bank);
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void prg16_89ab(int bank);
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void prg16_cdef(int bank);
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void prg8_89(int bank);
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void prg8_ab(int bank);
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void prg8_cd(int bank);
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void prg8_ef(int bank);
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void prg8_67(int bank); // a bunch of pcbs can bank ROM in WRAM area!
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void prg8_x(int start, int bank);
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// CHR 8k bankswitch
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void chr8(int bank, int source);
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// CHR 4k bankswitch
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void chr4_x(int start, int bank, int source);
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void chr4_0(int bank, int source){ chr4_x(0, bank, source); };
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void chr4_4(int bank, int source){ chr4_x(4, bank, source); };
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// CHR 2k bankswitch
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void chr2_x(int start, int bank, int source);
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void chr2_0(int bank, int source) { chr2_x(0, bank, source); };
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void chr2_2(int bank, int source) { chr2_x(2, bank, source); };
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void chr2_4(int bank, int source) { chr2_x(4, bank, source); };
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void chr2_6(int bank, int source) { chr2_x(6, bank, source); };
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// CHR 1k bankswitch
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void chr1_x(int start, int bank, int source);
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void chr1_0(int bank, int source) { chr1_x(0, bank, source); };
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void chr1_1(int bank, int source) { chr1_x(1, bank, source); };
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void chr1_2(int bank, int source) { chr1_x(2, bank, source); };
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void chr1_3(int bank, int source) { chr1_x(3, bank, source); };
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void chr1_4(int bank, int source) { chr1_x(4, bank, source); };
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void chr1_5(int bank, int source) { chr1_x(5, bank, source); };
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void chr1_6(int bank, int source) { chr1_x(6, bank, source); };
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void chr1_7(int bank, int source) { chr1_x(7, bank, source); };
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// NT bankswitch
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void set_nt_page(int page, int source, int bank, int writable);
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void set_nt_mirroring(int mirroring);
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};
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@ -140,7 +140,7 @@ void nes_state::init_nes_core()
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}
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if (m_four_screen_vram)
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set_nt_mirroring(machine(), PPU_MIRROR_4SCREEN);
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set_nt_mirroring(PPU_MIRROR_4SCREEN);
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else
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{
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switch (m_hard_mirroring)
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@ -149,10 +149,10 @@ void nes_state::init_nes_core()
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case PPU_MIRROR_VERT:
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case PPU_MIRROR_HIGH:
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case PPU_MIRROR_LOW:
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set_nt_mirroring(machine(), m_hard_mirroring);
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set_nt_mirroring(m_hard_mirroring);
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break;
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default:
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set_nt_mirroring(machine(), PPU_MIRROR_NONE);
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set_nt_mirroring(PPU_MIRROR_NONE);
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break;
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}
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}
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@ -1633,7 +1633,7 @@ WRITE8_MEMBER(nes_state::nes_fds_w)
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m_fds_head_position = 0;
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m_fds_read_mode = BIT(data, 2);
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set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
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set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
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if ((!(data & 0x40)) && (m_fds_write_reg & 0x40))
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m_fds_head_position -= 2; // ???
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@ -53,10 +53,10 @@ WRITE8_MEMBER(nes_carts_state::mapper6_l_w)
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{
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case 0x1fe:
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m_mmc_latch1 = data & 0x80;
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set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
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set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
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break;
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case 0x1ff:
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set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
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set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
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break;
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case 0x401:
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@ -78,14 +78,14 @@ WRITE8_MEMBER(nes_carts_state::mapper6_w)
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if (!m_mmc_latch1) // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
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{
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prg16_89ab(machine(), data >> 2);
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// chr8(machine(), data & 0x03, ???);
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prg16_89ab(data >> 2);
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// chr8(data & 0x03, ???);
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// due to lack of info on the exact behavior, we simply act as if mmc_latch1=1
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if (m_mmc_chr_source == CHRROM)
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chr8(machine(), data & 0x03, CHRROM);
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chr8(data & 0x03, CHRROM);
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}
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else if (m_mmc_chr_source == CHRROM) // otherwise, we can use CHRROM (when present)
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chr8(machine(), data, CHRROM);
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chr8(data, CHRROM);
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}
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/*************************************************************
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@ -103,8 +103,8 @@ WRITE8_MEMBER(nes_carts_state::mapper8_w)
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{
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LOG_MMC(("mapper8_w, offset: %04x, data: %02x\n", offset, data));
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chr8(machine(), data & 0x07, CHRROM);
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prg16_89ab(machine(), data >> 3);
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chr8(data & 0x07, CHRROM);
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prg16_89ab(data >> 3);
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}
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/*************************************************************
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@ -126,10 +126,10 @@ WRITE8_MEMBER(nes_carts_state::mapper17_l_w)
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switch (offset)
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{
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case 0x1fe:
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set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
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set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
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break;
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case 0x1ff:
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set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
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set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
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break;
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case 0x401:
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@ -144,16 +144,16 @@ WRITE8_MEMBER(nes_carts_state::mapper17_l_w)
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break;
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case 0x404:
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prg8_89(machine(), data);
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prg8_89(data);
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break;
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case 0x405:
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prg8_ab(machine(), data);
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prg8_ab(data);
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break;
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case 0x406:
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prg8_cd(machine(), data);
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prg8_cd(data);
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break;
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case 0x407:
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prg8_ef(machine(), data);
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prg8_ef(data);
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break;
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case 0x410:
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@ -164,7 +164,7 @@ WRITE8_MEMBER(nes_carts_state::mapper17_l_w)
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case 0x415:
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case 0x416:
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case 0x417:
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chr1_x(machine(), offset & 7, data, CHRROM);
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chr1_x(offset & 7, data, CHRROM);
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break;
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}
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}
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@ -235,22 +235,20 @@ READ8_MEMBER(nes_state::nes_low_mapper_r)
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*************************************************************/
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static void wram_bank( running_machine &machine, int bank, int source )
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void nes_carts_state::wram_bank(int bank, int source)
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{
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nes_state *state = machine.driver_data<nes_state>();
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assert(state->m_battery || state->m_prg_ram);
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assert(m_battery || m_prg_ram);
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if (source == NES_BATTERY)
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{
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bank &= (state->m_battery_size / 0x2000) - 1;
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state->m_prg_bank[4] = state->m_battery_bank5_start + bank;
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bank &= (m_battery_size / 0x2000) - 1;
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m_prg_bank[4] = m_battery_bank5_start + bank;
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}
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else
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{
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bank &= (state->m_wram_size / 0x2000) - 1;
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state->m_prg_bank[4] = state->m_prgram_bank5_start + bank;
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bank &= (m_wram_size / 0x2000) - 1;
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m_prg_bank[4] = m_prgram_bank5_start + bank;
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}
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state->membank("bank5")->set_entry(state->m_prg_bank[4]);
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membank("bank5")->set_entry(m_prg_bank[4]);
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}
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INLINE void prg_bank_refresh( running_machine &machine )
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@ -264,118 +262,100 @@ INLINE void prg_bank_refresh( running_machine &machine )
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/* PRG ROM in 8K, 16K or 32K blocks */
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static void prg32( running_machine &machine, int bank )
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void nes_carts_state::prg32(int bank)
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{
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nes_state *state = machine.driver_data<nes_state>();
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/* if there is only 16k PRG, return */
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if (!(state->m_prg_chunks >> 1))
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if (!(m_prg_chunks >> 1))
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return;
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/* assumes that bank references a 32k chunk */
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bank &= ((state->m_prg_chunks >> 1) - 1);
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bank &= ((m_prg_chunks >> 1) - 1);
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state->m_prg_bank[0] = bank * 4 + 0;
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state->m_prg_bank[1] = bank * 4 + 1;
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state->m_prg_bank[2] = bank * 4 + 2;
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state->m_prg_bank[3] = bank * 4 + 3;
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prg_bank_refresh(machine);
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m_prg_bank[0] = bank * 4 + 0;
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m_prg_bank[1] = bank * 4 + 1;
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m_prg_bank[2] = bank * 4 + 2;
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m_prg_bank[3] = bank * 4 + 3;
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prg_bank_refresh(machine());
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}
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static void prg16_89ab( running_machine &machine, int bank )
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void nes_carts_state::prg16_89ab(int bank)
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{
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nes_state *state = machine.driver_data<nes_state>();
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/* assumes that bank references a 16k chunk */
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bank &= (state->m_prg_chunks - 1);
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bank &= (m_prg_chunks - 1);
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state->m_prg_bank[0] = bank * 2 + 0;
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state->m_prg_bank[1] = bank * 2 + 1;
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prg_bank_refresh(machine);
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m_prg_bank[0] = bank * 2 + 0;
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m_prg_bank[1] = bank * 2 + 1;
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prg_bank_refresh(machine());
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}
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static void prg16_cdef( running_machine &machine, int bank )
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void nes_carts_state::prg16_cdef(int bank)
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{
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nes_state *state = machine.driver_data<nes_state>();
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/* assumes that bank references a 16k chunk */
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bank &= (state->m_prg_chunks - 1);
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bank &= (m_prg_chunks - 1);
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state->m_prg_bank[2] = bank * 2 + 0;
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state->m_prg_bank[3] = bank * 2 + 1;
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prg_bank_refresh(machine);
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m_prg_bank[2] = bank * 2 + 0;
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m_prg_bank[3] = bank * 2 + 1;
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prg_bank_refresh(machine());
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}
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static void prg8_89( running_machine &machine, int bank )
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void nes_carts_state::prg8_89(int bank)
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{
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nes_state *state = machine.driver_data<nes_state>();
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/* assumes that bank references an 8k chunk */
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bank &= ((state->m_prg_chunks << 1) - 1);
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bank &= ((m_prg_chunks << 1) - 1);
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state->m_prg_bank[0] = bank;
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prg_bank_refresh(machine);
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m_prg_bank[0] = bank;
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prg_bank_refresh(machine());
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}
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static void prg8_ab( running_machine &machine, int bank )
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void nes_carts_state::prg8_ab(int bank)
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{
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nes_state *state = machine.driver_data<nes_state>();
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/* assumes that bank references an 8k chunk */
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bank &= ((state->m_prg_chunks << 1) - 1);
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bank &= ((m_prg_chunks << 1) - 1);
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state->m_prg_bank[1] = bank;
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prg_bank_refresh(machine);
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m_prg_bank[1] = bank;
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prg_bank_refresh(machine());
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}
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static void prg8_cd( running_machine &machine, int bank )
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void nes_carts_state::prg8_cd(int bank)
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{
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nes_state *state = machine.driver_data<nes_state>();
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/* assumes that bank references an 8k chunk */
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bank &= ((state->m_prg_chunks << 1) - 1);
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bank &= ((m_prg_chunks << 1) - 1);
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state->m_prg_bank[2] = bank;
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prg_bank_refresh(machine);
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m_prg_bank[2] = bank;
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prg_bank_refresh(machine());
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}
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static void prg8_ef( running_machine &machine, int bank )
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void nes_carts_state::prg8_ef(int bank)
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{
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nes_state *state = machine.driver_data<nes_state>();
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/* assumes that bank references an 8k chunk */
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bank &= ((state->m_prg_chunks << 1) - 1);
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bank &= ((m_prg_chunks << 1) - 1);
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state->m_prg_bank[3] = bank;
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prg_bank_refresh(machine);
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m_prg_bank[3] = bank;
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prg_bank_refresh(machine());
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}
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/* We define an additional helper to map PRG-ROM to 0x6000-0x7000 */
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// TODO: are we implementing this correctly in the mappers which uses it? check!
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static void prg8_67( running_machine &machine, int bank )
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void nes_carts_state::prg8_67(int bank)
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{
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nes_state *state = machine.driver_data<nes_state>();
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/* assumes that bank references an 8k chunk */
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bank &= ((state->m_prg_chunks << 1) - 1);
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bank &= ((m_prg_chunks << 1) - 1);
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state->m_prg_bank[4] = bank;
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state->membank("bank5")->set_entry(state->m_prg_bank[4]);
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m_prg_bank[4] = bank;
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membank("bank5")->set_entry(m_prg_bank[4]);
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}
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/* We also define an additional helper to map 8k PRG-ROM to one of the banks (passed as parameter) */
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static void prg8_x( running_machine &machine, int start, int bank )
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void nes_carts_state::prg8_x(int start, int bank)
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{
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nes_state *state = machine.driver_data<nes_state>();
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assert(start < 4);
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/* assumes that bank references an 8k chunk */
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bank &= ((state->m_prg_chunks << 1) - 1);
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bank &= ((m_prg_chunks << 1) - 1);
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state->m_prg_bank[start] = bank;
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prg_bank_refresh(machine);
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m_prg_bank[start] = bank;
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prg_bank_refresh(machine());
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}
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/* CHR ROM in 1K, 2K, 4K or 8K blocks */
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@ -392,256 +372,174 @@ INLINE void chr_sanity_check( running_machine &machine, int source )
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fatalerror("CHRROM bankswitch with no VROM\n");
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}
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static void chr8( running_machine &machine, int bank, int source )
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void nes_carts_state::chr8(int bank, int source)
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{
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nes_state *state = machine.driver_data<nes_state>();
|
||||
int i;
|
||||
|
||||
chr_sanity_check(machine, source);
|
||||
chr_sanity_check(machine(), source);
|
||||
|
||||
if (source == CHRRAM)
|
||||
{
|
||||
bank &= (state->m_vram_chunks - 1);
|
||||
for (i = 0; i < 8; i++)
|
||||
bank &= (m_vram_chunks - 1);
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
state->m_chr_map[i].source = source;
|
||||
state->m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
|
||||
state->m_chr_map[i].access = &state->m_vram[state->m_chr_map[i].origin];
|
||||
m_chr_map[i].source = source;
|
||||
m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
|
||||
m_chr_map[i].access = &m_vram[m_chr_map[i].origin];
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
bank &= (state->m_chr_chunks - 1);
|
||||
for (i = 0; i < 8; i++)
|
||||
bank &= (m_chr_chunks - 1);
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
state->m_chr_map[i].source = source;
|
||||
state->m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
|
||||
state->m_chr_map[i].access = &state->m_vrom[state->m_chr_map[i].origin];
|
||||
m_chr_map[i].source = source;
|
||||
m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
|
||||
m_chr_map[i].access = &m_vrom[m_chr_map[i].origin];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void chr4_x( running_machine &machine, int start, int bank, int source )
|
||||
void nes_carts_state::chr4_x(int start, int bank, int source)
|
||||
{
|
||||
nes_state *state = machine.driver_data<nes_state>();
|
||||
int i;
|
||||
|
||||
chr_sanity_check(machine, source);
|
||||
chr_sanity_check(machine(), source);
|
||||
|
||||
if (source == CHRRAM)
|
||||
{
|
||||
bank &= ((state->m_vram_chunks << 1) - 1);
|
||||
for (i = 0; i < 4; i++)
|
||||
bank &= ((m_vram_chunks << 1) - 1);
|
||||
for (int i = 0; i < 4; i++)
|
||||
{
|
||||
state->m_chr_map[i + start].source = source;
|
||||
state->m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
|
||||
state->m_chr_map[i + start].access = &state->m_vram[state->m_chr_map[i + start].origin];
|
||||
m_chr_map[i + start].source = source;
|
||||
m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
|
||||
m_chr_map[i + start].access = &m_vram[m_chr_map[i + start].origin];
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
bank &= ((state->m_chr_chunks << 1) - 1);
|
||||
for (i = 0; i < 4; i++)
|
||||
bank &= ((m_chr_chunks << 1) - 1);
|
||||
for (int i = 0; i < 4; i++)
|
||||
{
|
||||
state->m_chr_map[i + start].source = source;
|
||||
state->m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
|
||||
state->m_chr_map[i + start].access = &state->m_vrom[state->m_chr_map[i + start].origin];
|
||||
m_chr_map[i + start].source = source;
|
||||
m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
|
||||
m_chr_map[i + start].access = &m_vrom[m_chr_map[i + start].origin];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void chr4_0( running_machine &machine, int bank, int source )
|
||||
void nes_carts_state::chr2_x(int start, int bank, int source)
|
||||
{
|
||||
chr4_x(machine, 0, bank, source);
|
||||
}
|
||||
|
||||
static void chr4_4( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr4_x(machine, 4, bank, source);
|
||||
}
|
||||
|
||||
static void chr2_x( running_machine &machine, int start, int bank, int source )
|
||||
{
|
||||
nes_state *state = machine.driver_data<nes_state>();
|
||||
int i;
|
||||
|
||||
chr_sanity_check(machine, source);
|
||||
chr_sanity_check(machine(), source);
|
||||
|
||||
if (source == CHRRAM)
|
||||
{
|
||||
bank &= ((state->m_vram_chunks << 2) - 1);
|
||||
for (i = 0; i < 2; i++)
|
||||
bank &= ((m_vram_chunks << 2) - 1);
|
||||
for (int i = 0; i < 2; i++)
|
||||
{
|
||||
state->m_chr_map[i + start].source = source;
|
||||
state->m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
|
||||
state->m_chr_map[i + start].access = &state->m_vram[state->m_chr_map[i + start].origin];
|
||||
m_chr_map[i + start].source = source;
|
||||
m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
|
||||
m_chr_map[i + start].access = &m_vram[m_chr_map[i + start].origin];
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
bank &= ((state->m_chr_chunks << 2) - 1);
|
||||
for (i = 0; i < 2; i++)
|
||||
bank &= ((m_chr_chunks << 2) - 1);
|
||||
for (int i = 0; i < 2; i++)
|
||||
{
|
||||
state->m_chr_map[i + start].source = source;
|
||||
state->m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
|
||||
state->m_chr_map[i + start].access = &state->m_vrom[state->m_chr_map[i + start].origin];
|
||||
m_chr_map[i + start].source = source;
|
||||
m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
|
||||
m_chr_map[i + start].access = &m_vrom[m_chr_map[i + start].origin];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void chr2_0( running_machine &machine, int bank, int source )
|
||||
void nes_carts_state::chr1_x(int start, int bank, int source)
|
||||
{
|
||||
chr2_x(machine, 0, bank, source);
|
||||
}
|
||||
|
||||
static void chr2_2( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr2_x(machine, 2, bank, source);
|
||||
}
|
||||
|
||||
static void chr2_4( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr2_x(machine, 4, bank, source);
|
||||
}
|
||||
|
||||
static void chr2_6( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr2_x(machine, 6, bank, source);
|
||||
}
|
||||
|
||||
static void chr1_x( running_machine &machine, int start, int bank, int source )
|
||||
{
|
||||
nes_state *state = machine.driver_data<nes_state>();
|
||||
|
||||
chr_sanity_check(machine, source);
|
||||
chr_sanity_check(machine(), source);
|
||||
|
||||
if (source == CHRRAM)
|
||||
{
|
||||
bank &= ((state->m_vram_chunks << 3) - 1);
|
||||
state->m_chr_map[start].source = source;
|
||||
state->m_chr_map[start].origin = (bank * 0x400); // for save state uses!
|
||||
state->m_chr_map[start].access = &state->m_vram[state->m_chr_map[start].origin];
|
||||
bank &= ((m_vram_chunks << 3) - 1);
|
||||
m_chr_map[start].source = source;
|
||||
m_chr_map[start].origin = (bank * 0x400); // for save state uses!
|
||||
m_chr_map[start].access = &m_vram[m_chr_map[start].origin];
|
||||
}
|
||||
else
|
||||
{
|
||||
bank &= ((state->m_chr_chunks << 3) - 1);
|
||||
state->m_chr_map[start].source = source;
|
||||
state->m_chr_map[start].origin = (bank * 0x400); // for save state uses!
|
||||
state->m_chr_map[start].access = &state->m_vrom[state->m_chr_map[start].origin];
|
||||
bank &= ((m_chr_chunks << 3) - 1);
|
||||
m_chr_map[start].source = source;
|
||||
m_chr_map[start].origin = (bank * 0x400); // for save state uses!
|
||||
m_chr_map[start].access = &m_vrom[m_chr_map[start].origin];
|
||||
}
|
||||
}
|
||||
|
||||
static void chr1_0 (running_machine &machine, int bank, int source)
|
||||
{
|
||||
chr1_x(machine, 0, bank, source);
|
||||
}
|
||||
|
||||
static void chr1_1( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr1_x(machine, 1, bank, source);
|
||||
}
|
||||
|
||||
static void chr1_2( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr1_x(machine, 2, bank, source);
|
||||
}
|
||||
|
||||
static void chr1_3( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr1_x(machine, 3, bank, source);
|
||||
}
|
||||
|
||||
static void chr1_4( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr1_x(machine, 4, bank, source);
|
||||
}
|
||||
|
||||
static void chr1_5( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr1_x(machine, 5, bank, source);
|
||||
}
|
||||
|
||||
static void chr1_6( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr1_x(machine, 6, bank, source);
|
||||
}
|
||||
|
||||
static void chr1_7( running_machine &machine, int bank, int source )
|
||||
{
|
||||
chr1_x(machine, 7, bank, source);
|
||||
}
|
||||
|
||||
|
||||
/* NameTable paging and mirroring */
|
||||
|
||||
static void set_nt_page( running_machine &machine, int page, int source, int bank, int writable )
|
||||
void nes_carts_state::set_nt_page(int page, int source, int bank, int writable)
|
||||
{
|
||||
nes_state *state = machine.driver_data<nes_state>();
|
||||
UINT8* base_ptr;
|
||||
|
||||
switch (source)
|
||||
{
|
||||
case CART_NTRAM:
|
||||
base_ptr = state->m_extended_ntram;
|
||||
base_ptr = m_extended_ntram;
|
||||
break;
|
||||
case MMC5FILL:
|
||||
base_ptr = NULL;
|
||||
break;
|
||||
case ROM:
|
||||
base_ptr = state->m_vrom;
|
||||
base_ptr = m_vrom;
|
||||
break;
|
||||
case EXRAM:
|
||||
base_ptr = state->m_mapper_ram;
|
||||
base_ptr = m_mapper_ram;
|
||||
break;
|
||||
case CIRAM:
|
||||
default:
|
||||
base_ptr = state->m_ciram;
|
||||
base_ptr = m_ciram;
|
||||
break;
|
||||
}
|
||||
|
||||
page &= 3; /* mask down to the 4 logical pages */
|
||||
state->m_nt_page[page].source = source;
|
||||
m_nt_page[page].source = source;
|
||||
|
||||
if (base_ptr != NULL)
|
||||
{
|
||||
state->m_nt_page[page].origin = bank * 0x400;
|
||||
state->m_nt_page[page].access = base_ptr + state->m_nt_page[page].origin;
|
||||
m_nt_page[page].origin = bank * 0x400;
|
||||
m_nt_page[page].access = base_ptr + m_nt_page[page].origin;
|
||||
}
|
||||
|
||||
state->m_nt_page[page].writable = writable;
|
||||
m_nt_page[page].writable = writable;
|
||||
}
|
||||
|
||||
void set_nt_mirroring( running_machine &machine, int mirroring )
|
||||
void nes_carts_state::set_nt_mirroring(int mirroring)
|
||||
{
|
||||
/* setup our videomem handlers based on mirroring */
|
||||
switch (mirroring)
|
||||
{
|
||||
case PPU_MIRROR_VERT:
|
||||
set_nt_page(machine, 0, CIRAM, 0, 1);
|
||||
set_nt_page(machine, 1, CIRAM, 1, 1);
|
||||
set_nt_page(machine, 2, CIRAM, 0, 1);
|
||||
set_nt_page(machine, 3, CIRAM, 1, 1);
|
||||
set_nt_page(0, CIRAM, 0, 1);
|
||||
set_nt_page(1, CIRAM, 1, 1);
|
||||
set_nt_page(2, CIRAM, 0, 1);
|
||||
set_nt_page(3, CIRAM, 1, 1);
|
||||
break;
|
||||
|
||||
case PPU_MIRROR_HORZ:
|
||||
set_nt_page(machine, 0, CIRAM, 0, 1);
|
||||
set_nt_page(machine, 1, CIRAM, 0, 1);
|
||||
set_nt_page(machine, 2, CIRAM, 1, 1);
|
||||
set_nt_page(machine, 3, CIRAM, 1, 1);
|
||||
set_nt_page(0, CIRAM, 0, 1);
|
||||
set_nt_page(1, CIRAM, 0, 1);
|
||||
set_nt_page(2, CIRAM, 1, 1);
|
||||
set_nt_page(3, CIRAM, 1, 1);
|
||||
break;
|
||||
|
||||
case PPU_MIRROR_HIGH:
|
||||
set_nt_page(machine, 0, CIRAM, 1, 1);
|
||||
set_nt_page(machine, 1, CIRAM, 1, 1);
|
||||
set_nt_page(machine, 2, CIRAM, 1, 1);
|
||||
set_nt_page(machine, 3, CIRAM, 1, 1);
|
||||
set_nt_page(0, CIRAM, 1, 1);
|
||||
set_nt_page(1, CIRAM, 1, 1);
|
||||
set_nt_page(2, CIRAM, 1, 1);
|
||||
set_nt_page(3, CIRAM, 1, 1);
|
||||
break;
|
||||
|
||||
case PPU_MIRROR_LOW:
|
||||
set_nt_page(machine, 0, CIRAM, 0, 1);
|
||||
set_nt_page(machine, 1, CIRAM, 0, 1);
|
||||
set_nt_page(machine, 2, CIRAM, 0, 1);
|
||||
set_nt_page(machine, 3, CIRAM, 0, 1);
|
||||
set_nt_page(0, CIRAM, 0, 1);
|
||||
set_nt_page(1, CIRAM, 0, 1);
|
||||
set_nt_page(2, CIRAM, 0, 1);
|
||||
set_nt_page(3, CIRAM, 0, 1);
|
||||
break;
|
||||
|
||||
case PPU_MIRROR_NONE:
|
||||
@ -653,10 +551,10 @@ void set_nt_mirroring( running_machine &machine, int mirroring )
|
||||
|
||||
logerror("Mapper set 4-screen mirroring without supplying external nametable memory!\n");
|
||||
|
||||
set_nt_page(machine, 0, CIRAM, 0, 1);
|
||||
set_nt_page(machine, 1, CIRAM, 0, 1);
|
||||
set_nt_page(machine, 2, CIRAM, 1, 1);
|
||||
set_nt_page(machine, 3, CIRAM, 1, 1);
|
||||
set_nt_page(0, CIRAM, 0, 1);
|
||||
set_nt_page(1, CIRAM, 0, 1);
|
||||
set_nt_page(2, CIRAM, 1, 1);
|
||||
set_nt_page(3, CIRAM, 1, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user