mirror of
https://github.com/holub/mame
synced 2025-10-04 16:34:53 +03:00
ribrac, awetoss: Combine into a single driver and start fleshing it out (nw)
This commit is contained in:
parent
bcfa7ba9eb
commit
3274284dbd
@ -4765,7 +4765,6 @@ files {
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MAME_DIR .. "src/mame/includes/ladyfrog.h",
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MAME_DIR .. "src/mame/video/ladyfrog.cpp",
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MAME_DIR .. "src/mame/drivers/laserbas.cpp",
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MAME_DIR .. "src/mame/drivers/laz_awetoss.cpp",
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MAME_DIR .. "src/mame/drivers/laz_aftrshok.cpp",
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MAME_DIR .. "src/mame/drivers/laz_ribrac.cpp",
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MAME_DIR .. "src/mame/drivers/lethalj.cpp",
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@ -639,7 +639,6 @@ lastbank.cpp
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lastduel.cpp
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lastfght.cpp
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laz_aftrshok.cpp
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laz_awetoss.cpp
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laz_ribrac.cpp
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lazercmd.cpp
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lbeach.cpp
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@ -1,86 +0,0 @@
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// license:BSD-3-Clause
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// copyright-holders:David Haywood
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/*
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Awesome tossem u21 = 27c512
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u7 = 27c512 cpu
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u10-u7 and u11-u14 = 27c512 sound board
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probably http://www.highwaygames.com/arcade-machines/awesome-toss-em-7115/
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*/
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#include "emu.h"
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#include "sound/okim6295.h"
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#include "speaker.h"
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class awetoss_state : public driver_device
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{
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public:
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awetoss_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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// ,m_maincpu(*this, "maincpu")
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{ }
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void awetoss(machine_config &config);
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private:
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virtual void machine_start() override;
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virtual void machine_reset() override;
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// required_device<mcs51_cpu_device> m_maincpu;
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};
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static INPUT_PORTS_START( awetoss )
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INPUT_PORTS_END
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void awetoss_state::machine_start()
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{
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}
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void awetoss_state::machine_reset()
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{
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}
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void awetoss_state::awetoss(machine_config &config)
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{
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/* basic machine hardware */
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// ??_device &maincpu(??(config, "maincpu", 8000000)); // unknown
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// maincpu.set_addrmap(AS_PROGRAM, &awetoss_state::awetoss_map);
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// maincpu.set_addrmap(AS_IO, &awetoss_state::awetoss_io);
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// maincpu.set_vblank_int("screen", FUNC(awetoss_state::irq0_line_hold));
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/* sound hardware */
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SPEAKER(config, "mono").front_center();
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OKIM6295(config, "oki", 1000000, okim6295_device::PIN7_HIGH).add_route(ALL_OUTPUTS, "mono", 1.0); // maybe
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}
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ROM_START( awetoss )
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// based on the IC positions differing I don't think this is 2 different sets?
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// both program roms look similar tho
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ROM_REGION( 0x10000, "maincpu", 0 )
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ROM_LOAD( "awsmtoss.u7", 0x00000, 0x10000, CRC(2c48469c) SHA1(5ccca03d6b9cbcaddd73c8a95425f55d9e6af238) )
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ROM_REGION( 0xc0000, "oki", 0 )
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ROM_LOAD( "awsmtoss.u10", 0x00000, 0x10000, CRC(84c8a6b9) SHA1(26dc8c0f2098c9b0ef0e06e5dd69c897a9af69a2) )
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ROM_LOAD( "awsmtoss.u9s", 0x10000, 0x10000, CRC(5c7bbbd9) SHA1(89713058d03f982647217e4c6cbe37969f2537a5) )
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ROM_LOAD( "awsmtoss.u8s", 0x20000, 0x10000, CRC(9852e0bd) SHA1(930cca65e3f7774334dd0513a261f874f94886ac) )
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ROM_LOAD( "awsmtoss.u7s", 0x30000, 0x10000, CRC(32fa11f5) SHA1(70914eac64f53bcb07c0eb9fcc1b4fbeab2fc453) )
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ROM_REGION( 0x10000, "maincpu2", 0 )
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ROM_LOAD( "awsmtoss.u21", 0x00000, 0x10000, CRC(2b66d952) SHA1(b95f019d007cbd1f0325c33ffd1208f2afa6b996) )
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ROM_REGION( 0xc0000, "oki2", 0 )
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ROM_LOAD( "awsmtoss.u14", 0x00000, 0x10000, CRC(6217daaf) SHA1(3036e7f941f787374ef130d3ae6d57813d9e9aac) )
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ROM_LOAD( "awsmtoss.u13", 0x10000, 0x10000, CRC(4ed3c827) SHA1(761d2796d4f40deeb2caa61c4a9c56ced156084b) )
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ROM_LOAD( "awsmtoss.u12", 0x20000, 0x10000, CRC(9ddf6dd9) SHA1(c115828ab261ae6d83cb500057313c3a5570b4b0) )
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ROM_LOAD( "awsmtoss.u11", 0x30000, 0x10000, CRC(8ae9d4f0) SHA1(58d1d8972c8e4c9a7c63e9d63e267ea81515d22a) )
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ROM_END
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GAME( 19??, awetoss, 0, awetoss, awetoss, awetoss_state, empty_init, ROT0, "Lazer-tron", "Awesome Toss'em (Lazer-tron)", MACHINE_IS_SKELETON_MECHANICAL )
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@ -1,5 +1,5 @@
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// license:BSD-3-Clause
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// copyright-holders:David Haywood
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// copyright-holders:David Haywood,AJR
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/*
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ribbit racing -- prog rom 27c512 @ u7
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@ -11,55 +11,307 @@ sound rom dumps weren't present even tho mentioned??
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this appears to be the operators manual
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http://ohwow-arcade.com/Assets/Game_Manuals/RIBBIT%20RACIN.PDF
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Awesome tossem u21 = 27c512
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u7 = 27c512 cpu
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u10-u7 and u11-u14 = 27c512 sound board
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probably http://www.highwaygames.com/arcade-machines/awesome-toss-em-7115/
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*/
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#include "emu.h"
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#include "cpu/mcs51/mcs51.h"
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#include "machine/nvram.h"
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#include "sound/okim6295.h"
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#include "speaker.h"
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class laz_ribrac_state : public driver_device
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class ribrac_state : public driver_device
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{
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public:
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laz_ribrac_state(const machine_config &mconfig, device_type type, const char *tag)
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ribrac_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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// ,m_maincpu(*this, "maincpu")
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, m_maincpu(*this, "maincpu")
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, m_oki(*this, "oki%u", 1U)
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, m_sound_data(0)
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{ }
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void laz_ribrac(machine_config &config);
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void ribrac(machine_config &config);
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private:
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virtual void machine_start() override;
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virtual void machine_reset() override;
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// required_device<mcs51_cpu_device> m_maincpu;
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void sound_data_w(u8 data);
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void sound_control_w(u8 data);
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void motor_w(u8 data);
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void lights_w(u8 data);
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void bonus_w(u8 data);
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void led_w(u8 data);
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void extra_w(u8 data);
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void prog_map(address_map &map);
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void ext_map(address_map &map);
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required_device<mcs51_cpu_device> m_maincpu;
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required_device_array<okim6295_device, 2> m_oki;
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u8 m_sound_data;
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};
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static INPUT_PORTS_START( laz_ribrac )
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void ribrac_state::machine_start()
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{
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save_item(NAME(m_sound_data));
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}
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void ribrac_state::sound_data_w(u8 data)
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{
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m_sound_data = data;
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}
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void ribrac_state::sound_control_w(u8 data)
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{
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if (!BIT(data, 0))
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m_oki[0]->reset();
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else if (!BIT(data, 1) && !BIT(data, 2))
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m_oki[0]->write(m_sound_data);
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if (!BIT(data, 3))
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m_oki[1]->reset();
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else if (!BIT(data, 4) && !BIT(data, 5))
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m_oki[1]->write(m_sound_data);
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}
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void ribrac_state::motor_w(u8 data)
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{
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}
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void ribrac_state::lights_w(u8 data)
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{
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}
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void ribrac_state::bonus_w(u8 data)
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{
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}
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void ribrac_state::led_w(u8 data)
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{
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}
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void ribrac_state::extra_w(u8 data)
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{
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}
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void ribrac_state::prog_map(address_map &map)
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{
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map(0x0000, 0xffff).rom().region("maincpu", 0);
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}
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void ribrac_state::ext_map(address_map &map)
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{
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map(0x0000, 0x0000).mirror(0x700).w(FUNC(ribrac_state::sound_data_w));
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map(0x0800, 0x0800).w(FUNC(ribrac_state::sound_control_w));
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map(0x1000, 0x1000).w(FUNC(ribrac_state::motor_w));
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map(0x1800, 0x1800).w(FUNC(ribrac_state::lights_w));
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map(0x2000, 0x2000).w(FUNC(ribrac_state::bonus_w));
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map(0x2800, 0x2800).w(FUNC(ribrac_state::led_w));
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map(0x3000, 0x3000).w(FUNC(ribrac_state::extra_w));
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map(0x4000, 0x4000).portr("INPUTS1");
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map(0x4800, 0x4800).portr("INPUTS2");
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map(0x5000, 0x5000).portr("INPUTS3");
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map(0x5800, 0x5800).portr("INPUTS4");
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map(0x6000, 0x6000).portr("INPUTS5");
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map(0x8000, 0x9fff).ram().share("nvram");
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}
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static INPUT_PORTS_START( ribrac )
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PORT_START("INPUTS1")
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PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_START("INPUTS2")
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PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_START("INPUTS3")
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PORT_DIPNAME(0x01, 0x01, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:1")
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PORT_DIPSETTING(0x01, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x02, 0x02, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:2")
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PORT_DIPSETTING(0x02, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x04, 0x04, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:3")
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PORT_DIPSETTING(0x04, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x08, 0x08, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:4")
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PORT_DIPSETTING(0x08, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x10, 0x10, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:5")
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PORT_DIPSETTING(0x10, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x20, 0x20, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:6")
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PORT_DIPSETTING(0x20, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x40, 0x40, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:7")
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PORT_DIPSETTING(0x40, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x80, 0x80, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:8")
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PORT_DIPSETTING(0x80, DEF_STR(Off))
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PORT_START("INPUTS4")
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PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_START("INPUTS5")
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PORT_DIPNAME(0x01, 0x01, DEF_STR(Unknown)) PORT_DIPLOCATION("SET2:1")
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PORT_DIPSETTING(0x01, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x02, 0x02, DEF_STR(Unknown)) PORT_DIPLOCATION("SET2:2")
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PORT_DIPSETTING(0x02, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x04, 0x04, DEF_STR(Unknown)) PORT_DIPLOCATION("SET2:3")
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PORT_DIPSETTING(0x04, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x08, 0x08, DEF_STR(Unknown)) PORT_DIPLOCATION("SET2:4")
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PORT_DIPSETTING(0x08, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x10, 0x10, DEF_STR(Unknown)) PORT_DIPLOCATION("SET3:1")
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PORT_DIPSETTING(0x10, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x20, 0x20, DEF_STR(Unknown)) PORT_DIPLOCATION("SET3:2")
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PORT_DIPSETTING(0x20, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x40, 0x40, DEF_STR(Unknown)) PORT_DIPLOCATION("SET3:3")
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PORT_DIPSETTING(0x40, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x80, 0x80, DEF_STR(Unknown)) PORT_DIPLOCATION("SET3:4")
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PORT_DIPSETTING(0x80, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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INPUT_PORTS_END
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static INPUT_PORTS_START( awetoss )
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PORT_START("INPUTS1")
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PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_START("INPUTS2")
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PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNKNOWN)
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PORT_START("INPUTS3")
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PORT_DIPNAME(0x01, 0x01, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:1")
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PORT_DIPSETTING(0x01, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x02, 0x02, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:2")
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PORT_DIPSETTING(0x02, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x04, 0x04, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:3")
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PORT_DIPSETTING(0x04, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x08, 0x08, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:4")
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PORT_DIPSETTING(0x08, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x10, 0x10, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:5")
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PORT_DIPSETTING(0x10, DEF_STR(Off))
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PORT_DIPSETTING(0x00, DEF_STR(On))
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PORT_DIPNAME(0x20, 0x20, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:6")
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PORT_DIPSETTING(0x20, DEF_STR(Off))
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||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
PORT_DIPNAME(0x40, 0x40, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:7")
|
||||
PORT_DIPSETTING(0x40, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
PORT_DIPNAME(0x80, 0x80, DEF_STR(Unknown)) PORT_DIPLOCATION("SET1:8")
|
||||
PORT_DIPSETTING(0x80, DEF_STR(Off))
|
||||
|
||||
PORT_START("INPUTS4")
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNKNOWN)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNKNOWN)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNKNOWN)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_UNKNOWN)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNKNOWN)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNKNOWN)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNKNOWN)
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNKNOWN)
|
||||
|
||||
PORT_START("INPUTS5")
|
||||
PORT_DIPNAME(0x01, 0x01, DEF_STR(Unknown)) PORT_DIPLOCATION("SET2:1")
|
||||
PORT_DIPSETTING(0x01, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
PORT_DIPNAME(0x02, 0x02, DEF_STR(Unknown)) PORT_DIPLOCATION("SET2:2")
|
||||
PORT_DIPSETTING(0x02, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
PORT_DIPNAME(0x04, 0x04, DEF_STR(Unknown)) PORT_DIPLOCATION("SET2:3")
|
||||
PORT_DIPSETTING(0x04, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
PORT_DIPNAME(0x08, 0x08, DEF_STR(Unknown)) PORT_DIPLOCATION("SET2:4")
|
||||
PORT_DIPSETTING(0x08, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
PORT_DIPNAME(0x10, 0x10, DEF_STR(Unknown)) PORT_DIPLOCATION("SET3:1")
|
||||
PORT_DIPSETTING(0x10, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
PORT_DIPNAME(0x20, 0x20, DEF_STR(Unknown)) PORT_DIPLOCATION("SET3:2")
|
||||
PORT_DIPSETTING(0x20, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
PORT_DIPNAME(0x40, 0x40, DEF_STR(Unknown)) PORT_DIPLOCATION("SET3:3")
|
||||
PORT_DIPSETTING(0x40, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
PORT_DIPNAME(0x80, 0x80, DEF_STR(Unknown)) PORT_DIPLOCATION("SET3:4")
|
||||
PORT_DIPSETTING(0x80, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
|
||||
void laz_ribrac_state::machine_start()
|
||||
void ribrac_state::ribrac(machine_config &config)
|
||||
{
|
||||
}
|
||||
I80C31(config, m_maincpu, 12_MHz_XTAL);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &ribrac_state::prog_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &ribrac_state::ext_map);
|
||||
|
||||
void laz_ribrac_state::machine_reset()
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void laz_ribrac_state::laz_ribrac(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
// ??_device &maincpu(??(config, "maincpu", 8000000)); // unknown
|
||||
// maincpu.set_addrmap(AS_PROGRAM, &laz_ribrac_state::laz_ribrac_map);
|
||||
// maincpu.set_addrmap(AS_IO, &laz_ribrac_state::laz_ribrac_io);
|
||||
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0); // 6264 + MAX694 + battery
|
||||
|
||||
/* sound hardware */
|
||||
SPEAKER(config, "mono").front_center();
|
||||
SPEAKER(config, "lspeaker").front_left();
|
||||
SPEAKER(config, "rspeaker").front_right();
|
||||
|
||||
OKIM6295(config, "oki", 1000000, okim6295_device::PIN7_HIGH).add_route(ALL_OUTPUTS, "mono", 1.0); // maybe
|
||||
OKIM6295(config, m_oki[0], 2.097152_MHz_XTAL, okim6295_device::PIN7_HIGH);
|
||||
m_oki[0]->add_route(ALL_OUTPUTS, "lspeaker", 1.0);
|
||||
|
||||
OKIM6295(config, m_oki[1], 2.097152_MHz_XTAL, okim6295_device::PIN7_HIGH);
|
||||
m_oki[1]->add_route(ALL_OUTPUTS, "rspeaker", 1.0);
|
||||
}
|
||||
|
||||
|
||||
@ -68,7 +320,7 @@ ROM_START( ribrac )
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_LOAD( "ribbitr.u7", 0x00000, 0x10000, CRC(9eb78ca3) SHA1(4fede7bdd30449602a01489dc72dbbd5452d6b5a) )
|
||||
|
||||
ROM_REGION( 0xc0000, "oki", 0 )
|
||||
ROM_REGION( 0xc0000, "oki1", 0 )
|
||||
ROM_LOAD( "ribbitr_snd.u10", 0x00000, 0x10000, NO_DUMP )
|
||||
ROM_LOAD( "ribbitr_snd.u9", 0x10000, 0x10000, NO_DUMP )
|
||||
ROM_LOAD( "ribbitr_snd.u8", 0x20000, 0x10000, NO_DUMP )
|
||||
@ -81,4 +333,27 @@ ROM_START( ribrac )
|
||||
ROM_LOAD( "ribbitr_snd.u11", 0x30000, 0x10000, NO_DUMP )
|
||||
ROM_END
|
||||
|
||||
GAME( 1993, ribrac, 0, laz_ribrac, laz_ribrac, laz_ribrac_state, empty_init, ROT0, "Lazer-tron", "Ribbit Racing (Lazer-tron)", MACHINE_IS_SKELETON_MECHANICAL )
|
||||
ROM_START( awetoss )
|
||||
// based on the IC positions differing I don't think this is 2 different sets?
|
||||
// both program roms look similar tho
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_LOAD( "awsmtoss.u7", 0x00000, 0x10000, CRC(2c48469c) SHA1(5ccca03d6b9cbcaddd73c8a95425f55d9e6af238) )
|
||||
|
||||
ROM_REGION( 0xc0000, "oki1", 0 )
|
||||
ROM_LOAD( "awsmtoss.u10", 0x00000, 0x10000, CRC(84c8a6b9) SHA1(26dc8c0f2098c9b0ef0e06e5dd69c897a9af69a2) )
|
||||
ROM_LOAD( "awsmtoss.u9s", 0x10000, 0x10000, CRC(5c7bbbd9) SHA1(89713058d03f982647217e4c6cbe37969f2537a5) )
|
||||
ROM_LOAD( "awsmtoss.u8s", 0x20000, 0x10000, CRC(9852e0bd) SHA1(930cca65e3f7774334dd0513a261f874f94886ac) )
|
||||
ROM_LOAD( "awsmtoss.u7s", 0x30000, 0x10000, CRC(32fa11f5) SHA1(70914eac64f53bcb07c0eb9fcc1b4fbeab2fc453) )
|
||||
|
||||
ROM_REGION( 0x10000, "maincpu2", 0 )
|
||||
ROM_LOAD( "awsmtoss.u21", 0x00000, 0x10000, CRC(2b66d952) SHA1(b95f019d007cbd1f0325c33ffd1208f2afa6b996) )
|
||||
|
||||
ROM_REGION( 0xc0000, "oki2", 0 )
|
||||
ROM_LOAD( "awsmtoss.u14", 0x00000, 0x10000, CRC(6217daaf) SHA1(3036e7f941f787374ef130d3ae6d57813d9e9aac) )
|
||||
ROM_LOAD( "awsmtoss.u13", 0x10000, 0x10000, CRC(4ed3c827) SHA1(761d2796d4f40deeb2caa61c4a9c56ced156084b) )
|
||||
ROM_LOAD( "awsmtoss.u12", 0x20000, 0x10000, CRC(9ddf6dd9) SHA1(c115828ab261ae6d83cb500057313c3a5570b4b0) )
|
||||
ROM_LOAD( "awsmtoss.u11", 0x30000, 0x10000, CRC(8ae9d4f0) SHA1(58d1d8972c8e4c9a7c63e9d63e267ea81515d22a) )
|
||||
ROM_END
|
||||
|
||||
GAME( 1993, ribrac, 0, ribrac, ribrac, ribrac_state, empty_init, ROT0, "Lazer-Tron", "Ribbit Racin (Lazer-Tron)", MACHINE_IS_SKELETON_MECHANICAL )
|
||||
GAME( 19??, awetoss, 0, ribrac, awetoss, ribrac_state, empty_init, ROT0, "Lazer-Tron", "Awesome Toss 'Em (Lazer-Tron)", MACHINE_NOT_WORKING | MACHINE_MECHANICAL )
|
||||
|
@ -18515,14 +18515,12 @@ madgearj // 2/1989 (c) 1989 (Japan)
|
||||
lastfght // (c) 2000 Subsino
|
||||
|
||||
@source:laz_aftrshok.cpp
|
||||
aftrshok // Lazer-tron After Shock
|
||||
aftrshok // Lazer-Tron After Shock
|
||||
aftrshoka //
|
||||
|
||||
@source:laz_awetoss.cpp
|
||||
awetoss // Lazer-tron Awesome Toss'em
|
||||
|
||||
@source:laz_ribrac.cpp
|
||||
ribrac // Lazer-tron Ribbit Racing
|
||||
awetoss // Lazer-Tron Awesome Toss 'Em
|
||||
ribrac // Lazer-Tron Ribbit Racin
|
||||
|
||||
@source:lazercmd.cpp
|
||||
bbonk // [1976?]
|
||||
|
Loading…
Reference in New Issue
Block a user