diff --git a/src/mame/audio/cage.c b/src/mame/audio/cage.c index e04a6551fe0..66753b37372 100644 --- a/src/mame/audio/cage.c +++ b/src/mame/audio/cage.c @@ -45,10 +45,10 @@ static attotime serial_period_per_word; static UINT8 dma_enabled; static UINT8 dma_timer_enabled; -static emu_timer *dma_timer; +static const device_config *dma_timer; static UINT8 cage_timer_enabled[2]; -static emu_timer *timer[2]; +static const device_config *timer[2]; static UINT32 *tms32031_io_regs; @@ -140,8 +140,8 @@ static const char *const register_names[] = * *************************************/ -static TIMER_CALLBACK( dma_timer_callback ); -static TIMER_CALLBACK( cage_timer_callback ); +static TIMER_DEVICE_CALLBACK( dma_timer_callback ); +static TIMER_DEVICE_CALLBACK( cage_timer_callback ); static void update_timer(int which); static WRITE32_HANDLER( speedup_w ); @@ -167,9 +167,9 @@ void cage_init(running_machine *machine, offs_t speedup) cage_cpu_clock_period = ATTOTIME_IN_HZ(cpu_get_clock(cage_cpu)); cage_cpu_h1_clock_period = attotime_mul(cage_cpu_clock_period, 2); - dma_timer = timer_alloc(machine, dma_timer_callback, NULL); - timer[0] = timer_alloc(machine, cage_timer_callback, NULL); - timer[1] = timer_alloc(machine, cage_timer_callback, NULL); + dma_timer = devtag_get_device(machine, "cage_dma_timer"); + timer[0] = devtag_get_device(machine, "cage_timer0"); + timer[1] = devtag_get_device(machine, "cage_timer1"); if (speedup) speedup_ram = memory_install_write32_handler(cpu_get_address_space(cage_cpu, ADDRESS_SPACE_PROGRAM), speedup, speedup, 0, 0, speedup_w); @@ -214,14 +214,14 @@ void cage_reset_w(int state) * *************************************/ -static TIMER_CALLBACK( dma_timer_callback ) +static TIMER_DEVICE_CALLBACK( dma_timer_callback ) { /* if we weren't enabled, don't do anything, just shut ourself off */ if (!dma_enabled) { if (dma_timer_enabled) { - timer_adjust_oneshot(dma_timer, attotime_never, 0); + timer_device_adjust_oneshot(timer, attotime_never, 0); dma_timer_enabled = 0; } return; @@ -272,7 +272,7 @@ static void update_dma_state(const address_space *space) if (!dma_timer_enabled) { attotime period = attotime_mul(serial_period_per_word, tms32031_io_regs[DMA_TRANSFER_COUNT]); - timer_adjust_periodic(dma_timer, period, addr, period); + timer_device_adjust_periodic(dma_timer, period, addr, period); dma_timer_enabled = 1; } } @@ -280,7 +280,7 @@ static void update_dma_state(const address_space *space) /* see if we turned off */ else if (!enabled && dma_enabled) { - timer_adjust_oneshot(dma_timer, attotime_never, 0); + timer_device_adjust_oneshot(dma_timer, attotime_never, 0); dma_timer_enabled = 0; } @@ -296,7 +296,7 @@ static void update_dma_state(const address_space *space) * *************************************/ -static TIMER_CALLBACK( cage_timer_callback ) +static TIMER_DEVICE_CALLBACK( cage_timer_callback ) { int which = param; @@ -322,13 +322,13 @@ static void update_timer(int which) if (tms32031_io_regs[base + TIMER0_GLOBAL_CTL] != 0x2c1) logerror("CAGE TIMER%d: unexpected timer config %08X!\n", which, tms32031_io_regs[base + TIMER0_GLOBAL_CTL]); - timer_adjust_oneshot(timer[which], period, which); + timer_device_adjust_oneshot(timer[which], period, which); } /* see if we turned off */ else if (!enabled && cage_timer_enabled[which]) { - timer_adjust_oneshot(timer[which], attotime_never, which); + timer_device_adjust_oneshot(timer[which], attotime_never, which); } /* set the new state */ @@ -569,12 +569,12 @@ void cage_control_w(running_machine *machine, UINT16 data) dma_enabled = 0; dma_timer_enabled = 0; - timer_adjust_oneshot(dma_timer, attotime_never, 0); + timer_device_adjust_oneshot(dma_timer, attotime_never, 0); cage_timer_enabled[0] = 0; cage_timer_enabled[1] = 0; - timer_adjust_oneshot(timer[0], attotime_never, 0); - timer_adjust_oneshot(timer[1], attotime_never, 0); + timer_device_adjust_oneshot(timer[0], attotime_never, 0); + timer_device_adjust_oneshot(timer[1], attotime_never, 0); memset(tms32031_io_regs, 0, 0x60 * 4); @@ -654,6 +654,10 @@ MACHINE_DRIVER_START( cage ) MDRV_CPU_CONFIG(cage_config) MDRV_CPU_PROGRAM_MAP(cage_map) + MDRV_TIMER_ADD("cage_dma_timer", dma_timer_callback) + MDRV_TIMER_ADD("cage_timer0", cage_timer_callback) + MDRV_TIMER_ADD("cage_timer1", cage_timer_callback) + /* sound hardware */ MDRV_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") diff --git a/src/mame/audio/dcs.c b/src/mame/audio/dcs.c index 9e712f587aa..f8e67dbb5f8 100644 --- a/src/mame/audio/dcs.c +++ b/src/mame/audio/dcs.c @@ -296,9 +296,9 @@ struct _dcs_state UINT16 size; UINT16 incs; const device_config *dmadac[6]; - emu_timer * reg_timer; - emu_timer * sport_timer; - emu_timer * internal_timer; + const device_config *reg_timer; + const device_config *sport_timer; + const device_config *internal_timer; INT32 ireg; UINT16 ireg_base; UINT16 control_regs[32]; @@ -350,7 +350,7 @@ struct _hle_transfer_state INT32 writes_left; UINT16 sum; INT32 fifo_entries; - emu_timer * watchdog; + const device_config *watchdog; }; @@ -410,16 +410,16 @@ static READ16_HANDLER( output_control_r ); static WRITE16_HANDLER( output_control_w ); static void timer_enable_callback(const device_config *device, int enable); -static TIMER_CALLBACK( internal_timer_callback ); -static TIMER_CALLBACK( dcs_irq ); -static TIMER_CALLBACK( sport0_irq ); +static TIMER_DEVICE_CALLBACK( internal_timer_callback ); +static TIMER_DEVICE_CALLBACK( dcs_irq ); +static TIMER_DEVICE_CALLBACK( sport0_irq ); static void recompute_sample_rate(running_machine *machine); static void sound_tx_callback(const device_config *device, int port, INT32 data); static READ16_HANDLER( dcs_polling_r ); static WRITE16_HANDLER( dcs_polling_w ); -static TIMER_CALLBACK( transfer_watchdog_callback ); +static TIMER_DEVICE_CALLBACK( transfer_watchdog_callback ); static int preprocess_write(running_machine *machine, UINT16 data); @@ -613,6 +613,9 @@ MACHINE_DRIVER_START( dcs_audio_2k ) MDRV_CPU_CONFIG(adsp_config) MDRV_CPU_PROGRAM_MAP(dcs_2k_program_map) MDRV_CPU_DATA_MAP(dcs_2k_data_map) + + MDRV_TIMER_ADD("dcs_reg_timer", dcs_irq) + MDRV_TIMER_ADD("dcs_int_timer", internal_timer_callback) MDRV_SPEAKER_STANDARD_MONO("mono") @@ -652,6 +655,11 @@ MACHINE_DRIVER_START( dcs2_audio_2115 ) MDRV_CPU_CONFIG(adsp_config) MDRV_CPU_PROGRAM_MAP(dcs2_2115_program_map) MDRV_CPU_DATA_MAP(dcs2_2115_data_map) + + MDRV_TIMER_ADD("dcs_reg_timer", dcs_irq) + MDRV_TIMER_ADD("dcs_sport_timer", sport0_irq) + MDRV_TIMER_ADD("dcs_int_timer", internal_timer_callback) + MDRV_TIMER_ADD("dcs_hle_timer", transfer_watchdog_callback) MDRV_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") @@ -855,11 +863,11 @@ static TIMER_CALLBACK( dcs_reset ) /* reset timers */ dcs.timer_enable = 0; dcs.timer_scale = 1; - timer_adjust_oneshot(dcs.internal_timer, attotime_never, 0); + timer_device_adjust_oneshot(dcs.internal_timer, attotime_never, 0); /* start the SPORT0 timer */ - if (dcs.sport_timer) - timer_adjust_periodic(dcs.sport_timer, ATTOTIME_IN_HZ(1000), 0, ATTOTIME_IN_HZ(1000)); + if (dcs.sport_timer != NULL) + timer_device_adjust_periodic(dcs.sport_timer, ATTOTIME_IN_HZ(1000), 0, ATTOTIME_IN_HZ(1000)); /* reset the HLE transfer states */ transfer.dcs_state = transfer.state = 0; @@ -948,8 +956,8 @@ void dcs_init(running_machine *machine) memory_configure_bank(machine, "databank", 0, dcs.sounddata_banks, dcs.sounddata, 0x1000*2); /* create the timers */ - dcs.internal_timer = timer_alloc(machine, internal_timer_callback, NULL); - dcs.reg_timer = timer_alloc(machine, dcs_irq, NULL); + dcs.internal_timer = devtag_get_device(machine, "dcs_int_timer"); + dcs.reg_timer = devtag_get_device(machine, "dcs_reg_timer"); /* non-RAM based automatically acks */ dcs.auto_ack = TRUE; @@ -1013,9 +1021,9 @@ void dcs2_init(running_machine *machine, int dram_in_mb, offs_t polling_offset) dcs_sram = auto_alloc_array(machine, UINT16, 0x8000*4/2); /* create the timers */ - dcs.internal_timer = timer_alloc(machine, internal_timer_callback, NULL); - dcs.reg_timer = timer_alloc(machine, dcs_irq, NULL); - dcs.sport_timer = timer_alloc(machine, sport0_irq, NULL); + dcs.internal_timer = devtag_get_device(machine, "dcs_int_timer"); + dcs.reg_timer = devtag_get_device(machine, "dcs_reg_timer"); + dcs.sport_timer = devtag_get_device(machine, "dcs_sport_timer"); /* we don't do auto-ack by default */ dcs.auto_ack = FALSE; @@ -1028,7 +1036,7 @@ void dcs2_init(running_machine *machine, int dram_in_mb, offs_t polling_offset) /* allocate a watchdog timer for HLE transfers */ transfer.hle_enabled = (ENABLE_HLE_TRANSFERS && dram_in_mb != 0); if (transfer.hle_enabled) - transfer.watchdog = timer_alloc(machine, transfer_watchdog_callback, NULL); + transfer.watchdog = devtag_get_device(machine, "dcs_hle_timer"); /* register for save states */ dcs_register_state(machine); @@ -1582,7 +1590,7 @@ void dcs_data_w(int data) return; /* if we are DCS1, set a timer to latch the data */ - if (!dcs.sport_timer) + if (dcs.sport_timer == NULL) timer_call_after_resynch(dcs.cpu->machine, NULL, data, dcs_delayed_data_w_callback); else dcs_delayed_data_w(dcs.cpu->machine, data); @@ -1733,7 +1741,7 @@ static void update_timer_count(running_machine *machine) } -static TIMER_CALLBACK( internal_timer_callback ) +static TIMER_DEVICE_CALLBACK( internal_timer_callback ) { INT64 target_cycles; @@ -1745,7 +1753,7 @@ static TIMER_CALLBACK( internal_timer_callback ) /* set the next timer, but only if it's for a reasonable number */ if (!dcs.timer_ignore && (dcs.timer_period > 10 || dcs.timer_scale > 1)) - timer_adjust_oneshot(dcs.internal_timer, cpu_clocks_to_attotime(dcs.cpu, target_cycles), 0); + timer_device_adjust_oneshot(timer, cpu_clocks_to_attotime(dcs.cpu, target_cycles), 0); /* the IRQ line is edge triggered */ cpu_set_input_line(dcs.cpu, ADSP2105_TIMER, ASSERT_LINE); @@ -1781,7 +1789,7 @@ static void reset_timer(running_machine *machine) /* adjust the timer if not optimized */ if (!dcs.timer_ignore) - timer_adjust_oneshot(dcs.internal_timer, cpu_clocks_to_attotime(dcs.cpu, dcs.timer_scale * (dcs.timer_start_count + 1)), 0); + timer_device_adjust_oneshot(dcs.internal_timer, cpu_clocks_to_attotime(dcs.cpu, dcs.timer_scale * (dcs.timer_start_count + 1)), 0); } @@ -1797,7 +1805,7 @@ static void timer_enable_callback(const device_config *device, int enable) else { // mame_printf_debug("Timer disabled\n"); - timer_adjust_oneshot(dcs.internal_timer, attotime_never, 0); + timer_device_adjust_oneshot(dcs.internal_timer, attotime_never, 0); } } @@ -1875,7 +1883,7 @@ static WRITE16_HANDLER( adsp_control_w ) if ((data & 0x0800) == 0) { dmadac_enable(&dcs.dmadac[0], dcs.channels, 0); - timer_adjust_oneshot(dcs.reg_timer, attotime_never, 0); + timer_device_adjust_oneshot(dcs.reg_timer, attotime_never, 0); } break; @@ -1884,7 +1892,7 @@ static WRITE16_HANDLER( adsp_control_w ) if ((data & 0x0002) == 0) { dmadac_enable(&dcs.dmadac[0], dcs.channels, 0); - timer_adjust_oneshot(dcs.reg_timer, attotime_never, 0); + timer_device_adjust_oneshot(dcs.reg_timer, attotime_never, 0); } break; @@ -1930,7 +1938,7 @@ static WRITE16_HANDLER( adsp_control_w ) DCS IRQ GENERATION CALLBACKS ****************************************************************************/ -static TIMER_CALLBACK( dcs_irq ) +static TIMER_DEVICE_CALLBACK( dcs_irq ) { /* get the index register */ int reg = cpu_get_reg(dcs.cpu, ADSP2100_I0 + dcs.ireg); @@ -1966,7 +1974,7 @@ static TIMER_CALLBACK( dcs_irq ) } -static TIMER_CALLBACK( sport0_irq ) +static TIMER_DEVICE_CALLBACK( sport0_irq ) { /* this latches internally, so we just pulse */ /* note that there is non-interrupt code that reads/modifies/writes the output_control */ @@ -1996,7 +2004,7 @@ static void recompute_sample_rate(running_machine *machine) if (dcs.incs) { attotime period = attotime_div(attotime_mul(sample_period, dcs.size), (2 * dcs.channels * dcs.incs)); - timer_adjust_periodic(dcs.reg_timer, period, 0, period); + timer_device_adjust_periodic(dcs.reg_timer, period, 0, period); } } @@ -2049,7 +2057,7 @@ static void sound_tx_callback(const device_config *device, int port, INT32 data) dmadac_enable(&dcs.dmadac[0], dcs.channels, 0); /* remove timer */ - timer_adjust_oneshot(dcs.reg_timer, attotime_never, 0); + timer_device_adjust_oneshot(dcs.reg_timer, attotime_never, 0); } @@ -2097,16 +2105,16 @@ void dcs_fifo_notify(int count, int max) } -static TIMER_CALLBACK( transfer_watchdog_callback ) +static TIMER_DEVICE_CALLBACK( transfer_watchdog_callback ) { int starting_writes_left = param; if (transfer.fifo_entries && starting_writes_left == transfer.writes_left) { for ( ; transfer.fifo_entries; transfer.fifo_entries--) - preprocess_write(machine, (*dcs.fifo_data_r)(dcs.cpu)); + preprocess_write(timer->machine, (*dcs.fifo_data_r)(dcs.cpu)); } - timer_adjust_oneshot(transfer.watchdog, ATTOTIME_IN_MSEC(1), transfer.writes_left); + timer_device_adjust_oneshot(transfer.watchdog, ATTOTIME_IN_MSEC(1), transfer.writes_left); } @@ -2336,7 +2344,7 @@ static int preprocess_stage_2(running_machine *machine, UINT16 data) transfer.sum = 0; if (transfer.hle_enabled) { - timer_adjust_oneshot(transfer.watchdog, ATTOTIME_IN_MSEC(1), transfer.writes_left); + timer_device_adjust_oneshot(transfer.watchdog, ATTOTIME_IN_MSEC(1), transfer.writes_left); return 1; } break; @@ -2363,7 +2371,7 @@ static int preprocess_stage_2(running_machine *machine, UINT16 data) if (transfer.state == 0) { timer_set(machine, ATTOTIME_IN_USEC(1), NULL, transfer.sum, s2_ack_callback); - timer_adjust_oneshot(transfer.watchdog, attotime_never, 0); + timer_device_adjust_oneshot(transfer.watchdog, attotime_never, 0); } return 1; } @@ -2378,7 +2386,7 @@ static int preprocess_write(running_machine *machine, UINT16 data) int result; /* if we're not DCS2, skip */ - if (!dcs.sport_timer) + if (dcs.sport_timer == NULL) return 0; /* state 0 - initialization phase */ diff --git a/src/mame/drivers/midvunit.c b/src/mame/drivers/midvunit.c index 57d4ae2cb6e..39e61cf8820 100644 --- a/src/mame/drivers/midvunit.c +++ b/src/mame/drivers/midvunit.c @@ -41,7 +41,7 @@ static UINT8 adc_shift; static UINT16 last_port0; static UINT8 shifter_state; -static emu_timer *timer[2]; +static const device_config *timer[2]; static double timer_rate; static UINT32 *tms32031_control; @@ -76,8 +76,8 @@ static MACHINE_RESET( midvunit ) memcpy(ram_base, memory_region(machine, "user1"), 0x20000*4); device_reset(cputag_get_cpu(machine, "maincpu")); - timer[0] = timer_alloc(machine, NULL, NULL); - timer[1] = timer_alloc(machine, NULL, NULL); + timer[0] = devtag_get_device(machine, "timer0"); + timer[1] = devtag_get_device(machine, "timer1"); } @@ -89,8 +89,8 @@ static MACHINE_RESET( midvplus ) memcpy(ram_base, memory_region(machine, "user1"), 0x20000*4); device_reset(cputag_get_cpu(machine, "maincpu")); - timer[0] = timer_alloc(machine, NULL, NULL); - timer[1] = timer_alloc(machine, NULL, NULL); + timer[0] = devtag_get_device(machine, "timer0"); + timer[1] = devtag_get_device(machine, "timer1"); devtag_reset(machine, "ide"); } @@ -261,7 +261,7 @@ static READ32_HANDLER( tms32031_control_r ) { /* timer is clocked at 100ns */ int which = (offset >> 4) & 1; - INT32 result = attotime_to_double(attotime_mul(timer_timeelapsed(timer[which]), timer_rate)); + INT32 result = attotime_to_double(attotime_mul(timer_device_timeelapsed(timer[which]), timer_rate)); // logerror("%06X:tms32031_control_r(%02X) = %08X\n", cpu_get_pc(space->cpu), offset, result); return result; } @@ -288,7 +288,7 @@ static WRITE32_HANDLER( tms32031_control_w ) int which = (offset >> 4) & 1; // logerror("%06X:tms32031_control_w(%02X) = %08X\n", cpu_get_pc(space->cpu), offset, data); if (data & 0x40) - timer_adjust_oneshot(timer[which], attotime_never, 0); + timer_device_adjust_oneshot(timer[which], attotime_never, 0); /* bit 0x200 selects internal clocking, which is 1/2 the main CPU clock rate */ if (data & 0x200) @@ -1027,6 +1027,9 @@ static MACHINE_DRIVER_START( midvcommon ) MDRV_MACHINE_START(midvunit) MDRV_MACHINE_RESET(midvunit) MDRV_NVRAM_HANDLER(generic_1fill) + + MDRV_TIMER_ADD("timer0", NULL) + MDRV_TIMER_ADD("timer1", NULL) /* video hardware */ MDRV_PALETTE_LENGTH(32768)