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scud: Fix music; reduce log spam (nw)

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This commit is contained in:
AJR 2017-11-19 00:33:50 -05:00
parent 773d968277
commit 3294bbf884
2 changed files with 15 additions and 11 deletions
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1
src/mame/audio/dsbz80.cpp
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@ -54,6 +54,7 @@ MACHINE_CONFIG_MEMBER( dsbz80_device::device_add_mconfig )
MCFG_CLOCK_ADD("uart_clock", 500000) // 16 times 31.25MHz (standard Sega/MIDI sound data rate) MCFG_CLOCK_ADD("uart_clock", 500000) // 16 times 31.25MHz (standard Sega/MIDI sound data rate)
MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("uart", i8251_device, write_rxc)) MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("uart", i8251_device, write_rxc))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("uart", i8251_device, write_txc))
MACHINE_CONFIG_END MACHINE_CONFIG_END
//************************************************************************** //**************************************************************************

25
src/mame/machine/m3comm.cpp
View File

@ -82,6 +82,9 @@ SEGA 1998
#include "emuopts.h" #include "emuopts.h"
#include "machine/m3comm.h" #include "machine/m3comm.h"
//#define VERBOSE 1
#include "logmacro.h"
#define M68K_TAG "m3commcpu" #define M68K_TAG "m3commcpu"
//////// Model 3 (main CPU @ C00xxxxx) and Hikaru (MMctrl bank 0E) interface //////// Model 3 (main CPU @ C00xxxxx) and Hikaru (MMctrl bank 0E) interface
@ -206,7 +209,7 @@ READ16_MEMBER(m3comm_device::ctrl_r)
case 0x00 / 2: case 0x00 / 2:
return m_commbank; return m_commbank;
default: default:
logerror("M3COMM CtrlRead from %04x mask %04x unimplemented!\n", offset * 2, mem_mask); LOG("M3COMM CtrlRead from %04x mask %04x unimplemented!\n", offset * 2, mem_mask);
return 0; return 0;
} }
} }
@ -228,7 +231,7 @@ WRITE16_MEMBER(m3comm_device::ctrl_w)
case 0xE0 / 2: // unknown, conditionally cleared in IRQ6 (receive complete) handler case 0xE0 / 2: // unknown, conditionally cleared in IRQ6 (receive complete) handler
break; break;
default: default:
logerror("M3COMM CtrlWrite to %04x %04x mask %04x\n", offset * 2, data, mem_mask); LOG("M3COMM CtrlWrite to %04x %04x mask %04x\n", offset * 2, data, mem_mask);
} }
} }
@ -249,7 +252,7 @@ READ16_MEMBER(m3comm_device::ioregs_r)
case 0x8A / 2: case 0x8A / 2:
return m_status1; return m_status1;
default: default:
logerror("M3COMM IOread from %02x mask %04x\n", offset * 2, mem_mask); LOG("M3COMM IOread from %02x mask %04x\n", offset * 2, mem_mask);
return 0; return 0;
} }
} }
@ -262,11 +265,11 @@ WRITE16_MEMBER(m3comm_device::ioregs_w)
break; // it seems one of these ^v is IRQ6 ON/ACK, another is data transfer enable break; // it seems one of these ^v is IRQ6 ON/ACK, another is data transfer enable
case 0x16 / 2: // written 8C at data receive enable, 0 at IRQ6 handler case 0x16 / 2: // written 8C at data receive enable, 0 at IRQ6 handler
if ((data & 0xFF) == 0x8C) { if ((data & 0xFF) == 0x8C) {
logerror("M3COMM Receive offs %04x size %04x\n", recv_offset, recv_size); LOG("M3COMM Receive offs %04x size %04x\n", recv_offset, recv_size);
/* /*
if (!m_line_rx.is_open()) if (!m_line_rx.is_open())
{ {
logerror("M3COMM: listen on %s\n", m_localhost); LOG("M3COMM: listen on %s\n", m_localhost);
m_line_rx.open(m_localhost); m_line_rx.open(m_localhost);
} }
if (m_line_rx.is_open()) if (m_line_rx.is_open())
@ -282,11 +285,11 @@ WRITE16_MEMBER(m3comm_device::ioregs_w)
break; // it seems one of these ^v is IRQ4 ON/ACK, another is data transfer enable break; // it seems one of these ^v is IRQ4 ON/ACK, another is data transfer enable
case 0x1C / 2: // written 8C at data transmit enable, 0 at IRQ4 handler case 0x1C / 2: // written 8C at data transmit enable, 0 at IRQ4 handler
if ((data & 0xFF) == 0x8C) { if ((data & 0xFF) == 0x8C) {
logerror("M3COMM Send offs %04x size %04x\n", send_offset, send_size); LOG("M3COMM Send offs %04x size %04x\n", send_offset, send_size);
/* /*
if (!m_line_tx.is_open()) if (!m_line_tx.is_open())
{ {
logerror("M3COMM: connect to %s\n", m_remotehost); LOG("M3COMM: connect to %s\n", m_remotehost);
m_line_tx.open(m_remotehost); m_line_tx.open(m_remotehost);
} }
if (m_line_tx.is_open()) if (m_line_tx.is_open())
@ -320,7 +323,7 @@ WRITE16_MEMBER(m3comm_device::ioregs_w)
m_commcpu->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE); m_commcpu->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);
break; break;
default: default:
logerror("M3COMM IOwrite to %02x %04x mask %04x\n", offset * 2, data, mem_mask); LOG("M3COMM IOwrite to %02x %04x mask %04x\n", offset * 2, data, mem_mask);
return; return;
} }
} }
@ -373,7 +376,7 @@ READ16_MEMBER(m3comm_device::naomi_r)
return naomi_offset; return naomi_offset;
case 2: // 5F7020 case 2: // 5F7020
{ {
// logerror("M3COMM read @ %08x\n", (naomi_control << 16) | naomi_offset); // LOG("M3COMM read @ %08x\n", (naomi_control << 16) | naomi_offset);
uint16_t value; uint16_t value;
if (naomi_control & 1) if (naomi_control & 1)
value = m68k_ram[naomi_offset / 2]; // FIXME endian value = m68k_ram[naomi_offset / 2]; // FIXME endian
@ -405,7 +408,7 @@ WRITE16_MEMBER(m3comm_device::naomi_w)
// bit 7: ??? // bit 7: ???
// bit 14: G1 DMA bus master 0 - active / 1 - disabled // bit 14: G1 DMA bus master 0 - active / 1 - disabled
// bit 15: 0 - enable / 1 - disable this device ??? // bit 15: 0 - enable / 1 - disable this device ???
// logerror("M3COMM control write %04x\n", data); // LOG("M3COMM control write %04x\n", data);
naomi_control = data; naomi_control = data;
m_commcpu->set_input_line(INPUT_LINE_RESET, (naomi_control & 0x20) ? CLEAR_LINE : ASSERT_LINE); m_commcpu->set_input_line(INPUT_LINE_RESET, (naomi_control & 0x20) ? CLEAR_LINE : ASSERT_LINE);
break; break;
@ -413,7 +416,7 @@ WRITE16_MEMBER(m3comm_device::naomi_w)
naomi_offset = data; naomi_offset = data;
break; break;
case 2: // 5F7020 case 2: // 5F7020
// logerror("M3COMM write @ %08x %04x\n", (naomi_control << 16) | naomi_offset, data); // LOG("M3COMM write @ %08x %04x\n", (naomi_control << 16) | naomi_offset, data);
if (naomi_control & 1) if (naomi_control & 1)
m68k_ram[naomi_offset / 2] = data; // FIXME endian m68k_ram[naomi_offset / 2] = data; // FIXME endian
else { else {