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https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
-netlist: Added 74174 Hex D-Type Flip-Flop with Clear [Ryan Holtz]
This commit is contained in:
therealmogminer@gmail.com
parent
19165cfbfd
commit
32d0f10418
@ -117,6 +117,8 @@ project "netlist"
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MAME_DIR .. "src/lib/netlist/devices/nld_74153.h",
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MAME_DIR .. "src/lib/netlist/devices/nld_74161.cpp",
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MAME_DIR .. "src/lib/netlist/devices/nld_74161.h",
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MAME_DIR .. "src/lib/netlist/devices/nld_74174.cpp",
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MAME_DIR .. "src/lib/netlist/devices/nld_74174.h",
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MAME_DIR .. "src/lib/netlist/devices/nld_74175.cpp",
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MAME_DIR .. "src/lib/netlist/devices/nld_74175.h",
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MAME_DIR .. "src/lib/netlist/devices/nld_74192.cpp",
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@ -79,6 +79,7 @@ NLOBJS := \
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$(NLOBJ)/devices/nld_74123.o \
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$(NLOBJ)/devices/nld_74153.o \
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$(NLOBJ)/devices/nld_74161.o \
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$(NLOBJ)/devices/nld_74174.o \
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$(NLOBJ)/devices/nld_74175.o \
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$(NLOBJ)/devices/nld_74192.o \
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$(NLOBJ)/devices/nld_74193.o \
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@ -118,7 +118,8 @@ static void initialize_factory(factory_list_t &factory)
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ENTRYX(74107A, TTL_74107A, "+CLK,J,K,CLRQ")
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ENTRYX(74123, TTL_74123, "-")
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ENTRYX(74153, TTL_74153, "+C0,C1,C2,C3,A,B,G")
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ENTRYX(74161, TTL_74175, "-")
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ENTRYX(74161, TTL_74161, "-")
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ENTRYX(74174, TTL_74174, "-")
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ENTRYX(74175, TTL_74175, "-")
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ENTRYX(74192, TTL_74192, "-")
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ENTRYX(74193, TTL_74193, "-")
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@ -150,6 +151,8 @@ static void initialize_factory(factory_list_t &factory)
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ENTRYX(74107_dip, TTL_74107_DIP, "-")
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ENTRYX(74123_dip, TTL_74123_DIP, "-")
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ENTRYX(74153_dip, TTL_74153_DIP, "-")
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ENTRYX(74161_dip, TTL_74161_DIP, "-")
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ENTRYX(74174_dip, TTL_74174_DIP, "-")
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ENTRYX(74175_dip, TTL_74175_DIP, "-")
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ENTRYX(74192_dip, TTL_74192_DIP, "-")
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ENTRYX(74193_dip, TTL_74193_DIP, "-")
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@ -27,6 +27,7 @@
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#include "nld_74123.h"
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#include "nld_74153.h"
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#include "nld_74161.h"
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#include "nld_74174.h"
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#include "nld_74175.h"
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#include "nld_74192.h"
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#include "nld_74193.h"
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140
src/lib/netlist/devices/nld_74174.cpp
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140
src/lib/netlist/devices/nld_74174.cpp
Normal file
@ -0,0 +1,140 @@
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// license:GPL-2.0+
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// copyright-holders:Couriersud
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/*
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* nld_74174.cpp
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*
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*/
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#include "nld_74174.h"
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namespace netlist
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{
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namespace devices
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{
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NETLIB_OBJECT(74174_sub)
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{
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NETLIB_CONSTRUCTOR(74174_sub)
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, m_CLK(*this, "CLK")
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, m_Q(*this, {{"Q1", "Q2", "Q3", "Q4", "Q5", "Q6"}})
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, m_clrq(*this, "m_clr", 0)
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, m_data(*this, "m_data", 0)
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{
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}
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NETLIB_RESETI();
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NETLIB_UPDATEI();
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public:
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logic_input_t m_CLK;
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object_array_t<logic_output_t, 6> m_Q;
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state_var<netlist_sig_t> m_clrq;
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state_var<unsigned> m_data;
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};
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NETLIB_OBJECT(74174)
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{
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NETLIB_CONSTRUCTOR(74174)
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, m_sub(*this, "sub")
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, m_D(*this, {{"D1", "D2", "D3", "D4", "D5", "D6"}})
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, m_CLRQ(*this, "CLRQ")
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{
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register_subalias("CLK", m_sub.m_CLK);
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register_subalias("Q1", m_sub.m_Q[0]);
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register_subalias("Q2", m_sub.m_Q[1]);
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register_subalias("Q3", m_sub.m_Q[2]);
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register_subalias("Q4", m_sub.m_Q[3]);
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register_subalias("Q5", m_sub.m_Q[4]);
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register_subalias("Q6", m_sub.m_Q[5]);
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}
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NETLIB_RESETI();
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NETLIB_UPDATEI();
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protected:
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NETLIB_SUB(74174_sub) m_sub;
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object_array_t<logic_input_t, 6> m_D;
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logic_input_t m_CLRQ;
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};
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NETLIB_OBJECT_DERIVED(74174_dip, 74174)
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{
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NETLIB_CONSTRUCTOR_DERIVED(74174_dip, 74174)
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{
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register_subalias("1", m_CLRQ);
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register_subalias("9", m_sub.m_CLK);
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register_subalias("3", m_D[0]);
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register_subalias("2", m_sub.m_Q[0]);
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register_subalias("4", m_D[1]);
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register_subalias("5", m_sub.m_Q[1]);
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register_subalias("6", m_D[2]);
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register_subalias("7", m_sub.m_Q[2]);
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register_subalias("11", m_D[3]);
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register_subalias("10", m_sub.m_Q[3]);
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register_subalias("13", m_D[4]);
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register_subalias("12", m_sub.m_Q[4]);
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register_subalias("14", m_D[5]);
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register_subalias("15", m_sub.m_Q[5]);
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}
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};
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NETLIB_RESET(74174_sub)
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{
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m_CLK.set_state(logic_t::STATE_INP_LH);
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m_clrq = 0;
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m_data = 0xFF;
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}
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NETLIB_UPDATE(74174_sub)
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{
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if (m_clrq)
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{
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for (std::size_t i=0; i<6; i++)
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{
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netlist_sig_t d = (m_data >> i) & 1;
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m_Q[i].push(d, NLTIME_FROM_NS(25));
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}
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m_CLK.inactivate();
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}
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}
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NETLIB_UPDATE(74174)
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{
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uint_fast8_t d = 0;
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for (std::size_t i=0; i<6; i++)
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{
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d |= (m_D[i]() << i);
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}
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m_sub.m_clrq = m_CLRQ();
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if (!m_sub.m_clrq)
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{
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for (std::size_t i=0; i<6; i++)
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{
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m_sub.m_Q[i].push(0, NLTIME_FROM_NS(40));
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}
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m_sub.m_data = 0;
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} else if (d != m_sub.m_data)
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{
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m_sub.m_data = d;
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m_sub.m_CLK.activate_lh();
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}
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}
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NETLIB_RESET(74174)
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{
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//m_sub.do_reset();
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}
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NETLIB_DEVICE_IMPL(74174)
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NETLIB_DEVICE_IMPL(74174_dip)
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} //namespace devices
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} // namespace netlist
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47
src/lib/netlist/devices/nld_74174.h
Normal file
47
src/lib/netlist/devices/nld_74174.h
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@ -0,0 +1,47 @@
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// license:GPL-2.0+
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// copyright-holders:Couriersud
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/*
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* nld_74174.h
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*
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* DM74174: hEX D Flip-Flops with Clear
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*
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* +--------------+
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* CLR |1 ++ 16| VCC
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* Q1 |2 15| Q6
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* D1 |3 14| D6
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* D2 |4 74174 13| D5
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* Q2 |5 12| Q5
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* D3 |6 11| D4
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* Q3 |7 10| Q4
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* GND |8 9| CLK
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* +--------------+
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*
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* +-----+-----+---++---+-----+
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* | CLR | CLK | D || Q | QQ |
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* +=====+=====+===++===+=====+
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* | 0 | X | X || 0 | 1 |
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* | 1 | R | 1 || 1 | 0 |
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* | 1 | R | 0 || 0 | 1 |
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* | 1 | 0 | X || Q0| Q0Q |
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* +-----+-----+---++---+-----+
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*
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* Q0 The output logic level of Q before the indicated input conditions were established
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*
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* R: 0 -> 1
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*
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* Naming conventions follow National Semiconductor datasheet
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*
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*/
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#ifndef NLD_74174_H_
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#define NLD_74174_H_
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#include "nl_setup.h"
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#define TTL_74174(name) \
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NET_REGISTER_DEV(TTL_74174, name)
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#define TTL_74174_DIP(name) \
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NET_REGISTER_DEV(TTL_74174_DIP, name)
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#endif /* NLD_74174_H_ */
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@ -28,7 +28,7 @@ namespace netlist
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object_array_t<logic_input_t, 8> m_A;
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logic_input_t m_CE1Q;
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logic_input_t m_CE2Q;
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object_array_t<logic_output_t, 8> m_O;
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object_array_t<logic_output_t, 4> m_O;
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param_rom_t m_ROM; // 1024 bits, 32x32, used as 256x4
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};
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