mirror of
https://github.com/holub/mame
synced 2025-04-23 08:49:55 +03:00
Wrote a preliminary TGPx4 interpreter core [Angelo Salese]
i960.cpp: support burst stall on writes [Angelo Salese]
This commit is contained in:
angelosa
parent
de5a35530b
commit
3344b2f6ac
@ -601,12 +601,13 @@ void i960_cpu_device::do_ret()
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// if last opcode was a multi dword burst read opcode save the data here
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// i.e. Model 2 FIFO reads with ldl, ldt, ldq
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void i960_cpu_device::burst_stall_save(uint32_t t1, uint32_t t2, int index, int size)
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void i960_cpu_device::burst_stall_save(uint32_t t1, uint32_t t2, int index, int size, bool iswriteop)
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{
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m_stall_state.t1 = t1;
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m_stall_state.t2 = t2;
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m_stall_state.index = index;
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m_stall_state.size = size;
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m_stall_state.iswriteop = iswriteop;
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m_stall_state.burst_mode = true;
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}
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@ -620,9 +621,12 @@ void i960_cpu_device::execute_burst_stall_op(uint32_t opcode)
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// check if our data is ready
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for(i=m_stall_state.index ; i<m_stall_state.size ;i++)
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{
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// count down 1 icount for every read
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// count down 1 icount for every op
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m_icount--;
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m_r[m_stall_state.t2+i] = i960_read_dword_unaligned(m_stall_state.t1);
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if(m_stall_state.iswriteop == true)
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i960_write_dword_unaligned(m_stall_state.t1, m_r[m_stall_state.t2+i]);
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else
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m_r[m_stall_state.t2+i] = i960_read_dword_unaligned(m_stall_state.t1);
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// if the host returned stall just save the index and try again on a later moment
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if(m_stalled == true)
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@ -1952,7 +1956,7 @@ void i960_cpu_device::execute_op(uint32_t opcode)
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m_r[t2+i] = i960_read_dword_unaligned(t1);
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if(m_stalled)
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{
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burst_stall_save(t1,t2,i,2);
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burst_stall_save(t1,t2,i,2,false);
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return;
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}
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if(m_bursting)
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@ -1969,6 +1973,11 @@ void i960_cpu_device::execute_op(uint32_t opcode)
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m_bursting = 1;
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for(i=0; i<2; i++) {
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i960_write_dword_unaligned(t1, m_r[t2+i]);
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if(m_stalled)
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{
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burst_stall_save(t1,t2,i,2,true);
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return;
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}
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if(m_bursting)
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t1 += 4;
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}
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@ -1985,7 +1994,7 @@ void i960_cpu_device::execute_op(uint32_t opcode)
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m_r[t2+i] = i960_read_dword_unaligned(t1);
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if(m_stalled)
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{
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burst_stall_save(t1,t2,i,3);
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burst_stall_save(t1,t2,i,3,false);
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return;
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}
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if(m_bursting)
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@ -2002,6 +2011,11 @@ void i960_cpu_device::execute_op(uint32_t opcode)
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m_bursting = 1;
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for(i=0; i<3; i++) {
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i960_write_dword_unaligned(t1, m_r[t2+i]);
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if(m_stalled)
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{
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burst_stall_save(t1,t2,i,3,true);
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return;
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}
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if(m_bursting)
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t1 += 4;
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}
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@ -2018,7 +2032,7 @@ void i960_cpu_device::execute_op(uint32_t opcode)
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m_r[t2+i] = i960_read_dword_unaligned(t1);
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if(m_stalled)
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{
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burst_stall_save(t1,t2,i,4);
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burst_stall_save(t1,t2,i,4,false);
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return;
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}
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if(m_bursting)
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@ -2035,6 +2049,11 @@ void i960_cpu_device::execute_op(uint32_t opcode)
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m_bursting = 1;
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for(i=0; i<4; i++) {
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i960_write_dword_unaligned(t1, m_r[t2+i]);
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if(m_stalled)
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{
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burst_stall_save(t1,t2,i,4,true);
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return;
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}
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if(m_bursting)
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t1 += 4;
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}
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@ -104,12 +104,13 @@ protected:
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virtual util::disasm_interface *create_disassembler() override;
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private:
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void burst_stall_save(uint32_t t1, uint32_t t2, int index, int size);
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void burst_stall_save(uint32_t t1, uint32_t t2, int index, int size, bool iswriteop);
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struct {
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uint32_t t1,t2;
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int index,size;
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bool burst_mode;
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bool iswriteop;
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}m_stall_state;
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bool m_stalled;
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@ -7,7 +7,14 @@
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* Written by Angelo Salese & ElSemi
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*
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* TODO:
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* - Everything!
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* - rewrite ALU integer/floating point functions, use templates etc;
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* - move post-opcodes outside of the execute_op() function, like increment_prp()
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* (needed if opcode uses fifo in/out);
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* - fifo stall shouldn't make the alu opcode to repeat;
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* - illegal delay slot on REP unsupported;
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* - externalize PDR / DDR (error LED flags on Model 2);
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* - instruction cycles;
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* - pipeline (four instruction executed per cycle!)
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*
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*****************************************************************************/
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@ -49,8 +56,31 @@ void mb86235_device::execute_run()
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#if ENABLE_DRC
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run_drc();
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#else
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debugger_instruction_hook(this, m_core->pc);
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m_core->icount = 0;
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uint64_t opcode;
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while(m_core->icount > 0)
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{
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uint32_t curpc;
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curpc = m_core->cur_fifo_state.has_stalled ? m_core->cur_fifo_state.pc : m_core->pc;
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debugger_instruction_hook(this, curpc);
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opcode = m_direct->read_qword(curpc);
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m_core->ppc = curpc;
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if(m_core->delay_slot == true)
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{
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m_core->pc = m_core->delay_pc;
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m_core->delay_slot = false;
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}
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else
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handle_single_step_execution();
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execute_op(opcode >> 32, opcode & 0xffffffff);
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m_core->icount--;
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}
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#endif
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}
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@ -66,7 +96,9 @@ void mb86235_device::device_start()
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memset(m_core, 0, sizeof(mb86235_internal_state));
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#if ENABLE_DRC
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// init UML generator
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uint32_t umlflags = 0;
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m_drcuml = std::make_unique<drcuml_state>(*this, m_cache, umlflags, 1, 24, 0);
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@ -124,7 +156,7 @@ void mb86235_device::device_start()
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m_regmap[i + 16] = uml::mem(&m_core->ma[i]);
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m_regmap[i + 24] = uml::mem(&m_core->mb[i]);
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}
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#endif
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// Register state for debugger
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state_add(MB86235_PC, "PC", m_core->pc).formatstr("%08X");
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@ -168,6 +200,18 @@ void mb86235_device::device_start()
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state_add(MB86235_MB5, "MB5", m_core->mb[5]).formatstr("%08X");
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state_add(MB86235_MB6, "MB6", m_core->mb[6]).formatstr("%08X");
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state_add(MB86235_MB7, "MB7", m_core->mb[7]).formatstr("%08X");
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state_add(MB86235_ST, "ST", m_core->st).formatstr("%08X");
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state_add(MB86235_EB, "EB", m_core->eb).formatstr("%08X");
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state_add(MB86235_EO, "EO", m_core->eo).formatstr("%08X");
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state_add(MB86235_SP, "SP", m_core->sp).formatstr("%08X");
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state_add(MB86235_RPC, "RPC", m_core->rpc).formatstr("%08X");
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state_add(MB86235_LPC, "LPC", m_core->lpc).formatstr("%08X");
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state_add(MB86235_PDR, "PDR", m_core->pdr).formatstr("%08X");
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state_add(MB86235_DDR, "DDR", m_core->ddr).formatstr("%08X");
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state_add(MB86235_MOD, "MOD", m_core->mod).formatstr("%04X");
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state_add(MB86235_PRP, "PRP", m_core->prp).formatstr("%02X");
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state_add(MB86235_PWP, "PWP", m_core->pwp).formatstr("%02X");
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state_add(STATE_GENPC, "GENPC", m_core->pc ).noshow();
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state_add(STATE_GENPCBASE, "CURPC", m_core->pc).noshow();
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@ -178,9 +222,14 @@ void mb86235_device::device_start()
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void mb86235_device::device_reset()
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{
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#if ENABLE_DRC
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flush_cache();
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#endif
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m_core->pc = 0;
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m_core->delay_pc = 0;
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m_core->ppc = 0;
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m_core->delay_slot = false;
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}
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#if 0
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@ -242,57 +291,53 @@ util::disasm_interface *mb86235_device::create_disassembler()
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}
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void mb86235_device::fifoin_w(uint64_t data)
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void mb86235_device::fifoin_w(uint32_t data)
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{
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#if ENABLE_DRC
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if (m_core->fifoin.num >= FIFOIN_SIZE)
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{
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fatalerror("fifoin_w: pushing to full fifo");
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}
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//printf("FIFOIN push %08X%08X\n", (uint32_t)(data >> 32), (uint32_t)(data));
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//printf("FIFOIN push %08X\n", data);
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m_core->fifoin.data[m_core->fifoin.wpos] = data;
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m_core->fifoin.wpos++;
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m_core->fifoin.wpos &= FIFOIN_SIZE-1;
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m_core->fifoin.num++;
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#endif
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}
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bool mb86235_device::is_fifoin_empty()
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{
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return m_core->fifoin.num == 0;
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}
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bool mb86235_device::is_fifoin_full()
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{
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#if ENABLE_DRC
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return m_core->fifoin.num >= FIFOIN_SIZE;
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#else
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return false;
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#endif
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}
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uint64_t mb86235_device::fifoout0_r()
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uint32_t mb86235_device::fifoout0_r()
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{
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#if ENABLE_DRC
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if (m_core->fifoout0.num == 0)
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{
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fatalerror("fifoout0_r: reading from empty fifo");
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}
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uint64_t data = m_core->fifoout0.data[m_core->fifoout0.rpos];
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uint32_t data = m_core->fifoout0.data[m_core->fifoout0.rpos];
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m_core->fifoout0.rpos++;
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m_core->fifoout0.rpos &= FIFOOUT0_SIZE - 1;
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m_core->fifoout0.num--;
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return data;
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#else
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return 0;
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#endif
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}
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bool mb86235_device::is_fifoout0_full()
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{
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return m_core->fifoout0.num >= FIFOOUT0_SIZE;
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}
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bool mb86235_device::is_fifoout0_empty()
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{
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#if ENABLE_DRC
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return m_core->fifoout0.num == 0;
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#else
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return false;
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#endif
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}
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@ -33,10 +33,12 @@ public:
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void pcs_overflow();
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void pcs_underflow();
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void fifoin_w(uint64_t data);
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void fifoin_w(uint32_t data);
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bool is_fifoin_full();
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uint64_t fifoout0_r();
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bool is_fifoin_empty();
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uint32_t fifoout0_r();
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bool is_fifoout0_empty();
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bool is_fifoout0_full();
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enum
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{
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@ -46,6 +48,9 @@ public:
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MB86235_MA0, MB86235_MA1, MB86235_MA2, MB86235_MA3, MB86235_MA4, MB86235_MA5, MB86235_MA6, MB86235_MA7,
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MB86235_MB0, MB86235_MB1, MB86235_MB2, MB86235_MB3, MB86235_MB4, MB86235_MB5, MB86235_MB6, MB86235_MB7,
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MB86235_AR0, MB86235_AR1, MB86235_AR2, MB86235_AR3, MB86235_AR4, MB86235_AR5, MB86235_AR6, MB86235_AR7,
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MB86235_MOD, MB86235_EB, MB86235_EO, MB86235_SP, MB86235_PDR, MB86235_DDR, MB86235_RPC, MB86235_LPC,
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MB86235_PRP, MB86235_PWP,
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MB86235_ST
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};
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static constexpr int FIFOIN_SIZE = 16;
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@ -102,12 +107,20 @@ private:
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int rpos;
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int wpos;
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int num;
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uint64_t data[16];
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uint32_t data[16];
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};
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struct fifo_state
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{
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uint32_t pc;
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bool has_stalled;
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};
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struct mb86235_internal_state
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{
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uint32_t pc;
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uint32_t delay_pc;
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uint32_t ppc;
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uint32_t aa[8];
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uint32_t ab[8];
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uint32_t ma[8];
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@ -125,8 +138,10 @@ private:
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uint32_t pr[24];
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uint32_t mod;
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// TODO: remove this, use ST instead
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mb86235_flags flags;
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uint32_t st;
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int icount;
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uint32_t arg0;
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@ -147,10 +162,12 @@ private:
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uint32_t ddr;
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float fp0;
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bool delay_slot;
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fifo fifoin;
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fifo fifoout0;
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fifo fifoout1;
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fifo_state cur_fifo_state;
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};
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mb86235_internal_state *m_core;
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@ -223,6 +240,44 @@ private:
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void generate_branch_target(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int type, int ef2);
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bool has_register_clash(const opcode_desc *desc, int outreg);
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bool aluop_has_result(int aluop);
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// interpreter
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void execute_op(uint32_t h, uint32_t l);
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void do_alu1(uint32_t h, uint32_t l);
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void do_alu2(uint32_t h, uint32_t l);
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void do_trans2_1(uint32_t h, uint32_t l);
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void do_trans1_1(uint32_t h, uint32_t l);
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void do_trans2_2(uint32_t h, uint32_t l);
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void do_trans1_2(uint32_t h, uint32_t l);
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void do_trans1_3(uint32_t h, uint32_t l);
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void do_control(uint32_t h, uint32_t l);
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inline uint32_t get_prx(uint8_t which);
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inline uint32_t get_constfloat(uint8_t which);
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inline uint32_t get_constint(uint8_t which);
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inline uint32_t get_alureg(uint8_t which, bool isfloatop);
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inline uint32_t get_mulreg(uint8_t which, bool isfloatop);
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inline void set_alureg(uint8_t which, uint32_t value);
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inline void decode_aluop(uint8_t opcode, uint32_t src1, uint32_t src2, uint8_t imm, uint8_t dst_which);
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inline void decode_mulop(bool isfmul, uint32_t src1, uint32_t src2, uint8_t dst_which);
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inline bool decode_branch_jump(uint8_t which);
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inline uint32_t do_control_dst(uint32_t l);
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inline void push_pc(uint32_t pcval);
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inline uint32_t pop_pc();
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inline void set_mod(uint16_t mod1, uint16_t mod2);
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inline uint32_t get_transfer_reg(uint8_t which);
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inline void set_transfer_reg(uint8_t which, uint32_t value);
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inline uint32_t decode_ea(uint8_t mode, uint8_t rx, uint8_t ry, uint16_t disp, bool isbbus);
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inline uint32_t read_bus(bool isbbus, uint32_t addr);
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inline void write_bus(bool isbbus, uint32_t addr, uint32_t data);
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inline void increment_pwp();
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inline void increment_prp();
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inline void decrement_prp();
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inline void zero_prp();
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inline void set_alu_flagsd(uint32_t val);
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inline void set_alu_flagsf(float val);
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inline void set_alu_flagsi(int val);
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inline bool get_alu_second_src(uint8_t which);
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void handle_single_step_execution();
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};
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@ -468,7 +468,7 @@ void mb86235_disassembler::dasm_xfer1(std::ostream &stream, uint64_t opcode)
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}
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}
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void mb86235_disassembler::dasm_double_xfer2_field(std::ostream &stream, int sd, uint32_t field)
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void mb86235_disassembler::dasm_double_xfer2_field(std::ostream &stream, int sd, bool isbbus, uint32_t field)
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{
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switch (sd)
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{
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@ -476,6 +476,11 @@ void mb86235_disassembler::dasm_double_xfer2_field(std::ostream &stream, int sd,
|
||||
{
|
||||
int s = (field >> 13) & 0x1f;
|
||||
int d = (field >> 8) & 0x1f;
|
||||
if(isbbus == true)
|
||||
{
|
||||
s |= 0x20;
|
||||
d |= 0x20;
|
||||
}
|
||||
util::stream_format(stream, "%s, %s", regname[s], regname[d]);
|
||||
break;
|
||||
}
|
||||
@ -576,9 +581,9 @@ void mb86235_disassembler::dasm_double_xfer2(std::ostream &stream, uint64_t opco
|
||||
else
|
||||
{
|
||||
stream << "MVD2 ";
|
||||
dasm_double_xfer2_field(stream, asd, (opcode >> 20) & 0x3ffff);
|
||||
dasm_double_xfer2_field(stream, asd, false, (opcode >> 20) & 0x3ffff);
|
||||
stream << ", ";
|
||||
dasm_double_xfer2_field(stream, bsd, opcode & 0x3ffff);
|
||||
dasm_double_xfer2_field(stream, bsd, true, opcode & 0x3ffff);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -32,7 +32,7 @@ private:
|
||||
void dasm_control(std::ostream &stream, uint32_t pc, uint64_t opcode);
|
||||
void dasm_double_xfer1(std::ostream &stream, uint64_t opcode);
|
||||
void dasm_xfer1(std::ostream &stream, uint64_t opcode);
|
||||
void dasm_double_xfer2_field(std::ostream &stream, int sd, uint32_t field);
|
||||
void dasm_double_xfer2_field(std::ostream &stream, int sd, bool isbbus, uint32_t field);
|
||||
void dasm_double_xfer2(std::ostream &stream, uint64_t opcode);
|
||||
void dasm_xfer2(std::ostream &stream, uint64_t opcode);
|
||||
void dasm_xfer3(std::ostream &stream, uint64_t opcode);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -553,7 +553,7 @@ WRITE32_MEMBER(model2_state::analog_2b_w)
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(model2_state::fifoctl_r)
|
||||
READ32_MEMBER(model2_state::fifo_control_2a_r)
|
||||
{
|
||||
uint32_t r = 0;
|
||||
|
||||
@ -563,7 +563,7 @@ READ32_MEMBER(model2_state::fifoctl_r)
|
||||
}
|
||||
|
||||
// #### 1 if fifo empty, zerogun needs | 0x04 set
|
||||
// TODO: 0x04 is probably fifo full, zeroguna stalls with a fresh nvram with that enabled!
|
||||
// TODO: 0x04 is probably fifo full, zeroguna stalls with a fresh nvram with that enabled?
|
||||
return r;
|
||||
// return r | 0x04;
|
||||
}
|
||||
@ -865,9 +865,18 @@ WRITE32_MEMBER(model2_state::copro_function_port_w)
|
||||
copro_fifoin_push(machine().device("tgp"), d,offset,mem_mask);
|
||||
else if (m_dsp_type == DSP_TYPE_TGPX4)
|
||||
{
|
||||
if (m_tgpx4->is_fifoin_full())
|
||||
printf("trying to push to full fifo! (function port)\n");
|
||||
m_maincpu->i960_noburst();
|
||||
|
||||
if (m_tgpx4->is_fifoin_full())
|
||||
{
|
||||
//fatalerror("model2.cpp: unsupported i960->tgpx4 fifo full");
|
||||
/* Writing to full FIFO causes the i960 to enter wait state */
|
||||
m_maincpu->i960_stall();
|
||||
/* spin the main cpu and let the TGP catch up */
|
||||
m_maincpu->spin_until_time(attotime::from_usec(1));
|
||||
return;
|
||||
}
|
||||
|
||||
m_tgpx4->fifoin_w(d);
|
||||
}
|
||||
}
|
||||
@ -888,8 +897,9 @@ READ32_MEMBER(model2_state::copro_fifo_r)
|
||||
/* Reading from empty FIFO causes the i960 to enter wait state */
|
||||
downcast<i960_cpu_device &>(*m_maincpu).i960_stall();
|
||||
/* spin the main cpu and let the TGP catch up */
|
||||
m_maincpu->spin_until_time(attotime::from_usec(100));
|
||||
printf("stalled\n");
|
||||
m_maincpu->spin_until_time(attotime::from_usec(1));
|
||||
|
||||
return 0x00884000+offset*4;
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -899,6 +909,11 @@ READ32_MEMBER(model2_state::copro_fifo_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2c_state::fifo_control_2c_r)
|
||||
{
|
||||
return (m_tgpx4->is_fifoout0_empty() == true) ? 1 : 0;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_state::copro_fifo_w)
|
||||
{
|
||||
if (m_coproctl & 0x80000000)
|
||||
@ -939,13 +954,15 @@ WRITE32_MEMBER(model2_state::copro_fifo_w)
|
||||
copro_fifoin_push(machine().device("tgp"), data,offset,mem_mask);
|
||||
else if (m_dsp_type == DSP_TYPE_TGPX4)
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
|
||||
if (m_tgpx4->is_fifoin_full())
|
||||
{
|
||||
//fatalerror("model2.cpp: unsupported i960->tgpx4 fifo full");
|
||||
/* Writing to full FIFO causes the i960 to enter wait state */
|
||||
m_maincpu->i960_stall();
|
||||
/* spin the main cpu and let the TGP catch up */
|
||||
m_maincpu->spin_until_time(attotime::from_usec(100));
|
||||
printf("write stalled\n");
|
||||
m_maincpu->spin_until_time(attotime::from_usec(1));
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -1393,7 +1410,7 @@ void model2_state::model2_base_mem(address_map &map)
|
||||
|
||||
map(0x00900000, 0x0091ffff).mirror(0x60000).ram().share("bufferram");
|
||||
|
||||
map(0x00980004, 0x00980007).r(this, FUNC(model2_state::fifoctl_r));
|
||||
map(0x00980004, 0x00980007).r(this, FUNC(model2_state::fifo_control_2a_r));
|
||||
map(0x0098000c, 0x0098000f).rw(this, FUNC(model2_state::videoctl_r), FUNC(model2_state::videoctl_w));
|
||||
map(0x00980030, 0x0098003f).r(this, FUNC(model2_state::tgpid_r));
|
||||
|
||||
@ -1475,7 +1492,7 @@ READ8_MEMBER(model2_state::virtuacop_lightgun_offscreen_r)
|
||||
}
|
||||
|
||||
/* Apparently original Model 2 doesn't have fifo control? */
|
||||
READ32_MEMBER(model2o_state::fifoctrl_r)
|
||||
READ32_MEMBER(model2o_state::fifo_control_2o_r)
|
||||
{
|
||||
return 0xffffffff;
|
||||
}
|
||||
@ -1509,7 +1526,7 @@ void model2o_state::model2o_mem(address_map &map)
|
||||
map(0x00884000, 0x00887fff).rw(this, FUNC(model2o_state::copro_fifo_r), FUNC(model2o_state::copro_fifo_w));
|
||||
|
||||
map(0x00980000, 0x00980003).rw(this, FUNC(model2o_state::copro_ctl1_r), FUNC(model2o_state::copro_ctl1_w));
|
||||
map(0x00980004, 0x00980007).r(this, FUNC(model2o_state::fifoctrl_r));
|
||||
map(0x00980004, 0x00980007).r(this, FUNC(model2o_state::fifo_control_2o_r));
|
||||
map(0x00980008, 0x0098000b).w(this, FUNC(model2o_state::geo_ctl1_w));
|
||||
map(0x009c0000, 0x009cffff).rw(this, FUNC(model2o_state::model2_serial_r), FUNC(model2o_state::model2_serial_w));
|
||||
|
||||
@ -1692,6 +1709,7 @@ void model2c_state::model2c_crx_mem(address_map &map)
|
||||
map(0x00884000, 0x00887fff).rw(this, FUNC(model2c_state::copro_fifo_r), FUNC(model2c_state::copro_fifo_w));
|
||||
|
||||
map(0x00980000, 0x00980003).rw(this, FUNC(model2c_state::copro_ctl1_r), FUNC(model2c_state::copro_ctl1_w));
|
||||
map(0x00980004, 0x00980007).r(this, FUNC(model2c_state::fifo_control_2c_r));
|
||||
map(0x00980008, 0x0098000b).w(this, FUNC(model2c_state::geo_ctl1_w));
|
||||
map(0x00980014, 0x00980017).r(this, FUNC(model2c_state::copro_status_r));
|
||||
map(0x009c0000, 0x009cffff).rw(this, FUNC(model2c_state::model2_serial_r), FUNC(model2c_state::model2_serial_w));
|
||||
@ -1703,6 +1721,8 @@ void model2c_state::model2c_crx_mem(address_map &map)
|
||||
|
||||
map(0x01c00000, 0x01c0001f).r(this, FUNC(model2c_state::model2_crx_in_r)).umask32(0x00ff00ff);
|
||||
map(0x01c00000, 0x01c00003).w(this, FUNC(model2c_state::ctrl0_w));
|
||||
map(0x01c00008, 0x01c0000b).nopw();
|
||||
map(0x01c00010, 0x01c00013).nopw();
|
||||
map(0x01c00014, 0x01c00017).w(this, FUNC(model2c_state::hotd_lightgun_w));
|
||||
map(0x01c0001c, 0x01c0001f).w(this, FUNC(model2c_state::analog_2b_w));
|
||||
map(0x01c80000, 0x01c80003).rw(this, FUNC(model2c_state::model2_serial_r), FUNC(model2c_state::model2_serial_w));
|
||||
@ -2745,11 +2765,17 @@ MACHINE_CONFIG_START(model2b_state::rchase2)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
ADDRESS_MAP_START(model2_state::copro_tgpx4_map)
|
||||
AM_RANGE(0x00000000, 0x00007fff) AM_RAM AM_SHARE("tgpx4_program")
|
||||
// AM_RANGE(0x00400000, 0x007fffff) // bufferram
|
||||
// AM_RANGE(0x00800000, 0x00ffffff) // ROM data
|
||||
ADDRESS_MAP_END
|
||||
void model2c_state::copro_tgpx4_map(address_map &map)
|
||||
{
|
||||
map(0x00000000, 0x00007fff).ram().share("tgpx4_program");
|
||||
}
|
||||
|
||||
void model2c_state::copro_tgpx4_data_map(address_map &map)
|
||||
{
|
||||
// map(0x00000000, 0x000003ff) internal RAM
|
||||
map(0x00400000, 0x007fffff).rw(this, FUNC(model2_state::copro_tgp_buffer_r),FUNC(model2_state::copro_tgp_buffer_w)); // bufferram
|
||||
map(0x00800000, 0x008fffff).rom().region("copro_data",0); // ROM data
|
||||
}
|
||||
|
||||
/* 2C-CRX */
|
||||
MACHINE_CONFIG_START(model2c_state::model2c)
|
||||
@ -2759,6 +2785,7 @@ MACHINE_CONFIG_START(model2c_state::model2c)
|
||||
|
||||
MCFG_CPU_ADD("tgpx4", MB86235, 40000000)
|
||||
MCFG_CPU_PROGRAM_MAP(copro_tgpx4_map)
|
||||
MCFG_CPU_DATA_MAP(copro_tgpx4_data_map)
|
||||
|
||||
MCFG_MACHINE_START_OVERRIDE(model2_state,model2)
|
||||
MCFG_MACHINE_RESET_OVERRIDE(model2_state,model2c)
|
||||
@ -3980,7 +4007,7 @@ ROM_START( dynamcopc ) /* Dynamite Cop (USA), Model 2C */
|
||||
ROM_LOAD32_WORD("mpr-20791.4", 0x1800000, 0x400000, CRC(4883d0df) SHA1(b98af63e81f6c1b2766d7e96acbd1821bba000d4) ) /* Located at position 5 on 2C-CRX rom board */
|
||||
ROM_LOAD32_WORD("mpr-20792.5", 0x1800002, 0x400000, CRC(47becfa2) SHA1(a333885872a64b322f3cb464a70352d73654b1b3) ) /* Located at position 6 on 2C-CRX rom board */
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", ROMREGION_ERASE00 ) // TGPx4 program (COPRO sockets)
|
||||
ROM_REGION( 0x800000, "copro_data", ROMREGION_ERASE00 ) // TGPx4 program (COPRO sockets)
|
||||
|
||||
ROM_REGION( 0x2000000, "polygons", 0 ) // Models
|
||||
ROM_LOAD32_WORD("mpr-20799.16", 0x0000000, 0x400000, CRC(424571bf) SHA1(18a4e8d0e968fff3b645b59a0023b0ef38d51924) ) /* Located at position 17 on 2C-CRX rom board */
|
||||
@ -4137,7 +4164,7 @@ ROM_START( stcc ) /* Sega Touring Car Championship, Model 2C - Defaults to Japan
|
||||
ROM_COPY("main_data", 0x800000, 0xe00000, 0x100000)
|
||||
ROM_COPY("main_data", 0x800000, 0xf00000, 0x100000)
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("mpr-19255.29", 0x000000, 0x200000, CRC(d78bf030) SHA1(e6b3d8422613d22db50cf6c251f9a21356d96653) )
|
||||
ROM_LOAD32_WORD("mpr-19256.30", 0x000002, 0x200000, CRC(cb2b2d9e) SHA1(86b2b8bb6074352f72eb81e616093a1ba6f5163f) )
|
||||
|
||||
@ -4202,7 +4229,7 @@ ROM_START( stccb ) /* Sega Touring Car Championship Revision B, Model 2C - Defau
|
||||
ROM_COPY("main_data", 0x800000, 0xe00000, 0x100000)
|
||||
ROM_COPY("main_data", 0x800000, 0xf00000, 0x100000)
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("mpr-19255.29", 0x000000, 0x200000, CRC(d78bf030) SHA1(e6b3d8422613d22db50cf6c251f9a21356d96653) )
|
||||
ROM_LOAD32_WORD("mpr-19256.30", 0x000002, 0x200000, CRC(cb2b2d9e) SHA1(86b2b8bb6074352f72eb81e616093a1ba6f5163f) )
|
||||
|
||||
@ -4267,7 +4294,7 @@ ROM_START( stcca ) /* Sega Touring Car Championship Revision A, Model 2C - Defau
|
||||
ROM_COPY("main_data", 0x800000, 0xe00000, 0x100000)
|
||||
ROM_COPY("main_data", 0x800000, 0xf00000, 0x100000)
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("mpr-19255.29", 0x000000, 0x200000, CRC(d78bf030) SHA1(e6b3d8422613d22db50cf6c251f9a21356d96653) )
|
||||
ROM_LOAD32_WORD("mpr-19256.30", 0x000002, 0x200000, CRC(cb2b2d9e) SHA1(86b2b8bb6074352f72eb81e616093a1ba6f5163f) )
|
||||
|
||||
@ -4327,7 +4354,7 @@ ROM_START( skisuprg ) /* Sega Ski Super G, Model 2C, Sega Game ID# 833-12861, RO
|
||||
ROM_LOAD32_WORD( "mpr-19492.9", 0x800000, 0x400000, CRC(4805318f) SHA1(dbd1359817933313c6d74d3a1450682e8ce5857a) )
|
||||
ROM_LOAD32_WORD( "mpr-19493.10", 0x800002, 0x400000, CRC(39daa909) SHA1(e29e50c7fc39bd4945f993ceaa100358054efc5a) )
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD( "mpr-19502.29", 0x000000, 0x400000, CRC(2212d8d6) SHA1(3b8a4da2dc00a1eac41b48cbdc322ea1c31b8b29) )
|
||||
ROM_LOAD32_WORD( "mpr-19503.30", 0x000002, 0x400000, CRC(3c9cfc73) SHA1(2213485a00cef0bcef11b67f00027c4159c5e2f5) )
|
||||
|
||||
@ -4372,7 +4399,7 @@ ROM_START( segawski ) /* Sega Water Ski Revision A, Model 2C, Sega Game ID# 833-
|
||||
ROM_COPY( "main_data", 0x1800000, 0x1e00000, 0x100000 )
|
||||
ROM_COPY( "main_data", 0x1800000, 0x1f00000, 0x100000 )
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("mpr-19986.29", 0x0000000, 0x400000, CRC(4b8e26f8) SHA1(859e3788c75599295a8b57ed7852f2cbb6a2a738) )
|
||||
ROM_LOAD32_WORD("mpr-19987.30", 0x0000002, 0x400000, CRC(8d5b9d38) SHA1(35f41c474af3754152aecefe81e912120823e0ff) )
|
||||
|
||||
@ -4425,7 +4452,7 @@ ROM_START( hotd ) /* House of the Dead, Model 2C, Sega Game ID# 610-0396-13054,
|
||||
ROM_COPY( "main_data", 0x1800000, 0x1f00000, 0x100000 )
|
||||
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("epr-19707.29", 0x000000, 0x080000, CRC(384fd133) SHA1(6d060378d0f801b04d12e7ee874f2fa0572992d9) )
|
||||
ROM_LOAD32_WORD("epr-19706.30", 0x000002, 0x080000, CRC(1277531c) SHA1(08d3e733ba9989fcd32290634171c73f26ab6e2b) )
|
||||
|
||||
@ -4974,7 +5001,7 @@ ROM_START( bel ) /* Behind Enemy Lines, Model 2C */
|
||||
ROM_LOAD32_WORD("mpr-20227.5", 0xc00000, 0x200000, CRC(1277686e) SHA1(fff27006659458300001425261b944e690f1d494) )
|
||||
ROM_LOAD32_WORD("mpr-20228.6", 0xc00002, 0x200000, CRC(49cb5568) SHA1(ee3273302830f3499c7d4e548b629c51e0369e8a) )
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("mpr-20236.29", 0x000000, 0x200000, CRC(8de9a3c2) SHA1(e7fde1fd509531e1002ff813163067dc0d134536) )
|
||||
ROM_LOAD32_WORD("mpr-20235.30", 0x000002, 0x200000, CRC(78fa11ef) SHA1(a60deabb662e9c09f5d6342dc1a1c6045744d93f) )
|
||||
|
||||
@ -5015,7 +5042,7 @@ ROM_START( overrev ) /* Over Rev Revision A, Model 2C */
|
||||
ROM_LOAD32_WORD( "mpr-19994.9", 0x800000, 0x400000, CRC(e691fbd5) SHA1(b99c2f3f2a682966d792917dfcb8ed8e53bc0b7a) )
|
||||
ROM_LOAD32_WORD( "mpr-19995.10", 0x800002, 0x400000, CRC(82a7828e) SHA1(4336a12a07a67f94091b4a9b491bab02c375dd15) )
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", ROMREGION_ERASE00 ) // TGPx4 program (COPRO sockets)
|
||||
ROM_REGION( 0x800000, "copro_data", ROMREGION_ERASE00 ) // TGPx4 program (COPRO sockets)
|
||||
|
||||
ROM_REGION( 0x800000, "polygons", 0 ) // Models (TGP sockets)
|
||||
ROM_LOAD32_WORD( "mpr-19998.17", 0x000000, 0x200000, CRC(6a834574) SHA1(8be19bf42dbb157d6acde62a2018ef4c0d41aab4) )
|
||||
@ -5075,7 +5102,7 @@ ROM_START( rascot2 ) /* Royal Ascot 2, Model 2C, Rom Board : 837-12485 Com Board
|
||||
ROM_LOAD32_WORD("mpr-20169.9", 0x800000, 0x400000, CRC(b5be4d6b) SHA1(cfb4696506efa0e93fab35bbeb87decd83aec040) )
|
||||
ROM_LOAD32_WORD("mpr-20170.10", 0x800002, 0x400000, CRC(7b05cf33) SHA1(9e392ea0c7a9f4cef76d46ad92a7cf814022c133) )
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", ROMREGION_ERASE00) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", ROMREGION_ERASE00) // TGPx4 program
|
||||
|
||||
ROM_REGION( 0x2000000, "polygons", 0 ) // Models
|
||||
ROM_LOAD32_WORD("mpr-20173.17", 0x0000000, 0x400000, CRC(60bd684e) SHA1(893985808adb88fb54f0ca85ca23995d65360360) )
|
||||
@ -5111,7 +5138,7 @@ ROM_START( topskatr ) /* Top Skater Revision A (Export), Model 2C, Sega Game ID#
|
||||
ROM_LOAD32_WORD("mpr-19737.9", 0x800000, 0x400000, CRC(281a7dde) SHA1(71d5ba434328a81969bfdc71ac1160c5ff3ae9d3) )
|
||||
ROM_LOAD32_WORD("mpr-19738.10", 0x800002, 0x400000, CRC(f688327e) SHA1(68c9db242ef7e8f98979e968a09e4b093bc5d470) )
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("mpr-19743.29", 0x000000, 0x200000, CRC(d41a41bf) SHA1(a5f6b24e6526d0d2ef9c526c273c018d1e0fed59) )
|
||||
ROM_LOAD32_WORD("mpr-19744.30", 0x000002, 0x200000, CRC(84f203bf) SHA1(4952b764e6bf6cd735018738c5eff08781ee2315) )
|
||||
|
||||
@ -5151,7 +5178,7 @@ ROM_START( topskatruo ) /* Top Skater (USA), Model 2C, Sega Game ID# 833-13080-0
|
||||
ROM_LOAD32_WORD("mpr-19737.9", 0x800000, 0x400000, CRC(281a7dde) SHA1(71d5ba434328a81969bfdc71ac1160c5ff3ae9d3) )
|
||||
ROM_LOAD32_WORD("mpr-19738.10", 0x800002, 0x400000, CRC(f688327e) SHA1(68c9db242ef7e8f98979e968a09e4b093bc5d470) )
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("mpr-19743.29", 0x000000, 0x200000, CRC(d41a41bf) SHA1(a5f6b24e6526d0d2ef9c526c273c018d1e0fed59) )
|
||||
ROM_LOAD32_WORD("mpr-19744.30", 0x000002, 0x200000, CRC(84f203bf) SHA1(4952b764e6bf6cd735018738c5eff08781ee2315) )
|
||||
|
||||
@ -5191,7 +5218,7 @@ ROM_START( topskatru ) /* Top Skater Revision A (USA), Model 2C, Sega Game ID# 8
|
||||
ROM_LOAD32_WORD("mpr-19737.9", 0x800000, 0x400000, CRC(281a7dde) SHA1(71d5ba434328a81969bfdc71ac1160c5ff3ae9d3) )
|
||||
ROM_LOAD32_WORD("mpr-19738.10", 0x800002, 0x400000, CRC(f688327e) SHA1(68c9db242ef7e8f98979e968a09e4b093bc5d470) )
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("mpr-19743.29", 0x000000, 0x200000, CRC(d41a41bf) SHA1(a5f6b24e6526d0d2ef9c526c273c018d1e0fed59) )
|
||||
ROM_LOAD32_WORD("mpr-19744.30", 0x000002, 0x200000, CRC(84f203bf) SHA1(4952b764e6bf6cd735018738c5eff08781ee2315) )
|
||||
|
||||
@ -5231,7 +5258,7 @@ ROM_START( topskatrj ) /* Top Skater (Japan), Model 2C, Sega Game ID# 833-13080-
|
||||
ROM_LOAD32_WORD("mpr-19737.9", 0x800000, 0x400000, CRC(281a7dde) SHA1(71d5ba434328a81969bfdc71ac1160c5ff3ae9d3) )
|
||||
ROM_LOAD32_WORD("mpr-19738.10", 0x800002, 0x400000, CRC(f688327e) SHA1(68c9db242ef7e8f98979e968a09e4b093bc5d470) )
|
||||
|
||||
ROM_REGION( 0x800000, "cpu2", 0 ) // TGPx4 program
|
||||
ROM_REGION( 0x800000, "copro_data", 0 ) // TGPx4 program
|
||||
ROM_LOAD32_WORD("mpr-19743.29", 0x000000, 0x200000, CRC(d41a41bf) SHA1(a5f6b24e6526d0d2ef9c526c273c018d1e0fed59) )
|
||||
ROM_LOAD32_WORD("mpr-19744.30", 0x000002, 0x200000, CRC(84f203bf) SHA1(4952b764e6bf6cd735018738c5eff08781ee2315) )
|
||||
|
||||
|
||||
@ -141,7 +141,7 @@ public:
|
||||
DECLARE_WRITE16_MEMBER(colorxlat_w);
|
||||
DECLARE_WRITE32_MEMBER(ctrl0_w);
|
||||
DECLARE_WRITE32_MEMBER(analog_2b_w);
|
||||
DECLARE_READ32_MEMBER(fifoctl_r);
|
||||
DECLARE_READ32_MEMBER(fifo_control_2a_r);
|
||||
DECLARE_READ32_MEMBER(videoctl_r);
|
||||
DECLARE_WRITE32_MEMBER(videoctl_w);
|
||||
DECLARE_WRITE32_MEMBER(rchase2_devices_w);
|
||||
@ -248,7 +248,6 @@ public:
|
||||
void sj25_0207_01(machine_config &config);
|
||||
void copro_sharc_map(address_map &map);
|
||||
void copro_tgp_map(address_map &map);
|
||||
void copro_tgpx4_map(address_map &map);
|
||||
void drive_io_map(address_map &map);
|
||||
void drive_map(address_map &map);
|
||||
void geo_sharc_map(address_map &map);
|
||||
@ -345,7 +344,7 @@ public:
|
||||
|
||||
DECLARE_READ32_MEMBER(daytona_unk_r);
|
||||
DECLARE_READ8_MEMBER(model2o_in_r);
|
||||
DECLARE_READ32_MEMBER(fifoctrl_r);
|
||||
DECLARE_READ32_MEMBER(fifo_control_2o_r);
|
||||
|
||||
void daytona(machine_config &config);
|
||||
void model2o(machine_config &config);
|
||||
@ -455,12 +454,16 @@ public:
|
||||
: model2_state(mconfig, type, tag)
|
||||
{}
|
||||
|
||||
DECLARE_READ32_MEMBER(fifo_control_2c_r);
|
||||
|
||||
void model2c(machine_config &config);
|
||||
void model2c_5881(machine_config &config);
|
||||
void overrev2c(machine_config &config);
|
||||
void stcc(machine_config &config);
|
||||
void model2c_crx_mem(address_map &map);
|
||||
void model2c_5881_mem(address_map &map);
|
||||
void copro_tgpx4_map(address_map &map);
|
||||
void copro_tgpx4_data_map(address_map &map);
|
||||
};
|
||||
|
||||
/*****************************
|
||||
|
||||
Loading…
Reference in New Issue
Block a user