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remove unnecessary acrobatics (nw)

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This commit is contained in:
smf- 2018-04-13 09:00:21 +01:00
parent 8e315058d0
commit 3376e628e1
5 changed files with 15 additions and 15 deletions
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10
src/mame/drivers/bublbobl.cpp
View File

@ -840,8 +840,8 @@ MACHINE_START_MEMBER(bublbobl_state,tokio)
MACHINE_RESET_MEMBER(bublbobl_state,tokio)
{
MACHINE_RESET_CALL_MEMBER(common);
tokio_bankswitch_w(m_maincpu->device_t::memory().space(AS_PROGRAM), 0, 0x00, 0xFF); // force a bankswitch write of all zeroes, as /RESET clears the latch
tokio_videoctrl_w(m_maincpu->device_t::memory().space(AS_PROGRAM), 0, 0x00, 0xFF); // TODO: does /RESET clear this the same as above? probably yes, needs tracing...
tokio_bankswitch_w(m_maincpu->space(AS_PROGRAM), 0, 0x00, 0xFF); // force a bankswitch write of all zeroes, as /RESET clears the latch
tokio_videoctrl_w(m_maincpu->space(AS_PROGRAM), 0, 0x00, 0xFF); // TODO: does /RESET clear this the same as above? probably yes, needs tracing...
}
MACHINE_CONFIG_START(bublbobl_state::tokio)
@ -944,7 +944,7 @@ MACHINE_START_MEMBER(bublbobl_state,bublbobl)
MACHINE_RESET_MEMBER(bublbobl_state,bublbobl)
{
MACHINE_RESET_CALL_MEMBER(common);
bublbobl_bankswitch_w(m_maincpu->device_t::memory().space(AS_PROGRAM), 0, 0x00, 0xFF); // force a bankswitch write of all zeroes, as /RESET clears the latch
bublbobl_bankswitch_w(m_maincpu->space(AS_PROGRAM), 0, 0x00, 0xFF); // force a bankswitch write of all zeroes, as /RESET clears the latch
m_ddr1 = 0;
m_ddr2 = 0;
@ -1035,7 +1035,7 @@ MACHINE_START_MEMBER(bublbobl_state,boblbobl)
MACHINE_RESET_MEMBER(bublbobl_state,boblbobl)
{
MACHINE_RESET_CALL_MEMBER(common);
bublbobl_bankswitch_w(m_maincpu->device_t::memory().space(AS_PROGRAM), 0, 0x00, 0xff); // force a bankswitch write of all zeroes, as /RESET clears the latch
bublbobl_bankswitch_w(m_maincpu->space(AS_PROGRAM), 0, 0x00, 0xff); // force a bankswitch write of all zeroes, as /RESET clears the latch
m_ic43_a = 0;
m_ic43_b = 0;
@ -1070,7 +1070,7 @@ MACHINE_START_MEMBER(bub68705_state, bub68705)
MACHINE_RESET_MEMBER(bub68705_state, bub68705)
{
MACHINE_RESET_CALL_MEMBER(common);
bublbobl_bankswitch_w(m_maincpu->device_t::memory().space(AS_PROGRAM), 0, 0x00, 0xff); // force a bankswitch write of all zeroes, as /RESET clears the latch
bublbobl_bankswitch_w(m_maincpu->space(AS_PROGRAM), 0, 0x00, 0xff); // force a bankswitch write of all zeroes, as /RESET clears the latch
m_address = 0;
m_latch = 0;

2
src/mame/drivers/missb2.cpp
View File

@ -458,7 +458,7 @@ MACHINE_RESET_MEMBER(missb2_state,missb2)
{
MACHINE_RESET_CALL_MEMBER(common);
m_oki->reset();
bublbobl_bankswitch_w(m_maincpu->device_t::memory().space(AS_PROGRAM), 0, 0x00, 0xFF); // force a bankswitch write of all zeroes, as /RESET clears the latch
bublbobl_bankswitch_w(m_maincpu->space(AS_PROGRAM), 0, 0x00, 0xFF); // force a bankswitch write of all zeroes, as /RESET clears the latch
}
MACHINE_CONFIG_START(missb2_state::missb2)

6
src/mame/drivers/ngen.cpp
View File

@ -255,13 +255,13 @@ WRITE16_MEMBER(ngen_state::cpu_peripheral_cb)
addr = (m_peripheral & 0xffc0) << 4;
if(m_middle & 0x0040)
{
m_maincpu->device_t::memory().space(AS_PROGRAM).install_readwrite_handler(addr, addr + 0x3ff, read16_delegate(FUNC(ngen_state::peripheral_r), this), write16_delegate(FUNC(ngen_state::peripheral_w), this));
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(addr, addr + 0x3ff, read16_delegate(FUNC(ngen_state::peripheral_r), this), write16_delegate(FUNC(ngen_state::peripheral_w), this));
logerror("Mapped peripherals to memory 0x%08x\n",addr);
}
else
{
addr &= 0xffff;
m_maincpu->device_t::memory().space(AS_IO).install_readwrite_handler(addr, addr + 0x3ff, read16_delegate(FUNC(ngen_state::peripheral_r), this), write16_delegate(FUNC(ngen_state::peripheral_w), this));
m_maincpu->space(AS_IO).install_readwrite_handler(addr, addr + 0x3ff, read16_delegate(FUNC(ngen_state::peripheral_r), this), write16_delegate(FUNC(ngen_state::peripheral_w), this));
logerror("Mapped peripherals to I/O 0x%04x\n",addr);
}
break;
@ -439,7 +439,7 @@ WRITE16_MEMBER(ngen_state::xbus_w)
cpu = m_maincpu;
else
cpu = m_i386cpu;
address_space& io = cpu->device_t::memory().space(AS_IO);
address_space& io = cpu->space(AS_IO);
switch(m_xbus_current)
{
case 0x00: // Floppy/Hard disk module

6
src/mame/drivers/notetaker.cpp
View File

@ -765,14 +765,14 @@ void notetaker_state::iop_reset()
m_eiauart->write_xr(0); // MR - pin 21
m_eiauart->write_xr(1); // ''
// reset the IPConReg ls273 latch at #f1
IPConReg_w(m_iop_cpu->device_t::memory().space(AS_PROGRAM), 0, 0x0000, 0xffff);
IPConReg_w(m_iop_cpu->space(AS_PROGRAM), 0, 0x0000, 0xffff);
// Clear the DAC FIFO
for (int i=0; i<16; i++) m_outfifo[i] = 0;
m_outfifo_count = m_outfifo_tail_ptr = m_outfifo_head_ptr = 0;
// reset the FIFOReg latch at #h9
FIFOReg_w(m_iop_cpu->device_t::memory().space(AS_PROGRAM), 0, 0x0000, 0xffff);
FIFOReg_w(m_iop_cpu->space(AS_PROGRAM), 0, 0x0000, 0xffff);
// reset the DiskReg latches at #c4 and #b4 on the disk/display/eia controller board
DiskReg_w(m_iop_cpu->device_t::memory().space(AS_PROGRAM), 0, 0x0000, 0xffff);
DiskReg_w(m_iop_cpu->space(AS_PROGRAM), 0, 0x0000, 0xffff);
// reset the framebuffer display address counter:
m_DispAddr = 0;
}

6
src/mame/drivers/superqix.cpp
View File

@ -291,7 +291,7 @@ TIMER_CALLBACK_MEMBER(superqix_state::mcu_port3_w_cb)
TIMER_CALLBACK_MEMBER(superqix_state::z80_ay1_sync_address_w_cb)
{
m_ay1->address_w(m_maincpu->device_t::memory().space(AS_PROGRAM), 0, param, 0xff);
m_ay1->address_w(m_maincpu->space(AS_PROGRAM), 0, param, 0xff);
}
@ -357,7 +357,7 @@ TIMER_CALLBACK_MEMBER(superqix_state::bootleg_mcu_port1_w_cb)
//already after a synchronize, and doing another one would be redundant
}
mcu_port2_w(m_mcu->device_t::memory().space(AS_PROGRAM), 0, m_bl_fake_port2, 0xff); // finally write to port 2, which will do another synchronize
mcu_port2_w(m_mcu->space(AS_PROGRAM), 0, m_bl_fake_port2, 0xff); // finally write to port 2, which will do another synchronize
}
WRITE8_MEMBER(superqix_state::bootleg_mcu_port1_w)
@ -957,7 +957,7 @@ MACHINE_RESET_MEMBER(superqix_state, superqix)
// the act of clearing this latch asserts the z80 reset, and the mcu must clear it itself by writing
// to the p2 latch with bit 5 set.
m_port2_raw = 0x01; // force the following function into latching a zero write by having bit 0 falling edge
mcu_port2_w(m_mcu->device_t::memory().space(AS_PROGRAM), 0, 0x00, 0xff);
mcu_port2_w(m_mcu->space(AS_PROGRAM), 0, 0x00, 0xff);
m_mcu->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
}
}