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https://github.com/holub/mame
synced 2025-04-22 08:22:15 +03:00
Compiles but produces printouts only when used from fccpu1 driver for needed registers only
This commit is contained in:
Joakim Larsson Edström
parent
27d9db1811
commit
338f3b1435
@ -4,41 +4,30 @@
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Motorola MC68230 PI/T Parallell Interface and Timer
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Revisions
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2015-07-15 JLE initial
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Todo
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- Add clock and timers
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- Add all missing registers
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- Add configuration
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**********************************************************************/
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/*
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Registers
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-----------------------------------------------------------------------
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Offset Reset R/W
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RS1-RS5 Name Value Reset Description
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-----------------------------------------------------------------------
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0x00 RW PGCR No Port General Control register
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0x01 RW PSRR No Port Service Request register
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0x02 RW PADDR No Port A Data Direction register
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0x03 RW PBDDR No Port B Data Direction register
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0x04 RW PCDDR No Port C Data Direction register
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0x05 RW PIVR No Port Interrupt vector register
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0x06 RW PACR No Port A Control register
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0x07 RW PBCR No Port B Control register
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0x08 RW PADR May Port A Data register
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0x09 RW PBDR May Port B Data register
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0x0a RO PAAR No Port A Alternate register
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0x0b RO PBAR No Port B Alternate register
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0x0c RW PCDR No Port C Data register
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0x0d RW PSR May Port Status register
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0x0e n/a
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0x0f n/a
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0x10 RW TCR No Timer Control Register
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0x11 RW TIVR No Timer Interrupt Vector Register
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0x12 n/a
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0x13 RW CPRH No Counter Preload Register High
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0x14 RW CPRM No Counter Preload Register Middle
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0x15 RW CPRL No Counter Preload Register Low
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0x17 RO CNTRH No Counter Register High
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0x18 RO CNTRM No Counter Register Middle
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0x19 RO CNTRL No Counter Register Low
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0x1A RW TSR May Timer Status Register
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Force CPU-1 init sequence
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0801EA 0E0000 W 0000 PGCR data_w: 0000 -> 0000 & 00ff
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0801EA 0E0002 W 0000 PSRR data_w: 0000 -> 0001 & 00ff
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0801EA 0E0004 W FFFF PADDR data_w: 00ff -> 0002 & 00ff
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0801EA 0E0006 W 0000 PBDDR data_w: 0000 -> 0003 & 00ff
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0801F0 0E000C W 6060 PACR data_w: 0060 -> 0006 & 00ff
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0801F6 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff
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0801FC 0E0000 W 3030 PGCR data_w: 0030 -> 0000 & 00ff
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080202 0E000E W A8A8 PBCR data_w: 00a8 -> 0007 & 00ff
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080210 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff
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Force CPU-1 after one keypress in terminal
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081DC0 0E000C W 6868 PACR
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081DC8 0E000C W 6060 PACR
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*/
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@ -57,55 +46,66 @@ const device_type PIT68230 = &device_creator<pit68230_device>;
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//-------------------------------------------------
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pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, PIT68230, "68230 PI/T", tag, owner, clock, "pit68230", __FILE__),
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m_internal_clock(0.0),
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m_out0_cb(*this),
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m_out1_cb(*this),
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m_out2_cb(*this),
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m_irq_cb(*this)
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: device_t(mconfig, PIT68230, "Motorola 68230 PI/T", tag, owner, clock, "pit68230", __FILE__),
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m_internal_clock(0.0)
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{
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m_external_clock = 0.0;
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}
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//-------------------------------------------------
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// tick
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//-------------------------------------------------
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void ptm6840_device::tick(int counter, int count)
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void pit68230_device::device_start()
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{
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if (counter == 2)
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{
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m_t3_scaler += count;
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printf("PIT68230 device started\n");
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}
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if ( m_t3_scaler > m_t3_divisor - 1)
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{
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subtract_from_counter(counter, 1);
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m_t3_scaler = 0;
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}
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}
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else
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{
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subtract_from_counter(counter, count);
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}
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void pit68230_device::device_reset()
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{
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printf("PIT68230 device reseted\n");
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m_pgcr = 0;
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m_psrr = 0;
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m_paddr = 0;
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m_pbddr = 0;
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m_pacr = 0;
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m_pbcr = 0;
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}
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WRITE8_MEMBER( pit68230_device::data_w )
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{
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printf("data_w: %04x -> ", data);
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switch (offset)
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{
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case PIT_68230_PGCR:
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printf("PGCR");
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m_pgcr = data;
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break;
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case PIT_68230_PSRR:
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printf("PSRR");
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m_psrr = data;
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break;
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case PIT_68230_PADDR:
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printf("PADDR");
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m_paddr = data;
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break;
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case PIT_68230_PBDDR:
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printf("PBDDR");
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m_pbddr = data;
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break;
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case PIT_68230_PACR:
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printf("PACR");
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m_pacr = data;
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break;
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case PIT_68230_PBCR:
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printf("PBCR");
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m_pbcr = data;
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break;
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default:
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printf("unhandled register %02x", offset);
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}
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printf("\n");
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}
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READ8_MEMBER( pit68230_device::data_r )
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{
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printf("data_r: %04x & %04x\n", offset, mem_mask);
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return (UINT8) 0;
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}
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//-------------------------------------------------
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// set_clock - set clock status (0 or 1)
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//-------------------------------------------------
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void ptm6840_device::set_clock(int idx, int state)
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{
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m_clk[idx] = state;
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if (!(m_control_reg[idx] & 0x02))
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{
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if (state)
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{
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tick(idx, 1);
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}
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}
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}
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WRITE_LINE_MEMBER( pit68230_device::set_c1 ) { set_clock(state); }
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@ -7,143 +7,66 @@
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**********************************************************************/
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#pragma once
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#ifndef __68230PTI_H__
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#define __68230PTI_H__
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#ifndef __68230PIT_H__
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#define __68230PIT_H__
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#include "emu.h"
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#define PIT_68230_PGCR 0x00 /* Port General Control register */
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#define PIT_68230_PSRR 0x01 /* Port Service Request register */
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#define PIT_68230_PADDR 0x02 /* Port A Data Direction register */
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#define PIT_68230_PBDDR 0x03 /* Port B Data Direction register */
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#define PIT_68230_PCDDR 0x04 /* Port C Data Direction register */
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#define PIT_68230_PIVR 0x05 /* Port Interrupt vector register */
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#define PIT_68230_PACR 0x06 /* Port A Control register */
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#define PIT_68230_PBCR 0x07 /* Port B Control register */
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#define PIT_68230_PADR 0x08 /* Port A Data register */
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#define PIT_68230_PBDR 0x09 /* Port B Data register */
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#define PIT_68230_PAAR 0x0a /* Port A Alternate register */
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#define PIT_68230_PBAR 0x0b /* Port B Alternate register */
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#define PIT_68230_PCDR 0x0c /* Port C Data register */
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#define PIT_68230_PSR 0x0d /* Port Status register */
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#define PIT_68230_TCR 0x10 /* Timer Control Register */
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#define PIT_68230_TIVR 0x11 /* Timer Interrupt Vector Register */
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#define PIT_68230_CPRH 0x13 /* Counter Preload Register High */
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#define PIT_68230_CPRM 0x14 /* Counter Preload Register Middle */
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#define PIT_68230_CPRL 0x15 /* Counter Preload Register Low */
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#define PIT_68230_CNTRH 0x17 /* Counter Register High */
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#define PIT_68230_CNTRM 0x18 /* Counter Register Middle */
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#define PIT_68230_CNTRL 0x19 /* Counter Register Low */
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#define PIT_68230_TSR 0x1A /* Timer Status Register */
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/*-----------------------------------------------------------------------
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Registers RS1-RS5 R/W Description
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-------------------------------------------------------------------------*/
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#define PIT_68230_PGCR 0x00 /* RW Port General Control register */
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#define PIT_68230_PSRR 0x01 /* RW Port Service Request register */
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#define PIT_68230_PADDR 0x02 /* RW Port A Data Direction register */
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#define PIT_68230_PBDDR 0x03 /* RW Port B Data Direction register */
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#define PIT_68230_PCDDR 0x04 /* RW Port C Data Direction register */
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#define PIT_68230_PIVR 0x05 /* RW Port Interrupt vector register */
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#define PIT_68230_PACR 0x06 /* RW Port A Control register */
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#define PIT_68230_PBCR 0x07 /* RW Port B Control register */
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#define PIT_68230_PADR 0x08 /* RW Port A Data register */
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#define PIT_68230_PBDR 0x09 /* RW Port B Data register */
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#define PIT_68230_PAAR 0x0a /* RO Port A Alternate register */
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#define PIT_68230_PBAR 0x0b /* RO Port B Alternate register */
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#define PIT_68230_PCDR 0x0c /* RW Port C Data register */
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#define PIT_68230_PSR 0x0d /* RW Port Status register */
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#define PIT_68230_TCR 0x10 /* RW Timer Control Register */
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#define PIT_68230_TIVR 0x11 /* RW Timer Interrupt Vector Register */
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#define PIT_68230_CPRH 0x13 /* RW Counter Preload Register High */
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#define PIT_68230_CPRM 0x14 /* RW Counter Preload Register Middle */
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#define PIT_68230_CPRL 0x15 /* RW Counter Preload Register Low */
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#define PIT_68230_CNTRH 0x17 /* RO Counter Register High */
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#define PIT_68230_CNTRM 0x18 /* RO Counter Register Middle */
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#define PIT_68230_CNTRL 0x19 /* RO Counter Register Low */
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#define PIT_68230_TSR 0x1A /* RW Timer Status Register */
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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// ======================> pit68230_device
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class pit68230_device : public device_t
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{
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public:
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// construction/destruction
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pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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static void set_internal_clock(device_t &device, double clock) { downcast<pit68230_device &>(device).m_internal_clock = clock; }
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static void set_external_clock(device_t &device, double clock) { downcast<pit68230_device &>(device).m_external_clock = clock; }
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template<class _Object> static devcb_base &set_out0_callback(device_t &device, _Object object) { return downcast<pit68230_device &>(device).m_out0_cb.set_callback(object); }
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template<class _Object> static devcb_base &set_out1_callback(device_t &device, _Object object) { return downcast<pit68230_device &>(device).m_out1_cb.set_callback(object); }
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template<class _Object> static devcb_base &set_out2_callback(device_t &device, _Object object) { return downcast<pit68230_device &>(device).m_out2_cb.set_callback(object); }
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template<class _Object> static devcb_base &set_irq_callback(device_t &device, _Object object) { return downcast<pit68230_device &>(device).m_irq_cb.set_callback(object); }
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int status(int clock) const { return m_enabled[clock]; } // get whether timer is enabled
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int irq_state() const { return m_IRQ; } // get IRQ state
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UINT16 count(int counter) const { return compute_counter(counter); } // get counter value
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void set_ext_clock(int counter, double clock); // set clock frequency
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int ext_clock(int counter) const { return m_external_clock[counter]; } // get clock frequency
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DECLARE_WRITE8_MEMBER( write );
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void write(offs_t offset, UINT8 data) { write(machine().driver_data()->generic_space(), offset, data); }
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DECLARE_READ8_MEMBER( read );
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UINT8 read(offs_t offset) { return read(machine().driver_data()->generic_space(), offset); }
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void set_gate(int idx, int state);
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DECLARE_WRITE_LINE_MEMBER( set_g1 );
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DECLARE_WRITE_LINE_MEMBER( set_g2 );
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DECLARE_WRITE_LINE_MEMBER( set_g3 );
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void set_clock(int idx, int state);
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DECLARE_WRITE_LINE_MEMBER( set_c1 );
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DECLARE_WRITE_LINE_MEMBER( set_c2 );
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DECLARE_WRITE_LINE_MEMBER( set_c3 );
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void update_interrupts();
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DECLARE_WRITE8_MEMBER( data_w );
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DECLARE_READ8_MEMBER( data_r );
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
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private:
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void subtract_from_counter(int counter, int count);
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void tick(int counter, int count);
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void timeout(int idx);
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UINT16 compute_counter(int counter) const;
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void reload_count(int idx);
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/*
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enum
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{
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PTM_6840_CTRL1 = 0,
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PTM_6840_CTRL2 = 1,
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PTM_6840_STATUS = 1,
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PTM_6840_MSBBUF1 = 2,
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PTM_6840_LSB1 = 3,
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PTM_6840_MSBBUF2 = 4,
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PTM_6840_LSB2 = 5,
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PTM_6840_MSBBUF3 = 6,
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PTM_6840_LSB3 = 7,
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};
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*/
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double m_internal_clock;
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double m_external_clock[3];
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devcb_write8 m_out0_cb;
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devcb_write8 m_out1_cb;
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devcb_write8 m_out2_cb;
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devcb_write_line m_irq_cb; // function called if IRQ line changes
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UINT8 m_control_reg[3];
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UINT8 m_output[3]; // Output states
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UINT8 m_gate[3]; // Input gate states
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UINT8 m_clk; // Clock states
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UINT8 m_enabled[3];
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UINT8 m_mode[3];
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UINT8 m_fired[3];
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UINT8 m_t3_divisor;
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UINT8 m_t3_scaler;
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UINT8 m_IRQ;
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UINT8 m_status_reg;
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UINT8 m_status_read_since_int;
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UINT8 m_lsb_buffer;
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UINT8 m_msb_buffer;
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// Each PTM has 3 timers
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emu_timer *m_timer[3];
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UINT16 m_latch[3];
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UINT16 m_counter[3];
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static const char *const opmode[];
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UINT8 m_pgcr; // Port General Control register
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UINT8 m_psrr; // Port Service Request register
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UINT8 m_paddr; // Port A Data Direction register
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UINT8 m_pbddr; // Port B Data Direction register
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UINT8 m_pacr; // Port A Control register
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UINT8 m_pbcr; // Port B Control register
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};
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// device type definition
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extern const device_type PIT68230;
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#endif // __68230PTI__
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#endif // __68230PIT__
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