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https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
r4000: simplify branch state
This commit is contained in:
Patrick Mackinlay
parent
41a0233715
commit
33ac8ffd54
@ -281,7 +281,7 @@ std::unique_ptr<util::disasm_interface> r4000_base_device::create_disassembler()
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void r4000_base_device::execute_run()
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{
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while (m_icount-- > 0)
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while (m_icount > 0)
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{
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debugger_instruction_hook(m_pc);
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@ -298,35 +298,33 @@ void r4000_base_device::execute_run()
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m_r[0] = 0;
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});
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if (m_hilo_delay)
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m_hilo_delay--;
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// update pc and branch state
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switch (m_branch_state)
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switch (m_branch_state & STATE)
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{
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case NONE:
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m_pc += 4;
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break;
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case DELAY:
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m_branch_state = NONE;
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m_pc = m_branch_target;
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break;
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case BRANCH:
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m_branch_state = DELAY;
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m_pc += 4;
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m_pc = m_branch_state & TARGET;
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m_branch_state = NONE;
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break;
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case EXCEPTION:
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m_branch_state = NONE;
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case DELAY:
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m_pc += 4;
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m_branch_state = (m_branch_state & TARGET) | BRANCH;
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break;
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case NULLIFY:
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m_branch_state = NONE;
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m_pc += 8;
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m_branch_state = NONE;
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break;
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}
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if (m_hilo_delay)
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m_hilo_delay--;
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m_icount--;
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}
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}
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@ -366,12 +364,12 @@ void r4000_base_device::cpu_execute(u32 const op)
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m_r[RDREG] = s64(s32(m_r[RTREG]) >> (m_r[RSREG] & 31));
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break;
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case 0x08: // JR
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_r[RSREG], 0);
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// FIXME: address error if low bits are set
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m_branch_state = ADDR(m_r[RSREG], 0) | DELAY;
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break;
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case 0x09: // JALR
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_r[RSREG], 0);
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// FIXME: address error if low bits are set
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m_branch_state = ADDR(m_r[RSREG], 0) | DELAY;
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m_r[RDREG] = ADDR(m_pc, 8);
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break;
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//case 0x0a: // *
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@ -656,33 +654,21 @@ void r4000_base_device::cpu_execute(u32 const op)
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{
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case 0x00: // BLTZ
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if (s64(m_r[RSREG]) < 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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break;
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case 0x01: // BGEZ
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if (s64(m_r[RSREG]) >= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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break;
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case 0x02: // BLTZL
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if (s64(m_r[RSREG]) < 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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break;
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case 0x03: // BGEZL
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if (s64(m_r[RSREG]) >= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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break;
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@ -718,36 +704,24 @@ void r4000_base_device::cpu_execute(u32 const op)
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//case 0x0f: // *
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case 0x10: // BLTZAL
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if (s64(m_r[RSREG]) < 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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m_r[31] = ADDR(m_pc, 8);
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break;
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case 0x11: // BGEZAL
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if (s64(m_r[RSREG]) >= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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m_r[31] = ADDR(m_pc, 8);
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break;
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case 0x12: // BLTZALL
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if (s64(m_r[RSREG]) < 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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m_r[31] = ADDR(m_pc, 8);
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break;
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case 0x13: // BGEZALL
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if (s64(m_r[RSREG]) >= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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m_r[31] = ADDR(m_pc, 8);
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@ -774,41 +748,27 @@ void r4000_base_device::cpu_execute(u32 const op)
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}
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break;
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case 0x02: // J
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m_branch_state = BRANCH;
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m_branch_target = (ADDR(m_pc, 4) & ~0x0fffffffULL) | ((op & 0x03ffffffU) << 2);
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m_branch_state = (ADDR(m_pc, 4) & ~0x0fffffffULL) | ((op & 0x03ffffffU) << 2) | DELAY;
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break;
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case 0x03: // JAL
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m_branch_state = BRANCH;
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m_branch_target = (ADDR(m_pc, 4) & ~0x0fffffffULL) | ((op & 0x03ffffffU) << 2);
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m_branch_state = (ADDR(m_pc, 4) & ~0x0fffffffULL) | ((op & 0x03ffffffU) << 2) | DELAY;
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m_r[31] = ADDR(m_pc, 8);
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break;
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case 0x04: // BEQ
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if (m_r[RSREG] == m_r[RTREG])
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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break;
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case 0x05: // BNE
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if (m_r[RSREG] != m_r[RTREG])
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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break;
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case 0x06: // BLEZ
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if (s64(m_r[RSREG]) <= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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break;
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case 0x07: // BGTZ
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if (s64(m_r[RSREG]) > 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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break;
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case 0x08: // ADDI
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{
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@ -856,37 +816,25 @@ void r4000_base_device::cpu_execute(u32 const op)
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break;
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case 0x14: // BEQL
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if (m_r[RSREG] == m_r[RTREG])
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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break;
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case 0x15: // BNEL
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if (m_r[RSREG] != m_r[RTREG])
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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break;
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case 0x16: // BLEZL
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if (s64(m_r[RSREG]) <= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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break;
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case 0x17: // BGTZL
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if (s64(m_r[RSREG]) > 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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break;
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@ -1205,8 +1153,8 @@ void r4000_base_device::cpu_exception(u32 exception, u16 const vector)
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CAUSE = (CAUSE & CAUSE_IP) | exception;
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// if in a branch delay slot, restart at the branch instruction
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if (m_branch_state == DELAY)
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// if executing a delay slot instruction, restart from the branch
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if ((m_branch_state & STATE) == BRANCH)
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{
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m_cp0[CP0_EPC] -= 4;
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CAUSE |= CAUSE_BD;
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@ -1217,10 +1165,20 @@ void r4000_base_device::cpu_exception(u32 exception, u16 const vector)
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else
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CAUSE = (CAUSE & (CAUSE_BD | CAUSE_IP)) | exception;
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m_branch_state = EXCEPTION;
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m_pc = ((SR & SR_BEV) ? s64(s32(0xbfc00200)) : s64(s32(0x80000000))) + vector;
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m_branch_state = (((SR & SR_BEV) ? s64(s32(0xbfc00200)) : s64(s32(0x80000000))) + vector) | BRANCH;
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if (exception != EXCEPTION_INT)
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if (exception == EXCEPTION_INT)
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{
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if (machine().debug_flags & DEBUG_FLAG_ENABLED)
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{
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// notify the debugger of the first pending hardware interrupt
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u32 const iphw = CAUSE & SR & CAUSE_IPHW;
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if (iphw)
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debug()->interrupt_hook(22 - count_leading_zeros((iphw - 1) & ~iphw));
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}
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}
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else
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debugger_exception_hook(exception);
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}
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@ -1395,14 +1353,12 @@ void r4000_base_device::cp0_execute(u32 const op)
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case 0x18: // ERET
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if (SR & SR_ERL)
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{
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m_branch_state = EXCEPTION;
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m_pc = m_cp0[CP0_ErrorEPC];
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m_branch_state = m_cp0[CP0_ErrorEPC] | BRANCH;
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SR &= ~SR_ERL;
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}
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else
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{
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m_branch_state = EXCEPTION;
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m_pc = m_cp0[CP0_EPC];
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m_branch_state = m_cp0[CP0_EPC] | BRANCH;
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SR &= ~SR_EXL;
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}
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@ -2255,33 +2211,21 @@ void r4000_base_device::cp1_execute(u32 const op)
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{
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case 0x00: // BC1F
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if (!(m_fcr31 & FCR31_C))
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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break;
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case 0x01: // BC1T
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if (m_fcr31 & FCR31_C)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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break;
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case 0x02: // BC1FL
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if (!(m_fcr31 & FCR31_C))
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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break;
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case 0x03: // BC1TL
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if (m_fcr31 & FCR31_C)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_branch_state = ADDR(m_pc + 4, s32(s16(op)) << 2) | DELAY;
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else
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m_branch_state = NULLIFY;
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break;
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@ -3133,8 +3077,7 @@ void r4000_base_device::cp1_execute(u32 const op)
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break;
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case 0x3d: // SDC1
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if ((SR & SR_FR) || !(RTREG & 1))
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store<u64>(ADDR(m_r[RSREG], s16(op)), m_f[RTREG]);
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store<u64>(ADDR(m_r[RSREG], s16(op)), m_f[RTREG]);
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break;
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}
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}
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@ -368,7 +368,7 @@ protected:
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void cp2_execute(u32 const op);
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// address and memory handling
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enum translate_result { ERROR, MISS, UNCACHED, CACHED };
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enum translate_result : unsigned { ERROR, MISS, UNCACHED, CACHED };
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translate_result translate(int intention, u64 &address);
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void address_error(int intention, u64 const address);
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@ -400,6 +400,17 @@ protected:
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std::function<void(offs_t offset, u32 data, u32 mem_mask)> write_dword;
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std::function<void(offs_t offset, u64 data, u64 mem_mask)> write_qword;
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enum branch_state : u64
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{
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STATE = 0x00000000'00000003,
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TARGET = 0xffffffff'fffffffc,
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NONE = 0,
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BRANCH = 1, // retire delayed branch
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DELAY = 2, // delay slot instruction
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NULLIFY = 3, // next instruction nullified
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};
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// runtime state
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int m_icount;
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@ -412,16 +423,7 @@ protected:
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u64 m_r[32];
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u64 m_hi;
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u64 m_lo;
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enum branch_state : unsigned
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{
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NONE = 0,
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DELAY = 1, // delay slot instruction active
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BRANCH = 2, // branch instruction active
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EXCEPTION = 3, // exception triggered
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NULLIFY = 4, // next instruction nullified
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}
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m_branch_state;
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u64 m_branch_target;
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u64 m_branch_state;
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// cp0 state
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u64 m_cp0[32];
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