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https://github.com/holub/mame
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Merge pull request #3824 from DavidHaywood/030818_3
current hng64 / tlcs870 notes, tweaks etc.
This commit is contained in:
ajrhacker
GitHub
commit
33bb92a03a
@ -475,6 +475,8 @@ READ8_MEMBER(tlcs870_device::tbtcr_r)
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/* SIO emulation */
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// TODO: use templates for SIO1/2 ports, as they're the same except for the DBR region they use?
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// Serial Port 1
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WRITE8_MEMBER(tlcs870_device::sio1cr1_w)
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{
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@ -493,14 +495,40 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w)
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m_transfer_mode[0] = (m_SIOCR1[0] & 0x38) >> 3;
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switch (m_transfer_mode[0])
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{
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case 0x0: logerror("(Serial set to 8-bit transmit mode)\n"); break;
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case 0x1: logerror("(Serial set to invalid mode)\n"); break;
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case 0x2: logerror("(Serial set to 4-bit transmit mode)\n"); break;
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case 0x3: logerror("(Serial set to invalid mode)\n"); break;
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case 0x4: logerror("(Serial set to 8-bit transmit/receive mode)\n"); break;
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case 0x5: logerror("(Serial set to 8-bit receive mode)\n"); break;
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case 0x6: logerror("(Serial set to 4-bit receive mode)\n"); break;
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case 0x7: logerror("(Serial set to invalid mode)\n"); break;
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case 0x0:
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logerror("(Serial set to 8-bit transmit mode)\n");
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m_transmit_bits[0] = 8;
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m_receive_bits[0] = 0;
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break;
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case 0x2:
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logerror("(Serial set to 4-bit transmit mode)\n");
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m_transmit_bits[0] = 4;
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m_receive_bits[0] = 0;
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break;
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case 0x4:
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logerror("(Serial set to 8-bit transmit/receive mode)\n");
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m_transmit_bits[0] = 8;
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m_receive_bits[0] = 8;
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break;
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case 0x5: logerror("(Serial set to 8-bit receive mode)\n");
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m_transmit_bits[0] = 0;
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m_receive_bits[0] = 8;
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break;
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case 0x6:
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logerror("(Serial set to 4-bit receive mode)\n");
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m_transmit_bits[0] = 0;
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m_receive_bits[0] = 4;
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break;
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default:
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logerror("(Serial set to invalid mode)\n");
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m_transmit_bits[0] = 0;
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m_receive_bits[0] = 0;
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break;
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}
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if ((m_SIOCR1[0] & 0xc0) == 0x80)
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@ -510,7 +538,7 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w)
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m_transfer_shiftreg[0] = 0;
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m_transfer_pos[0] = 0;
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m_serial_transmit_timer[0]->adjust(attotime::zero);
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m_serial_transmit_timer[0]->adjust(attotime::zero);
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}
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}
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@ -547,39 +575,42 @@ READ8_MEMBER(tlcs870_device::sio1sr_r)
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TIMER_CALLBACK_MEMBER(tlcs870_device::sio0_transmit_cb)
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{
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int finish = 0;
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if (m_transfer_shiftpos[0] == 0)
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if (m_transmit_bits[0]) // TODO: handle receive cases
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{
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m_transfer_shiftreg[0] = m_dbr[m_transfer_pos[0]];
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logerror("transmitting byte %02x\n", m_transfer_shiftreg[0]);
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}
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int dataout = m_transfer_shiftreg[0] & 0x01;
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m_serial_out_cb[0](dataout);
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m_transfer_shiftreg[0] >>= 1;
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m_transfer_shiftpos[0]++;
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if (m_transfer_shiftpos[0] == 8)
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{
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logerror("transmitted\n");
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m_transfer_shiftpos[0] = 0;
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m_transfer_pos[0]++;
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if (m_transfer_pos[0] > m_transfer_numbytes[0])
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int finish = 0;
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if (m_transfer_shiftpos[0] == 0)
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{
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logerror("end of transmission\n");
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m_SIOCR1[0] &= ~0x80;
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// set interrupt latch
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m_IL |= 1 << (15-TLCS870_IRQ_INTSIO1);
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finish = 1;
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m_transfer_shiftreg[0] = m_dbr[m_transfer_pos[0]];
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logerror("transmitting byte %02x\n", m_transfer_shiftreg[0]);
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}
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}
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if (!finish)
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m_serial_transmit_timer[0]->adjust(cycles_to_attotime(1000)); // TODO: use real speed
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int dataout = m_transfer_shiftreg[0] & 0x01;
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m_serial_out_cb[0](dataout);
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m_transfer_shiftreg[0] >>= 1;
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m_transfer_shiftpos[0]++;
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if (m_transfer_shiftpos[0] == 8)
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{
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logerror("transmitted\n");
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m_transfer_shiftpos[0] = 0;
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m_transfer_pos[0]++;
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if (m_transfer_pos[0] > m_transfer_numbytes[0])
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{
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logerror("end of transmission\n");
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m_SIOCR1[0] &= ~0x80;
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// set interrupt latch
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m_IL |= 1 << (15 - TLCS870_IRQ_INTSIO1);
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finish = 1;
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}
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}
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if (!finish)
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m_serial_transmit_timer[0]->adjust(cycles_to_attotime(1000)); // TODO: use real speed
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}
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}
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// Serial Port 2
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@ -299,6 +299,8 @@ private:
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uint8_t m_transfer_shiftreg[2];
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uint8_t m_transfer_shiftpos[2];
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uint8_t m_transfer_mode[2];
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int m_transmit_bits[2];
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int m_receive_bits[2];
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emu_timer *m_serial_transmit_timer[2];
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@ -188,7 +188,7 @@ LVS-JAM SNK 1999.1.20
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No. PCB Label IC Markings IC Package
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----------------------------------------------------
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01 DPRAM1 DT 71321 LA55PF QFP64
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01 DPRAM1 DT 71321 LA55PF QFP64 *
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02 IC1 MC44200FT QFP44
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03 IOCTR1 TOSHIBA TMP87CH40N-4828 SDIP64
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04 BACKUP EPSON RTC62423 SOP24
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@ -204,6 +204,9 @@ Notes:
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2. If the game cart is not plugged in, the hardware shows nothing on screen.
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3. The IOCTR I/O MCU runs at 8 MHz.
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*"IDT71321 is function-compatible (but not pin-compatible) with MB8421" ( src\devices\machine\mb8421.cpp )
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It appears unlikely the interrupt function of the DPRAM is unused unless address pins are all inverted as
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there aren't any accesses to 7ff / 7fe outside of the RAM testing, commands are put at byte 0 by the MIPS
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Hyper Neo Geo game cartridges
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-----------------------------
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@ -782,8 +785,24 @@ Beast Busters 2 outputs (all at offset == 0x1c):
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WRITE32_MEMBER(hng64_state::hng64_dualport_w)
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{
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//printf("dualport WRITE %08x %08x (PC=%08x)\n", offset*4, hng64_dualport[offset], m_maincpu->pc());
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COMBINE_DATA (&m_dualport[offset]);
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/*
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MIPS clearly writes commands for the TLCS870 MCU at 00 here
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first command it writes after the startup checks is 0x0a, it should also trigger an EXTINT0 on the TLCS870
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around that time, as the EXTINT0 reads the command.
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call at CBB0 in the MCU is to read the command from shared RAM
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value is used in the jump table at CBC5
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command 0x0a points at ccbd
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which starts with a call to copy 0x40 bytes of data from 0x200 in shared RAM to the internal RAM of the MCU
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the MIPS (at least in Fatal Fury) uploads this data to shared RAM prior to the call.
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need to work out what triggers the interrupt, as a write to 0 wouldn't as the Dual Port RAM interrupts
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are on addresses 0x7fe and 0x7ff
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(currently we use m_dualport due to simulation, but this should actually be the same RAM as m_ioram)
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*/
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COMBINE_DATA(&m_dualport[offset]);
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logerror("%s: dualport WRITE %08x (%08x)\n", machine().describe_context(), offset * 4, data, mem_mask);
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}
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@ -1534,50 +1553,61 @@ void hng64_state::machine_reset()
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reset_sound();
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}
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// used (shared ram access at least)
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READ8_MEMBER(hng64_state::ioport0_r)
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{
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uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff;
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uint8_t ret = m_ioram[addr];
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/***********************************************
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logerror("%s: ioport0_r %02x (from address %04x)\n", machine().describe_context(), ret, addr);
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return ret; // expects 0x03 after writing it to port 0 earlier
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}
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Control / Lamp etc. access from MCU side?
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// used
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READ8_MEMBER(hng64_state::ioport1_r)
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{
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logerror("%s: ioport1_r\n", machine().describe_context());
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return 0xff;
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}
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this is probably 8 multiplexed 8-bit input / output ports (probably joysticks, coins etc.)
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// used (shared ram access at least)
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WRITE8_MEMBER(hng64_state::ioport0_w)
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{
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uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff;
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m_ioram[addr] = data;
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***********************************************/
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logerror("%s: ioport0_w %02x (to address %04x)\n", machine().describe_context(), data, addr);
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}
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// used
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WRITE8_MEMBER(hng64_state::ioport1_w)
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{
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logerror("%s: ioport1_w %02x\n", machine().describe_context(), data);
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/* Port bits
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aaac w-?-
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a = external port number / address?
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c = toggled during read / write accesses, probably clocking byte from/to latch
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? = toggled at the start of extint 0 , set during reads?
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w = set during writes?
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*/
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m_port1 = data;
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}
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// used
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// it does write 0xff here before each set of reading, but before setting a new output address?
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WRITE8_MEMBER(hng64_state::ioport3_w)
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{
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logerror("%s: ioport3_w %02x\n", machine().describe_context(), data);
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int addr = (m_port1&0xe0)>>5;
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logerror("%s: ioport3_w %02x (to address %02x) (other bits of m_port1 %02x)\n", machine().describe_context(), data, addr, m_port1 & 0x1f);
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}
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// used (shared ram access control for port 0 at least)
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READ8_MEMBER(hng64_state::ioport3_r)
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{
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int addr = (m_port1&0xe0)>>5;
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logerror("%s: ioport3_r (from address %02x) (other bits of m_port1 %02x)\n", machine().describe_context(), addr, m_port1 & 0x1f);
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return 0xff;
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}
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/***********************************************
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Dual Port RAM access from MCU side
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***********************************************/
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WRITE8_MEMBER(hng64_state::ioport7_w)
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{
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/* Port bits
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-?xR Aacr
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i?xR Aacr
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a = 0x200 of address bit to external RAM (direct?)
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A = 0x400 of address bit to external RAM (direct?)
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@ -1589,12 +1619,19 @@ WRITE8_MEMBER(hng64_state::ioport7_w)
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x = written with clock bits, might be latch related?
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? = written before some operations
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i = generate interrupt on MIPS? (written after the MCU has completed writing 'results' of some operations to shared ram, before executing more code to write another result, so needs to be processed quickly by the MIPS?)
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*/
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//logerror("%s: ioport7_w %02x\n", machine().describe_context(), data);
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m_ex_ramaddr_upper = (data & 0x0c) >> 2;
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if ((!(data & 0x80)) && (m_port7 & 0x80))
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{
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logerror("%s: MCU request MIPS IRQ?\n");
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}
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if ((!(data & 0x01)) && (m_port7 & 0x01))
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{
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m_ex_ramaddr = 0;
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@ -1609,18 +1646,43 @@ WRITE8_MEMBER(hng64_state::ioport7_w)
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m_port7 = data;
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}
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// check if these are used
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READ8_MEMBER(hng64_state::ioport2_r) { logerror("%s: ioport2_r\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(hng64_state::ioport3_r) { logerror("%s: ioport3_r\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(hng64_state::ioport4_r) { logerror("%s: ioport4_r\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(hng64_state::ioport5_r) { logerror("%s: ioport5_r\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(hng64_state::ioport6_r) { logerror("%s: ioport6_r\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(hng64_state::ioport7_r) { logerror("%s: ioport7_r\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(hng64_state::ioport0_r)
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{
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uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff;
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uint8_t ret = m_ioram[addr];
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WRITE8_MEMBER(hng64_state::ioport2_w) { logerror("%s: ioport2_w %02x\n", machine().describe_context(), data); }
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WRITE8_MEMBER(hng64_state::ioport4_w) { logerror("%s: ioport4_w %02x\n", machine().describe_context(), data); }
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WRITE8_MEMBER(hng64_state::ioport5_w) { logerror("%s: ioport5_w %02x\n", machine().describe_context(), data); }
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WRITE8_MEMBER(hng64_state::ioport6_w) { logerror("%s: ioport6_w %02x\n", machine().describe_context(), data); }
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logerror("%s: ioport0_r %02x (from address %04x)\n", machine().describe_context(), ret, addr);
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return ret; // expects 0x03 after writing it to port 0 earlier
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}
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WRITE8_MEMBER(hng64_state::ioport0_w)
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{
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uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff;
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m_ioram[addr] = data;
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logerror("%s: ioport0_w %02x (to address %04x)\n", machine().describe_context(), data, addr);
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}
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/***********************************************
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Unknown (LED?) access from MCU side
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***********************************************/
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/* This port is dual purpose, with the upper pins being used as a serial input / output / clock etc. and the output latch (written data) being configured appropriately however the lower 2 bits also seem to be used
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maybe these lower 2 bits were intended for serial comms LEDs, although none are documented in the PCB layouts.
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*/
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WRITE8_MEMBER(hng64_state::ioport4_w)
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{
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logerror("%s: ioport4_w %02x\n", machine().describe_context(), data);
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}
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/***********************************************
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Other port accesses from MCU side
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***********************************************/
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READ8_MEMBER(hng64_state::anport0_r) { logerror("%s: anport0_r\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(hng64_state::anport1_r) { logerror("%s: anport1_r\n", machine().describe_context()); return 0xff; }
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@ -1631,6 +1693,26 @@ READ8_MEMBER(hng64_state::anport5_r) { logerror("%s: anport5_r\n", machine().des
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READ8_MEMBER(hng64_state::anport6_r) { logerror("%s: anport6_r\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(hng64_state::anport7_r) { logerror("%s: anport7_r\n", machine().describe_context()); return 0xff; }
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/***********************************************
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Serial Accesses from MCU side
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***********************************************/
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/* I think the serial reads / writes actually go to the network hardware, and the IO MCU is acting as an interface between the actual network and the KL5C80A12CFP
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because the network connectors are on the IO board. This might also be related to the 'm_no_machine_error_code' value required which differs per IO board
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type as the game startup sequences read that from the 0x6xx region of shared RAM, which also seems to be where a lot of the serial stuff is stored.
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*/
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// there are also serial reads, TLCS870 core doesn't support them yet
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WRITE_LINE_MEMBER( hng64_state::sio0_w )
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{
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// tlcs870 core provides better logging than anything we could put here at the moment
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}
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TIMER_CALLBACK_MEMBER(hng64_state::tempio_irqon_callback)
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{
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@ -1651,7 +1733,8 @@ void hng64_state::init_io()
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m_tempio_irqoff_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hng64_state::tempio_irqoff_callback), this));
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m_tempio_irqon_timer->adjust(m_maincpu->cycles_to_attotime(100000000)); // just ensure an IRQ gets turned on to move the program forward, real source currently unknown
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m_port7 = 0;
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m_port7 = 0x00;
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m_port1 = 0x00;
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m_ex_ramaddr = 0;
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m_ex_ramaddr_upper = 0;
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@ -1686,22 +1769,23 @@ MACHINE_CONFIG_START(hng64_state::hng64)
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hng64_network(config);
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tmp87ph40an_device &iomcu(TMP87PH40AN(config, m_iomcu, 8_MHz_XTAL));
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iomcu.p0_in_cb().set(FUNC(hng64_state::ioport0_r));
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iomcu.p1_in_cb().set(FUNC(hng64_state::ioport1_r));
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iomcu.p2_in_cb().set(FUNC(hng64_state::ioport2_r));
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iomcu.p3_in_cb().set(FUNC(hng64_state::ioport3_r));
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iomcu.p4_in_cb().set(FUNC(hng64_state::ioport4_r));
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iomcu.p5_in_cb().set(FUNC(hng64_state::ioport5_r));
|
||||
iomcu.p6_in_cb().set(FUNC(hng64_state::ioport6_r));
|
||||
iomcu.p7_in_cb().set(FUNC(hng64_state::ioport7_r));
|
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iomcu.p0_out_cb().set(FUNC(hng64_state::ioport0_w));
|
||||
iomcu.p1_out_cb().set(FUNC(hng64_state::ioport1_w));
|
||||
iomcu.p2_out_cb().set(FUNC(hng64_state::ioport2_w));
|
||||
iomcu.p3_out_cb().set(FUNC(hng64_state::ioport3_w));
|
||||
iomcu.p4_out_cb().set(FUNC(hng64_state::ioport4_w));
|
||||
iomcu.p5_out_cb().set(FUNC(hng64_state::ioport5_w));
|
||||
iomcu.p6_out_cb().set(FUNC(hng64_state::ioport6_w));
|
||||
iomcu.p7_out_cb().set(FUNC(hng64_state::ioport7_w));
|
||||
iomcu.p0_in_cb().set(FUNC(hng64_state::ioport0_r)); // reads from shared ram
|
||||
//iomcu.p1_in_cb().set(FUNC(hng64_state::ioport1_r)); // the IO MCU code uses opcodes that only access the output latch, never read from the port
|
||||
//iomcu.p2_in_cb().set(FUNC(hng64_state::ioport2_r)); // the IO MCU uses EXTINT0 which shares one of the pins on this port, but the port is not used for IO
|
||||
iomcu.p3_in_cb().set(FUNC(hng64_state::ioport3_r)); // probably reads input ports?
|
||||
//iomcu.p4_in_cb().set(FUNC(hng64_state::ioport4_r)); // the IO MCU code uses opcodes that only access the output latch, never read from the port
|
||||
//iomcu.p5_in_cb().set(FUNC(hng64_state::ioport5_r)); // simply seems to be unused, neither used for an IO port, nor any of the other features
|
||||
//iomcu.p6_in_cb().set(FUNC(hng64_state::ioport6_r)); // the IO MCU code uses the ADC which shares pins with port 6, meaning port 6 isn't used as an IO port
|
||||
//iomcu.p7_in_cb().set(FUNC(hng64_state::ioport7_r)); // the IO MCU code uses opcodes that only access the output latch, never read from the port
|
||||
iomcu.p0_out_cb().set(FUNC(hng64_state::ioport0_w)); // writes to shared ram
|
||||
iomcu.p1_out_cb().set(FUNC(hng64_state::ioport1_w)); // configuration / clocking for input port (port 3) accesses
|
||||
//iomcu.p2_out_cb().set(FUNC(hng64_state::ioport2_w)); // the IO MCU uses EXTINT0 which shares one of the pins on this port, but the port is not used for IO
|
||||
iomcu.p3_out_cb().set(FUNC(hng64_state::ioport3_w)); // writes to input ports? maybe lamps, coin counters etc.?
|
||||
iomcu.p4_out_cb().set(FUNC(hng64_state::ioport4_w)); // unknown, lower 2 IO bits accessed along with serial accesses
|
||||
//iomcu.p5_out_cb().set(FUNC(hng64_state::ioport5_w)); // simply seems to be unused, neither used for an IO port, nor any of the other features
|
||||
//iomcu.p6_out_cb().set(FUNC(hng64_state::ioport6_w)); // the IO MCU code uses the ADC which shares pins with port 6, meaning port 6 isn't used as an IO port
|
||||
iomcu.p7_out_cb().set(FUNC(hng64_state::ioport7_w)); // configuration / clocking for shared ram (port 0) accesses
|
||||
// most likely the analog inputs, up to a maximum of 8
|
||||
iomcu.an0_in_cb().set(FUNC(hng64_state::anport0_r));
|
||||
iomcu.an1_in_cb().set(FUNC(hng64_state::anport1_r));
|
||||
iomcu.an2_in_cb().set(FUNC(hng64_state::anport2_r));
|
||||
@ -1710,6 +1794,9 @@ MACHINE_CONFIG_START(hng64_state::hng64)
|
||||
iomcu.an5_in_cb().set(FUNC(hng64_state::anport5_r));
|
||||
iomcu.an6_in_cb().set(FUNC(hng64_state::anport6_r));
|
||||
iomcu.an7_in_cb().set(FUNC(hng64_state::anport7_r));
|
||||
// network related?
|
||||
iomcu.serial0_out_cb().set(FUNC(hng64_state::sio0_w));
|
||||
//iomcu.serial1_out_cb().set(FUNC(hng64_state::sio1_w)); // not initialized / used
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
|
||||
@ -305,24 +305,20 @@ private:
|
||||
DECLARE_READ8_MEMBER(hng64_comm_mmu_r);
|
||||
DECLARE_WRITE8_MEMBER(hng64_comm_mmu_w);
|
||||
|
||||
// shared ram access
|
||||
DECLARE_READ8_MEMBER(ioport0_r);
|
||||
DECLARE_READ8_MEMBER(ioport1_r);
|
||||
DECLARE_READ8_MEMBER(ioport2_r);
|
||||
DECLARE_READ8_MEMBER(ioport3_r);
|
||||
DECLARE_READ8_MEMBER(ioport4_r);
|
||||
DECLARE_READ8_MEMBER(ioport5_r);
|
||||
DECLARE_READ8_MEMBER(ioport6_r);
|
||||
DECLARE_READ8_MEMBER(ioport7_r);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(ioport0_w);
|
||||
DECLARE_WRITE8_MEMBER(ioport1_w);
|
||||
DECLARE_WRITE8_MEMBER(ioport2_w);
|
||||
DECLARE_WRITE8_MEMBER(ioport3_w);
|
||||
DECLARE_WRITE8_MEMBER(ioport4_w);
|
||||
DECLARE_WRITE8_MEMBER(ioport5_w);
|
||||
DECLARE_WRITE8_MEMBER(ioport6_w);
|
||||
DECLARE_WRITE8_MEMBER(ioport7_w);
|
||||
|
||||
// input port access
|
||||
DECLARE_READ8_MEMBER(ioport3_r);
|
||||
DECLARE_WRITE8_MEMBER(ioport3_w);
|
||||
DECLARE_WRITE8_MEMBER(ioport1_w);
|
||||
|
||||
// unknown access
|
||||
DECLARE_WRITE8_MEMBER(ioport4_w);
|
||||
|
||||
// analog input access
|
||||
DECLARE_READ8_MEMBER(anport0_r);
|
||||
DECLARE_READ8_MEMBER(anport1_r);
|
||||
DECLARE_READ8_MEMBER(anport2_r);
|
||||
@ -332,7 +328,11 @@ private:
|
||||
DECLARE_READ8_MEMBER(anport6_r);
|
||||
DECLARE_READ8_MEMBER(anport7_r);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( sio0_w );
|
||||
|
||||
uint8_t m_port7;
|
||||
uint8_t m_port1;
|
||||
|
||||
int m_ex_ramaddr;
|
||||
int m_ex_ramaddr_upper;
|
||||
std::unique_ptr<uint8_t[]> m_ioram;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user