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gkigt: checkpoint (nw)

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I'm stopping here on this for now; bored people welcome.
This commit is contained in:
arbee 2016-12-10 16:48:32 -05:00
parent 08085f064b
commit 33d5d79763
1 changed files with 64 additions and 6 deletions
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70
src/mame/drivers/gkigt.cpp
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@ -78,8 +78,9 @@ PCB board that connects to 044 boards via J6 & J7
Adds the abillity to use legacy 038 EPROM based software
or 039 EPROM + SIMM software
More chips (from eBay auction):
2x Phillips / NXT 28C94 quad UART (8 serial channels total)
ADV476 256 color RAMDAC
*/
#include "emu.h"
@ -90,9 +91,12 @@ class igt_gameking_state : public driver_device
{
public:
igt_gameking_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
: driver_device(mconfig, type, tag),
m_palette(*this, "palette")
{ }
required_device<palette_device> m_palette;
virtual void video_start() override;
uint32_t screen_update_igt_gameking(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
@ -101,7 +105,7 @@ public:
DECLARE_READ32_MEMBER(igt_gk_28010008_r)
{
return rand();
return rand(); // don't quite understand this one
};
DECLARE_READ32_MEMBER(igt_gk_28030000_r)
@ -109,13 +113,57 @@ public:
return rand();
};
DECLARE_READ32_MEMBER(uart_status_r);
DECLARE_WRITE32_MEMBER(uart_w);
DECLARE_WRITE32_MEMBER(clut_w);
DECLARE_WRITE32_MEMBER(clut_mask_w);
private:
int m_offset, m_r, m_g, m_b, m_state;
bool m_bToggle;
u8 m_clut_mask;
};
static INPUT_PORTS_START( igt_gameking )
INPUT_PORTS_END
WRITE32_MEMBER(igt_gameking_state::clut_w)
{
if (mem_mask == 0x000000ff)
{
m_offset = data & 0xff;
m_state = 0;
}
else if (mem_mask == 0x00ff0000)
{
switch (m_state)
{
case 0: m_r = (data>>16) & 0xff; m_state++; break;
case 1: m_g = (data>>16) & 0xff; m_state++; break;
case 2:
m_b = (data>>16) & 0xff;
//printf("CLUT: color %d = R %d G %d B %d\n", m_offset, m_r, m_g, m_b);
m_palette->set_pen_color(m_offset, m_r<<18 | m_g<<10 | m_b<<2);
m_state = 0;
break;
}
}
}
WRITE32_MEMBER(igt_gameking_state::clut_mask_w)
{
m_clut_mask = data & 0xff;
}
READ32_MEMBER(igt_gameking_state::uart_status_r)
{
return 0x00040000;
}
WRITE32_MEMBER(igt_gameking_state::uart_w)
{
printf("%c", (data>>16) & 0x7f);
}
void igt_gameking_state::machine_start()
{
@ -123,6 +171,9 @@ void igt_gameking_state::machine_start()
void igt_gameking_state::machine_reset()
{
m_bToggle = false;
m_offset = m_state = m_r = m_g = m_b = 0;
m_clut_mask = 0xff;
}
void igt_gameking_state::video_start()
@ -142,11 +193,18 @@ static ADDRESS_MAP_START( igt_gameking_mem, AS_PROGRAM, 32, igt_gameking_state )
AM_RANGE(0x10000000, 0x10ffffff) AM_RAM
AM_RANGE(0x18070000, 0x180fffff) AM_RAM // used by MS3 for the restart IAC and afterwards
AM_RANGE(0x18000000, 0x181fffff) AM_RAM // igtsc writes from 18000000 to 1817ffff, ms3 all the way to 181fffff.
// 28010000-2801007f: first 28C94 QUART
AM_RANGE(0x28010008, 0x2801000b) AM_READ(igt_gk_28010008_r)
AM_RANGE(0x28020000, 0x280205ff) AM_RAM
AM_RANGE(0x28010030, 0x28010033) AM_READ(uart_status_r) // channel D
AM_RANGE(0x28010034, 0x28010037) AM_WRITE(uart_w) // channel D
// 28020000-2802007f: second 28C94 QUART
AM_RANGE(0x28030000, 0x28030003) AM_READ(igt_gk_28030000_r)
AM_RANGE(0x28040000, 0x2804ffff) AM_RAM
AM_RANGE(0x28050000, 0x28050003) AM_DEVREADWRITE8("ymz", ymz280b_device, read, write, 0x00ff00ff)
AM_RANGE(0x28060000, 0x28060003) AM_WRITE(clut_w)
AM_RANGE(0x28060004, 0x28060007) AM_WRITE(clut_mask_w)
AM_RANGE(0xa1000000, 0xa1011fff) AM_RAM // used by gkkey for restart IAC