Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-05-29 09:03:08 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

mc68hc11: Added BRCLR DIR, BRSET DIR, RTI, COMA, COMB, CLV [Angelo Salese]

Browse Source 
Fixed gfx decoding in Hit Poker [David Haywood]
Made some logic fixes to Hit Poker, it now gets to a "Test IRQ" msg [Angelo Salese]
This commit is contained in:
Angelo Salese 2009-06-21 20:23:12 +00:00
parent bfc144d8f9
commit 341cb728cd
3 changed files with 92 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

85
src/emu/cpu/mc68hc11/hc11ops.c
View File

@ -880,6 +880,23 @@ static void HC11OP(bra)(hc11_state *cpustate)
CYCLES(cpustate, 3);
}
/* BRCLR DIR 0x13 */
static void HC11OP(brclr_dir)(hc11_state *cpustate)
{
UINT8 d = FETCH(cpustate);
UINT8 mask = FETCH(cpustate);
INT8 rel = FETCH(cpustate);
UINT8 i = READ8(cpustate, d);
if(!(i & mask))
{
SET_PC(cpustate, cpustate->ppc + rel + 4);
}
CYCLES(cpustate, 6);
}
/* BRCLR INDX 0x1F */
static void HC11OP(brclr_indx)(hc11_state *cpustate)
{
@ -896,6 +913,23 @@ static void HC11OP(brclr_indx)(hc11_state *cpustate)
CYCLES(cpustate, 7);
}
/* BRSET DIR 0x12 */
static void HC11OP(brset_dir)(hc11_state *cpustate)
{
UINT8 d = FETCH(cpustate);
UINT8 mask = FETCH(cpustate);
INT8 rel = FETCH(cpustate);
UINT8 i = READ8(cpustate, d);
if(i & mask)
{
SET_PC(cpustate, cpustate->ppc + rel + 4);
}
CYCLES(cpustate, 6);
}
/* BRSET INDX 0x1E */
static void HC11OP(brset_indx)(hc11_state *cpustate)
{
@ -1045,6 +1079,14 @@ static void HC11OP(clr_indy)(hc11_state *cpustate)
}
/* CLV 0x0A */
static void HC11OP(clv)(hc11_state *cpustate)
{
cpustate->ccr &= ~CC_V;
CYCLES(cpustate, 2);
}
/* CMPA IMM 0x81 */
static void HC11OP(cmpa_imm)(hc11_state *cpustate)
{
@ -1185,6 +1227,32 @@ static void HC11OP(cmpb_indy)(hc11_state *cpustate)
}
/* COMA , 0x43 */
static void HC11OP(coma)(hc11_state *cpustate)
{
UINT16 r = 0xff - REG_A;
CLEAR_NZVC(cpustate);
SET_N8(r);
SET_Z8(r);
cpustate->ccr |= CC_C; //always set for M6800 compatibility
REG_A = r;
CYCLES(cpustate, 2);
}
/* COMB , 0x53 */
static void HC11OP(comb)(hc11_state *cpustate)
{
UINT16 r = 0xff - REG_B;
CLEAR_NZVC(cpustate);
SET_N8(r);
SET_Z8(r);
cpustate->ccr |= CC_C; //always set for M6800 compatibility
REG_B = r;
CYCLES(cpustate, 2);
}
/* CPD IMM 0x1A, 0x83 */
static void HC11OP(cpd_imm)(hc11_state *cpustate)
{
@ -2308,6 +2376,23 @@ static void HC11OP(rolb)(hc11_state *cpustate)
CYCLES(cpustate, 2);
}
/* RTI 0x3B */
static void HC11OP(rti)(hc11_state *cpustate)
{
UINT16 rt_adr;
UINT8 x_flag = cpustate->ccr & CC_X;
cpustate->ccr = POP8(cpustate);
if(x_flag == 0 && cpustate->ccr & CC_X) //X flag cannot do a 0->1 transition with this instruction.
cpustate->ccr &= ~CC_X;
REG_B = POP8(cpustate);
REG_A = POP8(cpustate);
cpustate->ix = POP16(cpustate);
cpustate->iy = POP16(cpustate);
rt_adr = POP16(cpustate);
SET_PC(cpustate, rt_adr);
CYCLES(cpustate, 12);
}
/* RTS 0x39 */
static void HC11OP(rts)(hc11_state *cpustate)
{

12
src/emu/cpu/mc68hc11/hc11ops.h
View File

@ -82,11 +82,11 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
{ 0, 0x26, HC11OP(bne) },
{ 0, 0x2a, HC11OP(bpl) },
{ 0, 0x20, HC11OP(bra) },
// { 0, 0x13, HC11OP(brclr_dir) },
{ 0, 0x13, HC11OP(brclr_dir) },
{ 0, 0x1f, HC11OP(brclr_indx) },
// { 0x18, 0x1f, HC11OP(brclr_indy) },
{ 0, 0x21, HC11OP(brn) },
// { 0, 0x12, HC11OP(brset_dir) },
{ 0, 0x12, HC11OP(brset_dir) },
{ 0, 0x1e, HC11OP(brset_indx) },
// { 0x18, 0x1e, HC11OP(brset_indy) },
// { 0, 0x14, HC11OP(bset_dir) },
@ -103,7 +103,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
{ 0, 0x7f, HC11OP(clr_ext) },
{ 0, 0x6f, HC11OP(clr_indx) },
{ 0x18, 0x6f, HC11OP(clr_indy) },
// { 0, 0x0a, HC11OP(clv) },
{ 0, 0x0a, HC11OP(clv) },
{ 0, 0x81, HC11OP(cmpa_imm) },
{ 0, 0x91, HC11OP(cmpa_dir) },
{ 0, 0xb1, HC11OP(cmpa_ext) },
@ -114,8 +114,8 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
{ 0, 0xf1, HC11OP(cmpb_ext) },
{ 0, 0xe1, HC11OP(cmpb_indx) },
{ 0x18, 0xe1, HC11OP(cmpb_indy) },
// { 0, 0x43, HC11OP(coma) },
// { 0, 0x53, HC11OP(comb) },
{ 0, 0x43, HC11OP(coma) },
{ 0, 0x53, HC11OP(comb) },
// { 0, 0x73, HC11OP(com_ext) },
// { 0, 0x63, HC11OP(com_indx) },
// { 0x18, 0x63, HC11OP(com_indy) },
@ -242,7 +242,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
// { 0, 0x76, HC11OP(ror_ext) },
// { 0, 0x66, HC11OP(ror_indx) },
// { 0x18, 0x66, HC11OP(ror_indy) },
// { 0, 0x3b, HC11OP(rti) },
{ 0, 0x3b, HC11OP(rti) },
{ 0, 0x39, HC11OP(rts) },
// { 0, 0x10, HC11OP(sba) },
// { 0, 0x82, HC11OP(sbca_imm) },

2
src/emu/cpu/mc68hc11/mc68hc11.c
View File

@ -1,7 +1,7 @@
/*
Motorola MC68HC11 emulator
Written by Ville Linde
Written by Ville Linde & Angelo Salese
*/
#include "debugger.h"