diff --git a/src/devices/machine/vrc4373.cpp b/src/devices/machine/vrc4373.cpp index 8aef5983ee9..5ddfe2ad346 100644 --- a/src/devices/machine/vrc4373.cpp +++ b/src/devices/machine/vrc4373.cpp @@ -92,7 +92,7 @@ ADDRESS_MAP_END vrc4373_device::vrc4373_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : pci_host_device(mconfig, VRC4373, tag, owner, clock), - m_cpu_space(nullptr), m_cpu(nullptr), cpu_tag(nullptr), m_irq_num(-1), m_ram_size(0x0), m_simm0_size(0x0), + m_cpu_space(nullptr), m_irq_cb(*this), m_cpu(nullptr), cpu_tag(nullptr), m_ram_size(0x0), m_simm0_size(0x0), m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32), m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32), m_pci1_laddr(0), m_pci2_laddr(0), m_pci_io_laddr(0), m_target1_laddr(0), m_target2_laddr(0), m_romRegion(*this, "rom") @@ -114,6 +114,7 @@ void vrc4373_device::device_start() m_cpu_space = &m_cpu->space(AS_PCI_CONFIG); memory_space = &space(AS_PCI_MEM); io_space = &space(AS_PCI_IO); + is_multifunction_device = false; memset(m_cpu_regs, 0, sizeof(m_cpu_regs)); @@ -124,6 +125,9 @@ void vrc4373_device::device_start() io_window_end = 0xffffffff; io_offset = 0x00000000; status = 0x0280; + + m_irq_cb.resolve(); + // Reserve 8M for ram m_ram.reserve(0x00800000 / 4); m_ram.resize(m_ram_size); @@ -414,8 +418,8 @@ TIMER_CALLBACK_MEMBER (vrc4373_device::dma_transfer) m_cpu_regs[NREG_DMACR1 + which * 0xc] &= ~DMA_GO; // Set the interrupt if (m_cpu_regs[NREG_DMACR1 + which * 0xc] & DMA_INT_EN) { - if (m_irq_num != -1) { - m_cpu->set_input_line(m_irq_num, ASSERT_LINE); + if (!m_irq_cb.isnull()) { + m_irq_cb(ASSERT_LINE); } else { logerror("vrc4373_device::dma_transfer Error: DMA configured to trigger interrupt but no interrupt line configured\n"); } @@ -436,6 +440,10 @@ READ32_MEMBER (vrc4373_device::cpu_if_r) case NREG_PCICDR: result = config_data_r(space, offset); break; + case NREG_ICSR: + // Top 16 bits always read as zero + result &= 0xffff; + break; default: break; } @@ -514,6 +522,13 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w) LOGNILE("%08X:nile Start DMA Lane %i PCI: %08X MEM: %08X Words: %X\n", m_cpu->space(AS_PCI_CONFIG).device().safe_pc(), which, m_cpu_regs[NREG_DMA_CPAR], m_cpu_regs[NREG_DMA_CMAR], m_cpu_regs[NREG_DMA_REM]); } break; + case NREG_ICSR: + // TODO: Check and clear individual interrupts + if (data & 0xff000000) { + if (!m_irq_cb.isnull()) + m_irq_cb(CLEAR_LINE); + } + break; case NREG_BMCR: case NREG_SIMM1: case NREG_SIMM2: diff --git a/src/devices/machine/vrc4373.h b/src/devices/machine/vrc4373.h index 47ff76feb95..e321a4ebde4 100644 --- a/src/devices/machine/vrc4373.h +++ b/src/devices/machine/vrc4373.h @@ -20,6 +20,9 @@ #define MCFG_VRC4373_SET_SIMM0(_size) \ downcast(device)->set_simm0_size(_size); +#define MCFG_VRC4373_IRQ_CB(_devcb) \ + devcb = &ide_pci_device::set_irq_cb(*device, DEVCB_##_devcb); + class vrc4373_device : public pci_host_device { public: @@ -30,6 +33,7 @@ public: uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override; void postload(void); + template static devcb_base &set_irq_cb(device_t &device, Object &&cb) { return downcast(device).m_irq_cb.set_callback(std::forward(cb)); } void set_cpu_tag(const char *tag); void set_ram_size(const int size) { m_ram_size = size; }; void set_simm0_size(const int size) { m_simm0_size = size; }; @@ -80,9 +84,10 @@ private: void map_cpu_space(); + devcb_write_line m_irq_cb; + mips3_device *m_cpu; const char *cpu_tag; - int m_irq_num; int m_ram_size; int m_simm0_size; diff --git a/src/mame/drivers/atlantis.cpp b/src/mame/drivers/atlantis.cpp index 42aed47c108..fb790e6fd2a 100644 --- a/src/mame/drivers/atlantis.cpp +++ b/src/mame/drivers/atlantis.cpp @@ -61,29 +61,33 @@ #define RESET_IDE 0x10 #define RESET_DUART 0x20 -// IRQ Bits +// IRQ Status Bits #define IOASIC_IRQ_SHIFT 0 #define ROMBUS_IRQ_SHIFT 1 -#define ZEUS0_IRQ_SHIFT 2 -#define ZEUS1_IRQ_SHIFT 3 -#define ZEUS2_IRQ_SHIFT 4 +#define ZEUS_IRQ_SHIFT 2 +#define DUART_IRQ_SHIFT 3 +// PCI Slot and USB Chip +#define PCI_IRQ_SHIFT 4 #define WDOG_IRQ_SHIFT 5 #define A2D_IRQ_SHIFT 6 #define VBLANK_IRQ_SHIFT 7 -// DUART mapped to int3 (map3 = 0x08) -#define UART1_IRQ_SHIFT ZEUS1_IRQ_SHIFT -#define UART2_IRQ_SHIFT ZEUS1_IRQ_SHIFT -// PCI mapped to int2 (map2 = 0x10) -#define PCI_IRQ_SHIFT ZEUS2_IRQ_SHIFT - /* static interrupts */ #define GALILEO_IRQ_NUM MIPS3_IRQ0 #define IDE_IRQ_NUM MIPS3_IRQ4 -#define PCI_ID_NILE ":pci:00.0" +// From linux header +// IDSEL = AD17, USB chip +// IDSEL = AD18, CMD646 chip +// IDSEL = AD19, onboard PCI slot +// IDSEL = AD20, Nile 3 chip +// IDSEL = AD21, PLX9050 chip +// IDSEL = AD22, PCI expansion +// IDSEL = AD23, PCI expansion +// IDSEL = AD24, PCI expansion +#define PCI_ID_IDE ":pci:08.0" +#define PCI_ID_NILE ":pci:0a.0" #define PCI_ID_9050 ":pci:0b.0" -#define PCI_ID_IDE ":pci:0c.0" #define DEBUG_CONSOLE (0) #define LOG_RTC (0) @@ -161,8 +165,7 @@ public: DECLARE_WRITE_LINE_MEMBER(watchdog_irq); DECLARE_WRITE_LINE_MEMBER(watchdog_reset); - DECLARE_WRITE_LINE_MEMBER(uart1_irq_callback); - DECLARE_WRITE_LINE_MEMBER(uart2_irq_callback); + DECLARE_WRITE_LINE_MEMBER(duart_irq_callback); DECLARE_CUSTOM_INPUT_MEMBER(port_mod_r); DECLARE_READ16_MEMBER(port_ctrl_r); @@ -183,8 +186,9 @@ public: // Parallel Port READ8_MEMBER(atlantis_state::parallel_r) { - logerror("%06X: parallel_r %08x = %02x\n", machine().device("maincpu")->safe_pc(), offset, 0); - return 0x3; + uint8_t result = 0x7; + logerror("%06X: parallel_r %08x = %02x\n", machine().device("maincpu")->safe_pc(), offset, result); + return result; } WRITE8_MEMBER(atlantis_state::parallel_w) @@ -268,9 +272,7 @@ WRITE32_MEMBER(atlantis_state::board_ctrl_w) // 0x1 VBlank clear? if (changeData & 0x1) { if ((data & 0x0001) == 0) { - uint32_t status_bit = (1 << VBLANK_IRQ_SHIFT); - board_ctrl[CAUSE] &= ~status_bit; - board_ctrl[STATUS] &= ~status_bit; + board_ctrl[STATUS] &= ~(1 << VBLANK_IRQ_SHIFT); update_asic_irq(); } else { @@ -281,7 +283,6 @@ WRITE32_MEMBER(atlantis_state::board_ctrl_w) break; case IRQ_EN: // Zero bit will clear cause - board_ctrl[CAUSE] &= data; update_asic_irq(); if (LOG_IRQ) logerror("%s:board_ctrl_w write to IRQ_EN offset %04X = %08X & %08X bus offset = %08X\n", machine().describe_context(), newOffset, data, mem_mask, offset); @@ -395,39 +396,20 @@ READ32_MEMBER(atlantis_state::user_io_input) } /************************************* -* UART1 interrupt handler +* DUART interrupt handler *************************************/ -WRITE_LINE_MEMBER(atlantis_state::uart1_irq_callback) +WRITE_LINE_MEMBER(atlantis_state::duart_irq_callback) { - uint32_t status_bit = UART1_IRQ_SHIFT; + uint32_t status_bit = 1 << DUART_IRQ_SHIFT; if (state && !(board_ctrl[STATUS] & status_bit)) { board_ctrl[STATUS] |= status_bit; update_asic_irq(); } else if (!state && (board_ctrl[STATUS] & status_bit)) { board_ctrl[STATUS] &= ~status_bit; - board_ctrl[CAUSE] &= ~status_bit; update_asic_irq(); } - logerror("atlantis_state::uart1_irq_callback state = %1x\n", state); -} - -/************************************* -* UART2 interrupt handler -*************************************/ -WRITE_LINE_MEMBER(atlantis_state::uart2_irq_callback) -{ - uint32_t status_bit = UART2_IRQ_SHIFT; - if (state && !(board_ctrl[STATUS] & status_bit)) { - board_ctrl[STATUS] |= status_bit; - update_asic_irq(); - } - else if (!state && (board_ctrl[STATUS] & status_bit)) { - board_ctrl[STATUS] &= ~status_bit; - board_ctrl[CAUSE] &= ~status_bit; - update_asic_irq(); - } - logerror("atlantis_state::uart2_irq_callback state = %1x\n", state); + logerror("atlantis_state::duart_irq_callback state = %1x\n", state); } /************************************* @@ -438,27 +420,23 @@ WRITE_LINE_MEMBER(atlantis_state::vblank_irq) //logerror("%s: atlantis_state::vblank state = %i\n", machine().describe_context(), state); if (state) { board_ctrl[STATUS] |= (1 << VBLANK_IRQ_SHIFT); - update_asic_irq(); } else { board_ctrl[STATUS] &= ~(1 << VBLANK_IRQ_SHIFT); - board_ctrl[CAUSE] &= ~(1 << VBLANK_IRQ_SHIFT); - update_asic_irq(); } + update_asic_irq(); } WRITE_LINE_MEMBER(atlantis_state::zeus_irq) { //logerror("%s: atlantis_state::zeus_irq state = %i\n", machine().describe_context(), state); if (state) { - board_ctrl[STATUS] |= (1 << ZEUS0_IRQ_SHIFT); - update_asic_irq(); + board_ctrl[STATUS] |= (1 << ZEUS_IRQ_SHIFT); } else { - board_ctrl[STATUS] &= ~(1 << ZEUS0_IRQ_SHIFT); - board_ctrl[CAUSE] &= ~(1 << ZEUS0_IRQ_SHIFT); - update_asic_irq(); + board_ctrl[STATUS] &= ~(1 << ZEUS_IRQ_SHIFT); } + update_asic_irq(); } /************************************* @@ -466,7 +444,14 @@ WRITE_LINE_MEMBER(atlantis_state::zeus_irq) *************************************/ WRITE_LINE_MEMBER(atlantis_state::ide_irq) { - m_maincpu->set_input_line(IDE_IRQ_NUM, state); + if (state) { + m_maincpu->set_input_line(IDE_IRQ_NUM, ASSERT_LINE); + m_irq_state |= (1 << IDE_IRQ_NUM); + } + else { + m_maincpu->set_input_line(IDE_IRQ_NUM, CLEAR_LINE); + m_irq_state &= ~(1 << IDE_IRQ_NUM); + } if (LOG_IRQ) logerror("%s: atlantis_state::ide_irq state = %i\n", machine().describe_context(), state); } @@ -480,13 +465,11 @@ WRITE_LINE_MEMBER(atlantis_state::ioasic_irq) logerror("%s: atlantis_state::ioasic_irq state = %i\n", machine().describe_context(), state); if (state) { board_ctrl[STATUS] |= (1 << IOASIC_IRQ_SHIFT); - update_asic_irq(); } else { board_ctrl[STATUS] &= ~(1 << IOASIC_IRQ_SHIFT); - board_ctrl[CAUSE] &= ~(1 << IOASIC_IRQ_SHIFT); - update_asic_irq(); } + update_asic_irq(); } /************************************* @@ -498,14 +481,11 @@ WRITE_LINE_MEMBER(atlantis_state::watchdog_irq) logerror("%s: atlantis_state::watchdog_irq state = %i\n", machine().describe_context(), state); if (state) { board_ctrl[STATUS] |= (1 << WDOG_IRQ_SHIFT); - update_asic_irq(); } else { board_ctrl[STATUS] &= ~(1 << WDOG_IRQ_SHIFT); - board_ctrl[CAUSE] &= ~(1 << WDOG_IRQ_SHIFT); - update_asic_irq(); } - + update_asic_irq(); } /************************************* @@ -525,12 +505,13 @@ WRITE_LINE_MEMBER(atlantis_state::watchdog_reset) *************************************/ void atlantis_state::update_asic_irq() { + // Update cause register + board_ctrl[CAUSE] = board_ctrl[IRQ_EN] & board_ctrl[STATUS]; + // Check the MAP1, MAP2, and MAP3 and signal interrupt for (int irqIndex = 0; irqIndex < 3; irqIndex++) { - uint32_t irqBits = (board_ctrl[IRQ_EN] & board_ctrl[IRQ_MAP1 + irqIndex] & board_ctrl[STATUS]); - uint32_t causeBits = (board_ctrl[IRQ_EN] & board_ctrl[IRQ_MAP1 + irqIndex] & board_ctrl[CAUSE]); + uint32_t causeBits = board_ctrl[CAUSE] & board_ctrl[IRQ_MAP1 + irqIndex]; uint32_t currState = m_irq_state & (2 << irqIndex); - board_ctrl[CAUSE] |= irqBits; - if (irqBits && !currState) { + if (causeBits && !currState) { m_maincpu->set_input_line(MIPS3_IRQ1 + irqIndex, ASSERT_LINE); m_irq_state |= (2 << irqIndex); if (LOG_IRQ) @@ -727,9 +708,9 @@ static INPUT_PORTS_START( mwskins ) PORT_DIPSETTING(0x0002, "Boot Disk Based Self Test") PORT_DIPSETTING(0x0001, "Boot EEPROM Based Self Test") PORT_DIPSETTING(0x0000, "Run Interactive Tests") - PORT_DIPNAME(0x0004, 0x0004, "Boot Message") - PORT_DIPSETTING(0x0004, "Quiet") - PORT_DIPSETTING(0x0000, "Squawk During Boot") + PORT_DIPNAME(0x0004, 0x0004, "Console Enable") + PORT_DIPSETTING(0x0004, DEF_STR(No)) + PORT_DIPSETTING(0x0000, DEF_STR(Yes)) PORT_DIPUNUSED(0xfff8, 0xfff8) PORT_START("SYSTEM") @@ -816,6 +797,7 @@ static MACHINE_CONFIG_START( mwskins ) MCFG_CPU_ADD("maincpu", VR4310LE, 166666666) // clock is TRUSTED MCFG_MIPS3_ICACHE_SIZE(16384) MCFG_MIPS3_DCACHE_SIZE(16384) + MCFG_MIPS3_SYSTEM_CLOCK(66666666) MCFG_PCI_ROOT_ADD( ":pci") MCFG_VRC4373_ADD( PCI_ID_NILE, ":maincpu") @@ -832,8 +814,13 @@ static MACHINE_CONFIG_START( mwskins ) MCFG_M48T37_RESET_HANDLER(WRITELINE(atlantis_state, watchdog_reset)) MCFG_M48T37_IRQ_HANDLER(WRITELINE(atlantis_state, watchdog_irq)) - MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x07, 0x0) + MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x05, 0x0) MCFG_IDE_PCI_IRQ_HANDLER(DEVWRITELINE(":", atlantis_state, ide_irq)) + // The pci-ide by default expects the system controller to be pci:00.0 so need to fix here + MCFG_DEVICE_MODIFY(PCI_ID_IDE":ide") + MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(PCI_ID_NILE, AS_DATA) + MCFG_DEVICE_MODIFY(PCI_ID_IDE":ide2") + MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(PCI_ID_NILE, AS_DATA) /* video hardware */ MCFG_DEVICE_ADD("zeus2", ZEUS2, ZEUS2_VIDEO_CLOCK) @@ -868,13 +855,13 @@ static MACHINE_CONFIG_START( mwskins ) MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com1", rs232_port_device, write_txd)) MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com1", rs232_port_device, write_dtr)) MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com1", rs232_port_device, write_rts)) - MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart1_irq_callback)) + MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, duart_irq_callback)) MCFG_DEVICE_ADD("uart2", NS16550, XTAL_24MHz) MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com2", rs232_port_device, write_txd)) MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com2", rs232_port_device, write_dtr)) MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com2", rs232_port_device, write_rts)) - MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart2_irq_callback)) + MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, duart_irq_callback)) MCFG_RS232_PORT_ADD("com1", default_rs232_devices, nullptr) MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, rx_w)) diff --git a/src/mame/drivers/vegas.cpp b/src/mame/drivers/vegas.cpp index 566f15d33d4..2bffc4526f1 100644 --- a/src/mame/drivers/vegas.cpp +++ b/src/mame/drivers/vegas.cpp @@ -358,8 +358,7 @@ public: uint32_t m_keypad_select; uint32_t m_gear; - DECLARE_WRITE_LINE_MEMBER(uart1_irq_cb); - DECLARE_WRITE_LINE_MEMBER(uart2_irq_cb); + DECLARE_WRITE_LINE_MEMBER(duart_irq_cb); DECLARE_WRITE_LINE_MEMBER(vblank_assert); DECLARE_DRIVER_INIT(gauntleg); DECLARE_DRIVER_INIT(cartfury); @@ -581,22 +580,12 @@ void vegas_state::update_sio_irqs() } } -WRITE_LINE_MEMBER(vegas_state::uart1_irq_cb) +WRITE_LINE_MEMBER(vegas_state::duart_irq_cb) { if (state) - m_sio_irq_state |= (1 << 4); + m_nile->pci_intr_c(ASSERT_LINE); else - m_sio_irq_state &= ~(1 << 4); - update_sio_irqs(); -} - -WRITE_LINE_MEMBER(vegas_state::uart2_irq_cb) -{ - if (state) - m_sio_irq_state |= (1 << 4); - else - m_sio_irq_state &= ~(1 << 4); - update_sio_irqs(); + m_nile->pci_intr_c(CLEAR_LINE); } WRITE_LINE_MEMBER(vegas_state::vblank_assert) @@ -949,7 +938,7 @@ READ32_MEMBER(vegas_state::unknown_r) *************************************/ READ8_MEMBER(vegas_state::parallel_r) { - uint8_t result = 0x3; + uint8_t result = 0x7; logerror("%06X: parallel_r %08x = %02x\n", machine().device("maincpu")->safe_pc(), offset, result); return result; } @@ -1524,9 +1513,9 @@ static INPUT_PORTS_START( sf2049se ) PORT_MODIFY("DIPS") PORT_DIPUNUSED( 0x001e, 0x001e ) - PORT_DIPNAME(0x0020, 0x0020, "Boot Message") - PORT_DIPSETTING( 0x0020, "Quiet") - PORT_DIPSETTING( 0x0000, "Squawk During Boot") + PORT_DIPNAME( 0x0020, 0x0020, "Console Enable" ) + PORT_DIPSETTING( 0x0020, DEF_STR(No)) + PORT_DIPSETTING( 0x0000, DEF_STR(Yes)) PORT_DIPNAME( 0x00c0, 0x00c0, "Test Mode" ) PORT_DIPSETTING( 0x00c0, DEF_STR( Off ) ) PORT_DIPSETTING( 0x0080, "Disk-based Test" ) @@ -1636,9 +1625,10 @@ static ADDRESS_MAP_START(vegas_cs7_map, AS_PROGRAM, 32, vegas_state) ADDRESS_MAP_END static ADDRESS_MAP_START(vegas_cs8_map, AS_PROGRAM, 32, vegas_state) - AM_RANGE(0x01000000, 0x0100001f) AM_DEVREADWRITE8("uart2", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART2 (TL16C552 CS0) - AM_RANGE(0x01400000, 0x0140001f) AM_DEVREADWRITE8("uart1", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART1 (TL16C552 CS1) + AM_RANGE(0x01000000, 0x0100001f) AM_DEVREADWRITE8("uart1", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial ttyS01 (TL16C552 CS0) + AM_RANGE(0x01400000, 0x0140001f) AM_DEVREADWRITE8("uart2", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial ttyS02 (TL16C552 CS1) AM_RANGE(0x01800000, 0x0180001f) AM_READWRITE8(parallel_r, parallel_w, 0xff) // Parallel UART (TL16C552 CS2) + //AM_RANGE(0x01c00000, 0x0180001f) AM_READWRITE8(parallel_r, parallel_w, 0xff) // MPS Reset ADDRESS_MAP_END /************************************* @@ -1667,7 +1657,7 @@ static MACHINE_CONFIG_START( vegascore ) MCFG_VRC5074_SET_CS(6, vegas_cs6_map) MCFG_VRC5074_SET_CS(7, vegas_cs7_map) - MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x07, 0x0) + MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x05, 0x0) MCFG_IDE_PCI_IRQ_HANDLER(DEVWRITELINE(PCI_ID_NILE, vrc5074_device, pci_intr_d)) //MCFG_IDE_PCI_SET_PIF(0x8f) @@ -1762,25 +1752,25 @@ static MACHINE_CONFIG_DERIVED( denver, vegascore ) // TL16C552 UART MCFG_DEVICE_ADD("uart1", NS16550, vegas_state::SYSTEM_CLOCK / 12) - MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com1", rs232_port_device, write_txd)) - MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com1", rs232_port_device, write_dtr)) - MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com1", rs232_port_device, write_rts)) - MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", vegas_state, uart1_irq_cb)) + MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("ttys01", rs232_port_device, write_txd)) + MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("ttys01", rs232_port_device, write_dtr)) + MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("ttys01", rs232_port_device, write_rts)) + MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", vegas_state, duart_irq_cb)) MCFG_DEVICE_ADD("uart2", NS16550, vegas_state::SYSTEM_CLOCK / 12) - MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com2", rs232_port_device, write_txd)) - MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com2", rs232_port_device, write_dtr)) - MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com2", rs232_port_device, write_rts)) - MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", vegas_state, uart2_irq_cb)) + MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("ttys02", rs232_port_device, write_txd)) + MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("ttys02", rs232_port_device, write_dtr)) + MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("ttys02", rs232_port_device, write_rts)) + MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", vegas_state, duart_irq_cb)) - MCFG_RS232_PORT_ADD("com1", default_rs232_devices, nullptr) + MCFG_RS232_PORT_ADD("ttys01", default_rs232_devices, nullptr) MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, rx_w)) MCFG_RS232_DCD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, dcd_w)) MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, dsr_w)) MCFG_RS232_RI_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, ri_w)) MCFG_RS232_CTS_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, cts_w)) - MCFG_RS232_PORT_ADD("com2", default_rs232_devices, nullptr) + MCFG_RS232_PORT_ADD("ttys02", default_rs232_devices, nullptr) MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, rx_w)) MCFG_RS232_DCD_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, dcd_w)) MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, dsr_w))