mirror of
https://github.com/holub/mame
synced 2025-07-01 00:09:18 +03:00
midzeus: Added trackball and keyboard to the grid. Driver reorg and cleanup. (nw)
This commit is contained in:
Ted Green
parent
5783191dce
commit
34c3da3aa2
@ -37,6 +37,7 @@ The Grid v1.2 10/18/2000
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#include "crusnexo.lh"
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#define LOG_FW (0)
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#define CPU_CLOCK XTAL_60MHz
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@ -51,7 +52,8 @@ static int32_t gun_x[2], gun_y[2];
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static uint8_t crusnexo_leds_select;
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static uint8_t keypad_select;
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static uint8_t bitlatch[10];
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static uint32_t disk_asic[0x10];
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static uint32_t disk_asic_jr[0x10];
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static uint8_t cmos_protected;
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@ -72,6 +74,8 @@ public:
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required_device<zeus2_device> m_zeus;
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DECLARE_WRITE_LINE_MEMBER(zeus_irq);
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DECLARE_READ32_MEMBER(zeus2_timekeeper_r);
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DECLARE_WRITE32_MEMBER(zeus2_timekeeper_w);
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private:
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};
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@ -109,6 +113,9 @@ MACHINE_RESET_MEMBER(midzeus_state,midzeus)
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m_maincpu->reset();
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cmos_protected = true;
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memset(disk_asic_jr, 0x0, 0x10 * 4);
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disk_asic_jr[6] = 0xa0; // Rev3 Athens
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memset(disk_asic, 0x0, 0x10 * 4);
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}
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@ -144,10 +151,10 @@ WRITE_LINE_MEMBER(midzeus2_state::zeus_irq)
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WRITE32_MEMBER(midzeus_state::cmos_w)
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{
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if (bitlatch[2] && !cmos_protected)
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if (disk_asic_jr[2] && !cmos_protected)
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COMBINE_DATA(&m_nvram[offset]);
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else
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logerror("%06X:timekeeper_w with bitlatch[2] = %d, cmos_protected = %d\n", space.device().safe_pc(), bitlatch[2], cmos_protected);
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logerror("%06X:timekeeper_w with disk_asic_jr[2] = %d, cmos_protected = %d\n", space.device().safe_pc(), disk_asic_jr[2], cmos_protected);
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cmos_protected = true;
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}
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@ -172,17 +179,17 @@ WRITE32_MEMBER(midzeus_state::cmos_protect_w)
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*
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*************************************/
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READ32_MEMBER(midzeus_state::zeus2_timekeeper_r)
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READ32_MEMBER(midzeus2_state::zeus2_timekeeper_r)
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{
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return m_m48t35->read(space, offset, 0xff) | 0xffffff00;
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}
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WRITE32_MEMBER(midzeus_state::zeus2_timekeeper_w)
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WRITE32_MEMBER(midzeus2_state::zeus2_timekeeper_w)
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{
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if (bitlatch[2] && !cmos_protected)
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if (disk_asic_jr[2] && !cmos_protected)
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m_m48t35->write(space, offset, data, 0xff);
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else
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logerror("%s:zeus2_timekeeper_w with bitlatch[2] = %d, cmos_protected = %d\n", machine().describe_context(), bitlatch[2], cmos_protected);
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logerror("%s:zeus2_timekeeper_w with disk_asic_jr[2] = %d, cmos_protected = %d\n", machine().describe_context(), disk_asic_jr[2], cmos_protected);
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cmos_protected = true;
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}
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@ -195,114 +202,198 @@ READ32_MEMBER(midzeus_state::zpram_r)
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WRITE32_MEMBER(midzeus_state::zpram_w)
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{
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if (bitlatch[2])
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if (disk_asic_jr[2])
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COMBINE_DATA(&m_nvram[offset]);
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else
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logerror("%06X:zpram_w with bitlatch[2] = %d\n", space.device().safe_pc(), bitlatch[2]);
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logerror("%06X:zpram_w with disk_asic_jr[2] = %d\n", space.device().safe_pc(), disk_asic_jr[2]);
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}
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/*************************************
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*
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* Miscellaneous bit latches
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*
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*************************************/
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READ32_MEMBER(midzeus_state::bitlatches_r)
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*
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* Disk ASIC registers
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*
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*************************************/
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READ32_MEMBER(midzeus_state::disk_asic_r)
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{
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uint32_t retVal = disk_asic[offset];
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switch (offset)
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{
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/* unknown purpose; two bits are apparently used */
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// Sys Control
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// Bit 0: zeus reset
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// Bit 3: io reset
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// Bit 15:8 Version
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case 0:
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retVal = (retVal & 0xffff00ff) | 0x3300;
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break;
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// Interrupt Status / Control
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// 0x004: IFIFO Interrupt
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// 0x200: Firewire
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case 1:
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return bitlatch[offset] | ~3;
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/* CMOS/ZPRAM extra enable latch; only low bit is used */
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retVal = 0x0;
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break;
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// Test
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case 2:
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return bitlatch[offset] | ~1;
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/* unknown purpose; mk4/invasn/thegrid read at startup; invasn freaks if it is 1 at startup */
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/* only low bit is used */
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break;
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// Wait State Config
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case 3:
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return bitlatch[offset] | ~1;
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/* ROM bank selection on Zeus 2; two bits are used */
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break;
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// IDE Config
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case 4:
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break;
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// PSRAM Config
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case 5:
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return bitlatch[offset] | ~3;
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/* unknown purpose; crusnexo reads at startup: if (val & 0xf0) == 0xa0 it affects */
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/* how the Zeus is used (reg 0x5d is set to 0x54580006) */
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/* thegrid does the same, writing either 0xD4580006 or 0xC4180006 depending */
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/* this is the value reported as DISK JR ASIC version in thegrid startup test */
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case 6:
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return 0xa0 | ~0xff;
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/* unknown purpose */
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break;
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// Unknown
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default:
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logerror("%06X:bitlatches_r(%X)\n", space.device().safe_pc(), offset);
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logerror("%06X:disk_asic_r(%X) Unknown\n", space.device().safe_pc(), offset);
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break;
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}
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return ~0;
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return retVal;
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}
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WRITE32_MEMBER(midzeus_state::bitlatches_w)
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WRITE32_MEMBER(midzeus_state::disk_asic_w)
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{
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uint32_t oldval = bitlatch[offset];
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bitlatch[offset] = data;
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disk_asic[offset] = data;
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switch (offset)
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{
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// Sys Control
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// Bit 0: zeus reset
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// Bit 3: io reset
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case 0:
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break;
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// Interrupt Status / Control
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// 0x004: IFIFO Interrupt
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// 0x200: Enable Firewire interrupt
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case 1:
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break;
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// Test
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case 2:
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break;
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// Wait State Config
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case 3:
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break;
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// IDE Config
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case 4:
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break;
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// PSRAM Config
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case 5:
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break;
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// Unknown
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default:
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logerror("%06X:disk_asic_w(%X)=%08X Unknown\n", space.device().safe_pc(), offset, data);
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break;
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}
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}
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/*************************************
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*
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* Disk ASIC JR registers
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*
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*************************************/
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READ32_MEMBER(midzeus_state::disk_asic_jr_r)
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{
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uint32_t retVal = disk_asic_jr[offset];
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switch (offset)
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{
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// miscelaneous hw wait states
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case 1:
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break;
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/* CMOS/ZPRAM write enable; only low bit is used */
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case 2:
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break;
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// return disk_asic_jr[offset] | ~1;
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/* reset status; bit 0 is watchdog reset; mk4/invasn/thegrid read at startup; invasn freaks if it is 1 at startup */
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case 3:
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break;
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// return disk_asic_jr[offset] | ~1;
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/* ROM bank selection on Zeus 2; two bits are used */
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case 5:
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// return disk_asic_jr[offset] | ~3;
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/* disk asic jr id; crusnexo reads at startup: if (val & 0xf0) == 0xa0 it affects */
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/* how the Zeus is used (reg 0x5d is set to 0x54580006) */
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/* thegrid does the same, writing either 0xD4580006 or 0xC4180006 depending */
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/* this is the value reported as DISK JR ASIC version in thegrid startup test */
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// Set in reset
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// a0 = Rev3 Athens
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// 90 = Rev2 Athens
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case 6:
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break;
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/* unknown purpose */
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default:
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if (oldval ^ data)
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logerror("%06X:bitlatches_w(%X) = %X\n", space.device().safe_pc(), offset, data);
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logerror("%06X:disk_asic_jr_r(%X)\n", space.device().safe_pc(), offset);
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break;
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}
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return retVal;
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}
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/* unknown purpose; crusnexo toggles this between 0 and 1 every 20 frames; thegrid writes 1 */
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WRITE32_MEMBER(midzeus_state::disk_asic_jr_w)
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{
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//uint32_t oldval = disk_asic_jr[offset];
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disk_asic_jr[offset] = data;
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switch (offset)
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{
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/* disk asic jr led; crusnexo toggles this between 0 and 1 every 20 frames; thegrid writes 1 */
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case 0:
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if (data != 0 && data != 1)
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logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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break;
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/* unknown purpose; mk4/invasn write 1 here at initialization; crusnexo/thegrid write 3 */
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/* miscellaneous hardware wait states; mk4/invasn write 1 here at initialization; crusnexo/thegrid write 3 */
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case 1:
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if (data != 1 && data != 3)
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logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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break;
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/* CMOS/ZPRAM extra enable latch; only low bit is used */
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/* CMOS/ZPRAM write enable; only low bit is used */
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case 2:
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break;
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/* reset status; bit 0 is watchdog reset; mk4/invasn/thegrid read at startup; invasn freaks if it is 1 at startup */
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case 3:
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break;
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/* unknown purpose; invasn writes 2 here at startup */
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case 4:
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if (data != 2)
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logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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break;
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/* ROM bank selection on Zeus 2 */
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case 5:
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membank("bank1")->set_entry(bitlatch[offset] & 3);
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membank("bank1")->set_entry(disk_asic_jr[offset] & 3);
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break;
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/* unknown purpose; crusnexo/thegrid write 1 at startup */
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/* zeus2 ws; 0=zeus access 1 wait state, 2=unlock roms; crusnexo/thegrid write 1 at startup */
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case 7:
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if (data != 1)
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logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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break;
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/* unknown purpose; crusnexo writes 4 at startup; thegrid writes 6 */
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/* romsize; crusnexo writes 4 at startup; thegrid writes 6 */
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case 8:
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if (data != 4 && data != 6)
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logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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break;
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/* unknown purpose; thegrid writes 1 at startup */
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/* trackball reset; thegrid writes 1 at startup */
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case 9:
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if (data != 1)
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logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data);
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break;
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/* unknown purpose */
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default:
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//if (oldval ^ data)
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logerror("%06X:disk_asic_jr_w(%X) = %X\n", space.device().safe_pc(), offset, data);
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break;
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}
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}
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@ -358,33 +449,75 @@ WRITE32_MEMBER(midzeus_state::crusnexo_leds_w)
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/*************************************
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*
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* Link controller access (Zeus 2 only)
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* Firewwire access (Zeus 2 only)
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*
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*************************************/
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// read 8d0003, check bit 1, skip some stuff if 0
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// write junk to 9e0000
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READ32_MEMBER(midzeus_state::linkram_r)
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READ32_MEMBER(midzeus_state::firewire_r)
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{
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logerror("%06X:unknown_8a000_r(%02X)\n", space.device().safe_pc(), offset);
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if (offset == 0)
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return 0x30313042;
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else if (offset == 0x3c)
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return 0xffffffff;
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else if (offset == 0x30)
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// ???
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return 0xffffffff;
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else if (offset == 0xc)
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// ???
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return 0xffffffff;
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return m_linkram[offset];
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uint32_t retVal = 0;
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if (offset < 0x40)
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retVal = m_firewire[offset / 4];
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switch (offset) {
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case 0:
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// Version
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retVal = 0x30313042;
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break;
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case 0x0c:
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// Interrupt
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retVal = 0xf4000000;// &m_firewire[0x10 / 4];
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break;
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case 0x30:
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// Asynchronous Transmit FIFO Status
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// 8:0 space available
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retVal = 0x1ff;
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break;
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case 0x3c:
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// General Rx FIFO Status
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// 0x80000000 = Empty
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// 0x40000000 = Control Data
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// 0x20000000 = Packet Complete
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retVal = 0x80000000;
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break;
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case 0xc0:
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// General Rx FIFO
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retVal = 0x0;
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break;
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}
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if LOG_FW logerror("%06X:firewire_r(%02X)=%08X\n", space.device().safe_pc(), offset, retVal);
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return retVal;
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}
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WRITE32_MEMBER(midzeus_state::linkram_w)
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WRITE32_MEMBER(midzeus_state::firewire_w)
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{
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logerror("%06X:unknown_8a000_w(%02X) = %08X\n", space.device().safe_pc(), offset, data);
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COMBINE_DATA(&m_linkram[offset]);
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// 0x08 // Control
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// Bit 0: Flush bad packets from Rx FIFO
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// Bit 6: IRP2En
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// Bit 7: IRP1En
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// Bit 8: TrgEn
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// Bit 20: Reset Rx
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// Bit 21: Reset Tx
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// Bit 22: Enable Acknowledge
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// Bit 23: Iso Rx Enable
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// Bit 24: Iso Rx Enable
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// Bit 25: Async Rx Enable
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// Bit 26: Async Tx Enable
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// Bit 30: Rx Self ID packets
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// Bit 31: Rx Packets adddressed to phy
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// 0x00200000 Reset Tx
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// 0x00100000 Reset Rx
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// 0x1c // FIFO Control
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// Bit 0:8: ITF Size
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// Bit 9:17: ATF Size
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// Bit 18:26 Trigger Size
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// Bit 29: Clear GRF
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// Bit 32: Clear ATF
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// 0x20 // Diagnostics
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// Bit 31: Enable Snooping
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if (offset < 0x40)
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COMBINE_DATA(&m_firewire[offset / 4]);
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if LOG_FW logerror("%06X:firewire_w(%02X) = %08X\n", space.device().safe_pc(), offset, data);
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}
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@ -469,6 +602,20 @@ CUSTOM_INPUT_MEMBER(midzeus_state::keypad_r)
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return bits;
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}
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READ32_MEMBER(midzeus_state::grid_keypad_r)
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{
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uint32_t bits = (ioport("KEYPAD")->read() >> ((offset >> 1) << 2)) & 0xf;
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return bits;
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}
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READ32_MEMBER(midzeus_state::trackball_r)
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{
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if (offset==0)
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return ioport("TRACKY1")->read();
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else
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return ioport("TRACKX1")->read();
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}
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/*************************************
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@ -587,7 +734,7 @@ static ADDRESS_MAP_START( zeus_map, AS_PROGRAM, 32, midzeus_state )
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AM_RANGE(0x400000, 0x41ffff) AM_RAM
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AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_SHARE("tms32031_ctl")
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AM_RANGE(0x880000, 0x8803ff) AM_READWRITE(zeus_r, zeus_w) AM_SHARE("zeusbase")
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AM_RANGE(0x8d0000, 0x8d0004) AM_READWRITE(bitlatches_r, bitlatches_w)
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AM_RANGE(0x8d0000, 0x8d0009) AM_READWRITE(disk_asic_jr_r, disk_asic_jr_w)
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AM_RANGE(0x990000, 0x99000f) AM_DEVREADWRITE("ioasic", midway_ioasic_device, read, write)
|
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AM_RANGE(0x9e0000, 0x9e0000) AM_WRITENOP // watchdog?
|
||||
AM_RANGE(0x9f0000, 0x9f7fff) AM_READWRITE(cmos_r, cmos_w) AM_SHARE("nvram")
|
||||
@ -602,11 +749,12 @@ static ADDRESS_MAP_START( zeus2_map, AS_PROGRAM, 32, midzeus2_state )
|
||||
AM_RANGE(0x400000, 0x43ffff) AM_RAM
|
||||
AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_SHARE("tms32031_ctl")
|
||||
AM_RANGE(0x880000, 0x88007f) AM_DEVREADWRITE("zeus2", zeus2_device, zeus2_r, zeus2_w)
|
||||
AM_RANGE(0x8a0000, 0x8a003f) AM_READWRITE(linkram_r, linkram_w) AM_SHARE("linkram")
|
||||
AM_RANGE(0x8d0000, 0x8d000a) AM_READWRITE(bitlatches_r, bitlatches_w)
|
||||
AM_RANGE(0x8a0000, 0x8a00cf) AM_READWRITE(firewire_r, firewire_w) AM_SHARE("firewire")
|
||||
AM_RANGE(0x8d0000, 0x8d0009) AM_READWRITE(disk_asic_jr_r, disk_asic_jr_w)
|
||||
AM_RANGE(0x900000, 0x91ffff) AM_READWRITE(zpram_r, zpram_w) AM_SHARE("nvram") AM_MIRROR(0x020000)
|
||||
AM_RANGE(0x990000, 0x99000f) AM_DEVREADWRITE("ioasic", midway_ioasic_device, read, write)
|
||||
AM_RANGE(0x9c0000, 0x9c000f) AM_READWRITE(analog_r, analog_w)
|
||||
AM_RANGE(0x9d0000, 0x9d000f) AM_READWRITE(disk_asic_r, disk_asic_w)
|
||||
AM_RANGE(0x9e0000, 0x9e0000) AM_WRITENOP // watchdog?
|
||||
AM_RANGE(0x9f0000, 0x9f7fff) AM_READWRITE(zeus2_timekeeper_r, zeus2_timekeeper_w)
|
||||
AM_RANGE(0x9f8000, 0x9f8000) AM_WRITE(cmos_protect_w)
|
||||
@ -1092,10 +1240,31 @@ static INPUT_PORTS_START( thegrid )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("49WAYX")
|
||||
PORT_BIT( 0xff, 0x38, IPT_AD_STICK_X ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10)
|
||||
PORT_BIT( 0xff, 0x38, IPT_AD_STICK_X ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE
|
||||
|
||||
PORT_START("49WAYY")
|
||||
PORT_BIT( 0xff, 0x38, IPT_AD_STICK_Y ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10)
|
||||
PORT_BIT( 0xff, 0x38, IPT_AD_STICK_Y ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE
|
||||
|
||||
PORT_START("KEYPAD")
|
||||
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 1") PORT_CODE(KEYCODE_1_PAD) /* keypad 1 */
|
||||
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 4") PORT_CODE(KEYCODE_4_PAD) /* keypad 4 */
|
||||
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 7") PORT_CODE(KEYCODE_7_PAD) /* keypad 7 */
|
||||
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad *") PORT_CODE(KEYCODE_MINUS_PAD) /* keypad * */
|
||||
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 2") PORT_CODE(KEYCODE_2_PAD) /* keypad 2 */
|
||||
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 5") PORT_CODE(KEYCODE_5_PAD) /* keypad 5 */
|
||||
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 8") PORT_CODE(KEYCODE_8_PAD) /* keypad 8 */
|
||||
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 0") PORT_CODE(KEYCODE_0_PAD) /* keypad 0 */
|
||||
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 3") PORT_CODE(KEYCODE_3_PAD) /* keypad 3 */
|
||||
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 6") PORT_CODE(KEYCODE_6_PAD) /* keypad 6 */
|
||||
PORT_BIT(0x400, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 9") PORT_CODE(KEYCODE_9_PAD) /* keypad 9 */
|
||||
PORT_BIT(0x800, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad #") PORT_CODE(KEYCODE_PLUS_PAD) /* keypad # */
|
||||
|
||||
PORT_START("TRACKX1")
|
||||
PORT_BIT(0xff, 0x00, IPT_TRACKBALL_X) PORT_SENSITIVITY(1) PORT_KEYDELTA(1) PORT_PLAYER(1)
|
||||
|
||||
PORT_START("TRACKY1")
|
||||
PORT_BIT(0xff, 0x00, IPT_TRACKBALL_Y) PORT_SENSITIVITY(1) PORT_KEYDELTA(1) PORT_REVERSE PORT_PLAYER(1)
|
||||
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
@ -1531,6 +1700,8 @@ DRIVER_INIT_MEMBER(midzeus_state,crusnexo)
|
||||
DRIVER_INIT_MEMBER(midzeus_state,thegrid)
|
||||
{
|
||||
membank("bank1")->configure_entries(0, 3, memregion("user2")->base(), 0x400000*4);
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8c0000, 0x8c0001, read32_delegate(FUNC(midzeus_state::trackball_r), this));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x9b0000, 0x9b0004, read32_delegate(FUNC(midzeus_state::grid_keypad_r), this));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -18,7 +18,7 @@ public:
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_nvram(*this, "nvram"),
|
||||
m_ram_base(*this, "ram_base"),
|
||||
m_linkram(*this, "linkram"),
|
||||
m_firewire(*this, "firewire"),
|
||||
m_tms32031_control(*this, "tms32031_ctl"),
|
||||
m_zeusbase(*this, "zeusbase") ,
|
||||
m_m48t35(*this, "m48t35"),
|
||||
@ -28,7 +28,7 @@ public:
|
||||
|
||||
required_shared_ptr<uint32_t> m_nvram;
|
||||
required_shared_ptr<uint32_t> m_ram_base;
|
||||
optional_shared_ptr<uint32_t> m_linkram;
|
||||
optional_shared_ptr<uint32_t> m_firewire;
|
||||
required_shared_ptr<uint32_t> m_tms32031_control;
|
||||
optional_shared_ptr<uint32_t> m_zeusbase;
|
||||
optional_device<timekeeper_device> m_m48t35;
|
||||
@ -43,12 +43,14 @@ public:
|
||||
DECLARE_WRITE32_MEMBER(cmos_protect_w);
|
||||
DECLARE_READ32_MEMBER(zpram_r);
|
||||
DECLARE_WRITE32_MEMBER(zpram_w);
|
||||
DECLARE_READ32_MEMBER(bitlatches_r);
|
||||
DECLARE_WRITE32_MEMBER(bitlatches_w);
|
||||
DECLARE_READ32_MEMBER(disk_asic_r);
|
||||
DECLARE_WRITE32_MEMBER(disk_asic_w);
|
||||
DECLARE_READ32_MEMBER(disk_asic_jr_r);
|
||||
DECLARE_WRITE32_MEMBER(disk_asic_jr_w);
|
||||
DECLARE_READ32_MEMBER(crusnexo_leds_r);
|
||||
DECLARE_WRITE32_MEMBER(crusnexo_leds_w);
|
||||
DECLARE_READ32_MEMBER(linkram_r);
|
||||
DECLARE_WRITE32_MEMBER(linkram_w);
|
||||
DECLARE_READ32_MEMBER(firewire_r);
|
||||
DECLARE_WRITE32_MEMBER(firewire_w);
|
||||
DECLARE_READ32_MEMBER(tms32031_control_r);
|
||||
DECLARE_WRITE32_MEMBER(tms32031_control_w);
|
||||
DECLARE_WRITE32_MEMBER(keypad_select_w);
|
||||
@ -60,8 +62,8 @@ public:
|
||||
DECLARE_WRITE32_MEMBER(zeus_w);
|
||||
DECLARE_CUSTOM_INPUT_MEMBER(custom_49way_r);
|
||||
DECLARE_CUSTOM_INPUT_MEMBER(keypad_r);
|
||||
DECLARE_READ32_MEMBER(zeus2_timekeeper_r);
|
||||
DECLARE_WRITE32_MEMBER(zeus2_timekeeper_w);
|
||||
DECLARE_READ32_MEMBER(grid_keypad_r);
|
||||
DECLARE_READ32_MEMBER(trackball_r);
|
||||
DECLARE_DRIVER_INIT(invasn);
|
||||
DECLARE_DRIVER_INIT(mk4);
|
||||
DECLARE_DRIVER_INIT(thegrid);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user