mirror of
https://github.com/holub/mame
synced 2025-04-24 01:11:11 +03:00
Fixed port mapping so that standalone iteagle doesn't crash.
Added serial port handling in fpga so that self-test (start==0 at power on) doesn't hang.
This commit is contained in:
ted green
parent
ece3a08e19
commit
352c2ab45a
@ -138,6 +138,14 @@ void iteagle_state::machine_reset()
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{
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}
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#define PCI_ID_IDE ":pci:06.0"
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// Primary IDE Control ":pci:06.1"
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// Seconday IDE Control ":pci:06.2"
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#define PCI_ID_SOUND ":pci:07.0"
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#define PCI_ID_FPGA ":pci:08.0"
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#define PCI_ID_VIDEO ":pci:09.0"
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#define PCI_ID_EEPROM ":pci:0a.0"
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static MACHINE_CONFIG_START( iteagle, iteagle_state )
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/* basic machine hardware */
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@ -147,91 +155,90 @@ static MACHINE_CONFIG_START( iteagle, iteagle_state )
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MCFG_PCI_ROOT_ADD( ":pci")
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MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu")
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MCFG_ITEAGLE_FPGA_ADD( ":pci:06.0")
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MCFG_ITEAGLE_IDE_ADD( ":pci:06.1")
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MCFG_ITEAGLE_IDE_ADD( PCI_ID_IDE)
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MCFG_ITEAGLE_IDE_IRQ_ADD( ":maincpu", MIPS3_IRQ2)
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MCFG_ES1373_ADD( ":pci:07.0")
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MCFG_SOUND_ROUTE(0, ":pci:07.0:lspeaker", 1.0)
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MCFG_SOUND_ROUTE(1, ":pci:07.0:rspeaker", 1.0)
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MCFG_ITEAGLE_FPGA_ADD( PCI_ID_FPGA, ":maincpu", MIPS3_IRQ1)
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MCFG_ES1373_ADD( PCI_ID_SOUND)
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MCFG_SOUND_ROUTE(0, PCI_ID_SOUND":lspeaker", 1.0)
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MCFG_SOUND_ROUTE(1, PCI_ID_SOUND":rspeaker", 1.0)
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MCFG_ES1373_IRQ_ADD( ":maincpu", MIPS3_IRQ3)
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MCFG_VOODOO_ADD( ":pci:09.0", ":maincpu")
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MCFG_ITEAGLE_EEPROM_ADD( ":pci:0a.0")
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MCFG_VOODOO_ADD( PCI_ID_VIDEO, ":maincpu")
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MCFG_ITEAGLE_EEPROM_ADD( PCI_ID_EEPROM)
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_REFRESH_RATE(59)
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MCFG_SCREEN_SIZE(512, 384)
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MCFG_SCREEN_UPDATE_DEVICE(":pci:09.0", voodoo_pci_device, screen_update)
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MCFG_SCREEN_UPDATE_DEVICE(PCI_ID_VIDEO, voodoo_pci_device, screen_update)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( gtfore01, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x01000401, 0x0b0b0b)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
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MCFG_ITEAGLE_EEPROM_INIT(0x0401, 0x7)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( gtfore02, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x01000402, 0x020201)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_ITEAGLE_EEPROM_INIT(0x0402, 0x7)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( gtfore03, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x01000403, 0x0a0b0a)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
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MCFG_ITEAGLE_EEPROM_INIT(0x0403, 0x7)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( gtfore04, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x01000404, 0x0a020b)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
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MCFG_ITEAGLE_EEPROM_INIT(0x0404, 0x7)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( gtfore05, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x01000405, 0x0b0a0c)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
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MCFG_ITEAGLE_EEPROM_INIT(0x0405, 0x7);
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( gtfore06, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x01000406, 0x0c0b0d)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_ITEAGLE_EEPROM_INIT(0x0406, 0x7);
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MCFG_ITEAGLE_EEPROM_INIT(0x0406, 0x9);
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( carnking, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x01000603, 0x0c0b0d)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_ITEAGLE_EEPROM_INIT(0x0603, 0x7)
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MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
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MCFG_ITEAGLE_EEPROM_INIT(0x0603, 0x9)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( bbhsc, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_ITEAGLE_FPGA_INIT(0x02000201, 0x0c0a0a)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_ITEAGLE_EEPROM_INIT(0x0201, 0x7)
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x01000600, 0x0c0a0a)
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MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
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MCFG_ITEAGLE_EEPROM_INIT(0x0600, 0x9)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( bbhcotw, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x02000603, 0x080704)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_ITEAGLE_EEPROM_INIT(0x0603, 0x7)
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MCFG_ITEAGLE_EEPROM_INIT(0x0603, 0x9)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( virtpool, iteagle )
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MCFG_DEVICE_MODIFY(":pci:06.0")
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x01000202, 0x0c0b0d)
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MCFG_DEVICE_MODIFY(":pci:0a.0")
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MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
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MCFG_ITEAGLE_EEPROM_INIT(0x0202, 0x7)
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MACHINE_CONFIG_END
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@ -252,11 +259,12 @@ static INPUT_PORTS_START( iteagle )
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PORT_START("IN1")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START1 )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "Left" )
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PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Right" )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "Left/Trigger" )
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PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Right/Pump" )
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PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME( "Fly By" )
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME( "Backspin" )
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PORT_BIT( 0x00c0, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNUSED )
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@ -282,32 +290,21 @@ static INPUT_PORTS_START( iteagle )
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PORT_DIPSETTING(0x4000, "High" )
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PORT_DIPSETTING(0x0000, "Not Detected" )
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INPUT_PORTS_END
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static INPUT_PORTS_START( gtfore )
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PORT_INCLUDE(iteagle)
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PORT_START("TRACKX1")
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PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_PLAYER(1)
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PORT_START("TRACKY1")
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PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_REVERSE PORT_PLAYER(1)
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INPUT_PORTS_END
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PORT_START("GUNX1")
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PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_SENSITIVITY(50) PORT_KEYDELTA(5)
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static INPUT_PORTS_START( carnking )
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PORT_INCLUDE(iteagle)
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PORT_START("TRACKX1")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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//PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(1) PORT_PLAYER(1)
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PORT_START("TRACKY1")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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//PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(1) PORT_PLAYER(1)
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PORT_START("GUNY1")
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PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_SENSITIVITY(50) PORT_KEYDELTA(5)
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INPUT_PORTS_END
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/*************************************
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*
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* ROM definition(s)
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@ -347,21 +344,21 @@ INPUT_PORTS_END
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ROM_LOAD( "e2-card1.u22.jed", 0x000000, 0x000bd1, CRC(9d1e1ace) SHA1(287d6a30e9f32137ef4eba54f0effa092c97a6eb) ) \
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ROM_LOAD( "e2-res3.u117.jed", 0x001000, 0x000bd1, CRC(4f1ff45a) SHA1(213cbdd6cd37ad9b5bfc9545084892a68d29f5ff) )
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ROM_START( iteagle )
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EAGLE_BIOS
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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//DISK_REGION( ":pci:06.1:ide:1:cdrom" ) // program CD-ROM
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//DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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//DISK_REGION( PCI_ID_IDE":ide2:1:cdrom" ) // program CD-ROM
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ROM_END
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ROM_START( virtpool ) /* On earlier Eagle 1 PCB, possibly a prototype version - later boards are known as Eagle 2 */
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EAGLE_BIOS
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "itvp-1.u53", 0x0000, 0x0880, NO_DUMP )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "virtualpool", 0, SHA1(be8f890c33701ca17fab8112ee6cd7b5e435d8cf) ) /* HD hand labeled 3-1-99 V.P. */
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ROM_END
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@ -371,7 +368,7 @@ ROM_START( carnking ) /* REQUIRES a "RED" board, will NOT work with earlier gree
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "ck1-us.u53", 0x0000, 0x0880, NO_DUMP )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "carnival_king_v_1.00.11", 0, SHA1(c819af66d36df173ab17bf42f4045c7cca3203d8) ) /* Labeled Carnival King V 1.00.11 */
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ROM_END
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@ -381,7 +378,7 @@ ROM_START( gtfore01 )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "e2-led0.u53", 0x0000, 0x0880, CRC(6ec86dc6) SHA1(01665ad6d92d2b8e917e33ca705fab9258766513) )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "golf_fore_v1.00.25", 0, SHA1(6dc445b982aee3bab93ade5c4f5d148471939ecc) ) /* Build 19:19:59, Sep 11 2000 */
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ROM_END
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@ -391,7 +388,7 @@ ROM_START( gtfore02 )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "g42-us-u.u53", 0x0000, 0x0880, CRC(06e0b452) SHA1(f6b865799cb94941e0e77453b9d556d5988b0194) )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "golf_fore_2002_v2.01.06", 0, SHA1(d1363bc17337c91684148b76fa1e73ac9dd80d8f) ) /* Build 11:27:20, Nov 5 2001 */
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ROM_END
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@ -401,7 +398,7 @@ ROM_START( gtfore03 )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "g43-us-u.u53", 0x0000, 0x0880, CRC(51c6f726) SHA1(9930337315128f89f7202893fb123ee3f0d33649) )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "golf_fore_2003_v3.00.10", 0, SHA1(d789ef86837a5012beb224c487537dd563d93886) ) /* Build 09:36:45, Nov 7 2002 */
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ROM_END
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@ -411,7 +408,7 @@ ROM_START( gtfore03a )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "g43-us-u.u53", 0x0000, 0x0880, CRC(51c6f726) SHA1(9930337315128f89f7202893fb123ee3f0d33649) )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "golf_fore_2003_v3.00.09", 0, SHA1(3c9cf82c3ad87b0d6b5a21089795abd8a08f8dd2) ) /* Build 09:36:45, Oct 17 2002 */
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ROM_END
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@ -421,7 +418,7 @@ ROM_START( gtfore04 )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "g44-us-u.u53", 0x0000, 0x0880, NO_DUMP )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "golf_fore_2004_v4.00.08", 0, SHA1(739a52d6ce13bb6ac7a543ee0e8086fb66be19b9) ) /* Build 14:15:44, Aug 27 2003 - Has been upgraded to Extra */
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ROM_END
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@ -431,7 +428,7 @@ ROM_START( gtfore04a )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "g44-us-u.u53", 0x0000, 0x0880, NO_DUMP )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "golf_fore_2004_v4.00.00", 0, SHA1(fe7525de89d67e0e3d10c48572fd04382543c19f) ) /* Build 16:40:59, Feb 28 2003 */
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ROM_END
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@ -441,7 +438,7 @@ ROM_START( gtfore05 )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "g45-us-u.u53", 0x0000, 0x0880, NO_DUMP )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "golf_fore_2005_v5.01.06", 0, SHA1(fa465263218d8e39102ec81d116c11447ef07e19) ) /* Build 10:55:49, Oct 27 2005 - Has been upgraded to Extra */
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ROM_END
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@ -451,7 +448,7 @@ ROM_START( gtfore05a )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "g45-us-u.u53", 0x0000, 0x0880, NO_DUMP )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "golf_fore_2005_v5.01.02", 0, SHA1(6e20d60fb7e9ab6bf0086267fa5b4329d8a9f468) ) /* Build 15:02:32, Feb 27 2004 - Has been upgraded to Extra */
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ROM_END
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@ -461,7 +458,7 @@ ROM_START( gtfore05b )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "g45-us-u.u53", 0x0000, 0x0880, NO_DUMP )
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DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
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DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
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DISK_IMAGE( "golf_fore_2005_v5.01.00", 0, SHA1(d8de569d8cf97b5aaada10ce896eb3c75f1b37f1) ) /* Build 12:30:35, Feb 16 2004 - Has been upgraded to Extra */
|
||||
ROM_END
|
||||
|
||||
@ -471,7 +468,7 @@ ROM_START( gtfore05c )
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "g45-us-u.u53", 0x0000, 0x0880, NO_DUMP )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
|
||||
DISK_IMAGE( "golf_fore_2005_v5.00.00", 0, SHA1(4236f57e639cae2e5a3eaa97fb24f5ff80557e84) ) /* Build 23:15:38, Jan 31 2004 - Has been upgraded to Extra */
|
||||
ROM_END
|
||||
|
||||
@ -481,7 +478,7 @@ ROM_START( gtfore06 )
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "g4c-us-u.u53", 0x0000, 0x0880, NO_DUMP )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
|
||||
DISK_IMAGE( "golf_fore_complete_v6.00.01", 0, SHA1(e902b91bd739daee0b95b10e5cf33700dd63a76b) ) /* Build 09:51:13, Jan 20 2006 */
|
||||
ROM_END
|
||||
|
||||
@ -491,7 +488,7 @@ ROM_START( bbhsc )
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "bb15-us.u53", 0x0000, 0x0880, NO_DUMP )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
|
||||
DISK_IMAGE( "bbhsc_v1.50.07_cf", 0, SHA1(21dcf1f7e5ab901ac64e6afb099c35e273b3bf1f) ) /* Build 16:35:34, Feb 26 2002 - 4gb Compact Flash conversion */
|
||||
ROM_END
|
||||
|
||||
@ -501,7 +498,7 @@ ROM_START( bbhcotw ) /* This version is meant for 8meg GREEN board PCBs */
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "cw-us-8.u53", 0x0000, 0x0880, CRC(c5234b58) SHA1(fb47b2233147a3f633f01edebef9994c358bd162) )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
|
||||
DISK_IMAGE( "bbhcotw_v3.02.05_cf", 0, SHA1(b1fcaab3a5aa51821673a914333c8868d36f77ae) ) /* Build 21:00:39, Sep 10 2006 - 4gb Compact Flash conversion */
|
||||
ROM_END
|
||||
|
||||
@ -511,19 +508,19 @@ ROM_END
|
||||
*
|
||||
*************************************/
|
||||
|
||||
GAME( 2000, iteagle, 0, iteagle, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Eagle BIOS", GAME_IS_BIOS_ROOT )
|
||||
GAME( 1998, virtpool, iteagle, virtpool, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Virtual Pool", GAME_NOT_WORKING )
|
||||
GAME( 2002, carnking, iteagle, carnking, carnking, driver_device, 0, ROT0, "Incredible Technologies", "Carnival King (v1.00.11)", GAME_NOT_WORKING )
|
||||
GAME( 2000, gtfore01, iteagle, gtfore01, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! (v1.00.25)", 0 )
|
||||
GAME( 2001, gtfore02, iteagle, gtfore02, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.01.06)", 0 )
|
||||
GAME( 2002, gtfore03, iteagle, gtfore03, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2003 (v3.00.10)", 0 )
|
||||
GAME( 2002, gtfore03a, gtfore03, gtfore03, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2003 (v3.00.09)", 0 )
|
||||
GAME( 2003, gtfore04, iteagle, gtfore04, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004 Extra (v4.00.08)", 0 )
|
||||
GAME( 2003, gtfore04a, gtfore04, gtfore04, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004 (v4.00.00)", 0 )
|
||||
GAME( 2004, gtfore05, iteagle, gtfore05, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.06)", 0 )
|
||||
GAME( 2004, gtfore05a, gtfore05, gtfore05, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.02)", 0 )
|
||||
GAME( 2004, gtfore05b, gtfore05, gtfore05, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.00)", 0 )
|
||||
GAME( 2004, gtfore05c, gtfore05, gtfore05, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.00.00)", 0 )
|
||||
GAME( 2005, gtfore06, iteagle, gtfore06, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2006 Complete (v6.00.01)", 0 )
|
||||
GAME( 2002, bbhsc, iteagle, bbhsc, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.50.07)", GAME_NOT_WORKING )
|
||||
GAME( 2006, bbhcotw, iteagle, bbhcotw, gtfore, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter Call of the Wild (v3.02.5)", GAME_NOT_WORKING )
|
||||
GAME( 2000, iteagle, 0, iteagle, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Eagle BIOS", GAME_IS_BIOS_ROOT )
|
||||
GAME( 1998, virtpool, iteagle, virtpool, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Virtual Pool", GAME_NOT_WORKING )
|
||||
GAME( 2002, carnking, iteagle, carnking, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Carnival King (v1.00.11)", GAME_NOT_WORKING )
|
||||
GAME( 2000, gtfore01, iteagle, gtfore01, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! (v1.00.25)", 0 )
|
||||
GAME( 2001, gtfore02, iteagle, gtfore02, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.01.06)", 0 )
|
||||
GAME( 2002, gtfore03, iteagle, gtfore03, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2003 (v3.00.10)", 0 )
|
||||
GAME( 2002, gtfore03a, gtfore03, gtfore03, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2003 (v3.00.09)", 0 )
|
||||
GAME( 2003, gtfore04, iteagle, gtfore04, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004 Extra (v4.00.08)", 0 )
|
||||
GAME( 2003, gtfore04a, gtfore04, gtfore04, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004 (v4.00.00)", 0 )
|
||||
GAME( 2004, gtfore05, iteagle, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.06)", 0 )
|
||||
GAME( 2004, gtfore05a, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.02)", 0 )
|
||||
GAME( 2004, gtfore05b, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.00)", 0 )
|
||||
GAME( 2004, gtfore05c, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.00.00)", 0 )
|
||||
GAME( 2005, gtfore06, iteagle, gtfore06, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2006 Complete (v6.00.01)", 0 )
|
||||
GAME( 2002, bbhsc, iteagle, bbhsc, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.50.07)", GAME_NOT_WORKING )
|
||||
GAME( 2006, bbhcotw, iteagle, bbhcotw, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter Call of the Wild (v3.02.5)", GAME_NOT_WORKING )
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
#define LOG_EEPROM (0)
|
||||
#define LOG_IDE (0)
|
||||
#define LOG_IDE_CTRL (0)
|
||||
|
||||
#define LOG_IDE_REG (0)
|
||||
|
||||
const device_type ITEAGLE_FPGA = &device_creator<iteagle_fpga_device>;
|
||||
|
||||
@ -39,35 +39,36 @@ void iteagle_fpga_device::device_start()
|
||||
add_map(sizeof(m_rtc_regs), M_MEM, FUNC(iteagle_fpga_device::rtc_map));
|
||||
// RTC defaults to base address 0x000c0000
|
||||
bank_infos[1].adr = 0x000c0000 & (~(bank_infos[1].size - 1));
|
||||
|
||||
m_timer = timer_alloc(0, NULL);
|
||||
m_timer->adjust(attotime::zero, 0, attotime::from_hz(25));
|
||||
}
|
||||
|
||||
void iteagle_fpga_device::device_reset()
|
||||
{
|
||||
m_cpu = machine().device<cpu_device>(m_cpu_tag);
|
||||
pci_device::device_reset();
|
||||
memset(m_fpga_regs, 0, sizeof(m_fpga_regs));
|
||||
//memset(m_rtc_regs, 0, sizeof(m_rtc_regs));
|
||||
//m_rtc_regs[0] = 0x11223344;
|
||||
m_seq = m_seq_init;
|
||||
m_seq_rem1 = 0;
|
||||
m_seq_rem2 = 0;
|
||||
|
||||
// 0x00&0x2 == 1 for boot
|
||||
//m_fpga_regs[0x00/4] = 0xC1110002; // 0xCF000002;// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
|
||||
//m_fpga_regs[0x00/4] = 0xC010ffff;
|
||||
// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
|
||||
// Bit 20 seems to be sw51 (operator mode) 0 = Normal, 1 = Operator Mode
|
||||
//m_fpga_regs[0x04/4] = 0x06060044; // Nibble starting at bit 20 is resolution, byte 0 is atmel response
|
||||
// 0x00080000 and interrupt starts reading from 0x14
|
||||
// 0x02000000 and interrupt starts reading from 0x18
|
||||
m_fpga_regs[0x04/4] = 0x00000000; // Nibble starting at bit 20 is resolution, byte 0 is atmel response
|
||||
//m_fpga_regs[0x308/4]=0x0000ffff; // Low 16 bits gets read alot?
|
||||
//m_fpga_regs[0x08/4]=0x0000ffff; // Low 16 bits is trackball
|
||||
m_prev_reg = 0;
|
||||
|
||||
m_serial_idx = 0;
|
||||
m_serial_data = false;
|
||||
m_serial_reg1c[0] = 0x2c;
|
||||
m_serial_reg1d[0] = 0x2c;
|
||||
}
|
||||
|
||||
void iteagle_fpga_device::update_sequence(UINT32 data)
|
||||
{
|
||||
UINT32 offset = 0x04/4;
|
||||
if (data & 0x80) {
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | (m_version>>(8*(data&3)));
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((m_version>>(8*(data&3)))&0xff);
|
||||
} else {
|
||||
UINT32 val1, feed;
|
||||
feed = ((m_seq<<4) ^ m_seq)>>7;
|
||||
@ -93,29 +94,64 @@ void iteagle_fpga_device::update_sequence(UINT32 data)
|
||||
}
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_timer - called when our device timer expires
|
||||
//-------------------------------------------------
|
||||
void iteagle_fpga_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
|
||||
{
|
||||
if (m_fpga_regs[0x4/4]&0x01000000) {
|
||||
//m_fpga_regs[0x04/4] |= 0x02080000;
|
||||
m_fpga_regs[0x04/4] |= 0x00000000;
|
||||
//m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga device_timer Setting interrupt(%i)\n", machine().describe_context(), m_irq_num);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
READ32_MEMBER( iteagle_fpga_device::fpga_r )
|
||||
{
|
||||
UINT32 result = m_fpga_regs[offset];
|
||||
|
||||
switch (offset) {
|
||||
case 0x00/4:
|
||||
result = ((machine().root_device().ioport("SYSTEM")->read()&0xffff)<<16) | (machine().root_device().ioport("IN1")->read()&0xffff);
|
||||
if (1 && LOG_FPGA)
|
||||
if (LOG_FPGA && m_prev_reg!=offset)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x04/4:
|
||||
result = (result & 0xFF0FFFFF) | ((machine().root_device().ioport("SW5")->read()&0xf)<<20);
|
||||
//if (1 && ACCESSING_BITS_0_7)
|
||||
if (1 && LOG_FPGA)
|
||||
result = (result & 0xFF0FFFFF) | ((machine().root_device().ioport("SW5")->read()&0xf)<<20);
|
||||
if (LOG_FPGA && !ACCESSING_BITS_0_7)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
|
||||
case 0x08/4:
|
||||
result = (result & 0xffff0000) | ((machine().root_device().ioport("TRACKY1")->read()&0xff)<<8) | (machine().root_device().ioport("TRACKX1")->read()&0xff);
|
||||
if (1 && LOG_FPGA && m_prev_reg != offset)
|
||||
//result = ((machine().root_device().ioport("GUNY1")->read()&0xff)<<8) | ((machine().root_device().ioport("GUNX1")->read()&0xff)<<0);
|
||||
result = ((machine().root_device().ioport("TRACKY1")->read()&0xff)<<8) | (machine().root_device().ioport("TRACKX1")->read()&0xff);
|
||||
if (LOG_FPGA && m_prev_reg!=offset)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x0c/4: // 1d = modem byte
|
||||
result = (result & 0xFFFF0000) | 0x2c2c;
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x14/4: // Interrupt & 0x4==0x00080000
|
||||
result = 0x00000000;
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x18/4: // Interrupt & 0x4==0x02000000
|
||||
result = 0x00000000;
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x1c/4: // 1d = modem byte
|
||||
result = (result & 0xFFFFFF00) | 0x04;
|
||||
result = (result & 0xFFFF0000) | ((m_serial_reg1d[m_serial_idx]&0xff)<<8) | (m_serial_reg1c[m_serial_idx]&0xff);
|
||||
if (ACCESSING_BITS_0_15) {
|
||||
m_serial_data = false;
|
||||
m_serial_idx = 0;
|
||||
}
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
@ -124,7 +160,8 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
}
|
||||
m_prev_reg = offset;
|
||||
if (offset!=0x4/4)
|
||||
m_prev_reg = offset;
|
||||
return result;
|
||||
}
|
||||
|
||||
@ -136,13 +173,54 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
|
||||
if (ACCESSING_BITS_0_7) {
|
||||
// ATMEL Chip access. Returns version id's when bit 7 is set.
|
||||
update_sequence(data & 0xff);
|
||||
if (1 && LOG_FPGA)
|
||||
if (0 && LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
// Interrupt clear/enable
|
||||
if (ACCESSING_BITS_24_31 && (data & 0x01000000)) {
|
||||
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X Clearing interrupt(%i)\n", machine().describe_context(), offset*4, data, mem_mask, m_irq_num);
|
||||
} else {
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
break;
|
||||
case 0x14/4:
|
||||
if (ACCESSING_BITS_0_7 && (data&0x1)) {
|
||||
m_fpga_regs[0x04/4] &= ~0x00080000;
|
||||
}
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
case 0x18/4:
|
||||
if (ACCESSING_BITS_0_7 && (data&0x1)) {
|
||||
m_fpga_regs[0x04/4] &= ~0x02000000;
|
||||
}
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
case 0x1c/4:
|
||||
if (ACCESSING_BITS_0_7) {
|
||||
if (!m_serial_data) {
|
||||
m_serial_idx = data&0xff;
|
||||
} else {
|
||||
m_serial_reg1c[m_serial_idx] = data&0xff;
|
||||
m_serial_idx = 0;
|
||||
}
|
||||
m_serial_data = !m_serial_data;
|
||||
}
|
||||
if (ACCESSING_BITS_8_15) {
|
||||
if (!m_serial_data) {
|
||||
m_serial_idx = (data&0xff00)>>8;
|
||||
} else {
|
||||
m_serial_reg1d[m_serial_idx] = (data&0xff00)>>8;
|
||||
}
|
||||
m_serial_data = !m_serial_data;
|
||||
}
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
default:
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
@ -249,8 +327,8 @@ ADDRESS_MAP_END
|
||||
// 0x7f = checksum
|
||||
static const UINT16 iteagle_default_eeprom[0x40] =
|
||||
{
|
||||
0x0000,0x0000,0x0000,0x0003,0x1209,0x1111,0x2222,0x1234,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0001,
|
||||
0xd000,0x0022,0x0000,0x0003,0x1209,0x1111,0x2222,0x1234,
|
||||
0x0000,0x0000,0x0000,0x0000,0xcd00,0x0000,0x0000,0x0001,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
@ -369,10 +447,10 @@ ADDRESS_MAP_END
|
||||
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( iteagle_ide )
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, NULL, "cdrom", true)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
|
||||
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(iteagle_ide_device, ide_interrupt))
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, "hdd", NULL, true)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, NULL, "cdrom", true)
|
||||
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(iteagle_ide_device, ide2_interrupt))
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
|
||||
MACHINE_CONFIG_END
|
||||
@ -405,21 +483,20 @@ void iteagle_ide_device::device_start()
|
||||
bank_infos[0].adr = 0x000;
|
||||
|
||||
add_map(0x8, M_IO, FUNC(iteagle_ide_device::ide_map));
|
||||
bank_infos[1].adr = 0x170;
|
||||
bank_infos[1].adr = 0x1f0;
|
||||
add_map(0x4, M_IO, FUNC(iteagle_ide_device::ide_ctrl_map));
|
||||
bank_infos[2].adr = 0x374;
|
||||
bank_infos[2].adr = 0x3f4;
|
||||
add_map(0x8, M_IO, FUNC(iteagle_ide_device::ide2_map));
|
||||
bank_infos[3].adr = 0x1f0;
|
||||
bank_infos[3].adr = 0x170;
|
||||
add_map(0x4, M_IO, FUNC(iteagle_ide_device::ide2_ctrl_map));
|
||||
bank_infos[4].adr = 0x3f4;
|
||||
bank_infos[4].adr = 0x374;
|
||||
}
|
||||
|
||||
void iteagle_ide_device::device_reset()
|
||||
{
|
||||
pci_device::device_reset();
|
||||
memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs));
|
||||
// 0x23 & 0x20 = IDE LED
|
||||
m_ctrl_regs[0x10/4] = 0x00000000; // 0x6=No SIMM, 0x2, 0x0 = SIMM
|
||||
m_ctrl_regs[0x10/4] = 0x00000000; // 0x6=No SIMM, 0x2, 0x1, 0x0 = SIMM . Top 16 bits are compared to 0x3.
|
||||
}
|
||||
|
||||
READ32_MEMBER( iteagle_ide_device::ctrl_r )
|
||||
@ -427,11 +504,11 @@ READ32_MEMBER( iteagle_ide_device::ctrl_r )
|
||||
UINT32 result = m_ctrl_regs[offset];
|
||||
switch (offset) {
|
||||
case 0x0/4:
|
||||
if (LOG_IDE_CTRL)
|
||||
if (LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
default:
|
||||
if (LOG_IDE_CTRL)
|
||||
if (LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
}
|
||||
@ -442,22 +519,22 @@ WRITE32_MEMBER( iteagle_ide_device::ctrl_w )
|
||||
{
|
||||
COMBINE_DATA(&m_ctrl_regs[offset]);
|
||||
switch (offset) {
|
||||
case 0x20/4: // IDE LED and ??
|
||||
case 0x20/4: // IDE LED
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
// Probably watchdog
|
||||
if (1 && LOG_IDE_CTRL)
|
||||
// Sets register index
|
||||
if (LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
} else if (ACCESSING_BITS_24_31) {
|
||||
// Bit 25 is IDE LED
|
||||
if (1 && LOG_IDE_CTRL)
|
||||
if (1 && LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
} else {
|
||||
if (LOG_IDE_CTRL)
|
||||
if (LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (LOG_IDE_CTRL)
|
||||
if (LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
}
|
||||
@ -467,8 +544,7 @@ READ32_MEMBER( iteagle_ide_device::ide_r )
|
||||
{
|
||||
UINT32 result = m_ide->read_cs0(space, offset, mem_mask);
|
||||
if (offset==0x4/4 && ACCESSING_BITS_24_31) {
|
||||
//result = 0;
|
||||
if ((m_irq_num!=-1) && m_ctrl_regs[0x20/4]&0x80000000) {
|
||||
if (m_irq_num!=-1) {
|
||||
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
|
||||
if (LOG_IDE)
|
||||
logerror("%s:ide_interrupt Clearing interrupt\n", machine().describe_context());
|
||||
@ -499,8 +575,7 @@ WRITE32_MEMBER( iteagle_ide_device::ide_ctrl_w )
|
||||
}
|
||||
WRITE_LINE_MEMBER(iteagle_ide_device::ide_interrupt)
|
||||
{
|
||||
//cpu_device *m_cpu = machine().device<cpu_device>(":maincpu");
|
||||
if ((m_irq_num!=-1) && m_ctrl_regs[0x20/4]&0x80000000) {
|
||||
if (m_irq_num!=-1) {
|
||||
m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:ide_interrupt Setting interrupt\n", machine().describe_context());
|
||||
@ -511,7 +586,7 @@ READ32_MEMBER( iteagle_ide_device::ide2_r )
|
||||
{
|
||||
UINT32 result = m_ide2->read_cs0(space, offset, mem_mask);
|
||||
if (offset==0x4/4 && ACCESSING_BITS_24_31) {
|
||||
if ((m_irq_num!=-1) && m_ctrl_regs[0x20/4]&0x40000000) {
|
||||
if (m_irq_num!=-1) {
|
||||
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:ide2_interrupt Clearing interrupt\n", machine().describe_context());
|
||||
@ -542,7 +617,7 @@ WRITE32_MEMBER( iteagle_ide_device::ide2_ctrl_w )
|
||||
}
|
||||
WRITE_LINE_MEMBER(iteagle_ide_device::ide2_interrupt)
|
||||
{
|
||||
if ((m_irq_num!=-1) &&m_ctrl_regs[0x20/4]&0x40000000) {
|
||||
if (m_irq_num!=-1) {
|
||||
m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:ide2_interrupt Setting interrupt\n", machine().describe_context());
|
||||
|
||||
@ -10,20 +10,21 @@
|
||||
#include "machine/idectrl.h"
|
||||
#include "machine/eepromser.h"
|
||||
|
||||
#define MCFG_ITEAGLE_FPGA_ADD(_tag) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_FPGA, 0x55CC33AA, 0xAA, 0xAAAAAA, 0x00)
|
||||
#define MCFG_ITEAGLE_FPGA_ADD(_tag, _cpu_tag, _irq_num) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_FPGA, 0x55CC33AA, 0xAA, 0xAAAAAA, 0x00) \
|
||||
downcast<iteagle_fpga_device *>(device)->set_irq_info(_cpu_tag, _irq_num);
|
||||
|
||||
#define MCFG_ITEAGLE_FPGA_INIT(_version, _seq_init) \
|
||||
downcast<iteagle_fpga_device *>(device)->set_init_info(_version, _seq_init);
|
||||
|
||||
#define MCFG_ITEAGLE_EEPROM_ADD(_tag) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_EEPROM, 0xAABBCCDD, 0x00, 0x088000, 0x00)
|
||||
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_EEPROM, 0x80861229, 0x00, 0x088000, 0x00)
|
||||
|
||||
#define MCFG_ITEAGLE_EEPROM_INIT(_sw_version, _hw_version) \
|
||||
downcast<iteagle_eeprom_device *>(device)->set_info(_sw_version, _hw_version);
|
||||
|
||||
#define MCFG_ITEAGLE_IDE_ADD(_tag) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_IDE, 0x11223344, 0x00, 0x010100, 0x00)
|
||||
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_IDE, 0x1080C693, 0x00, 0x060100, 0x00)
|
||||
|
||||
#define MCFG_ITEAGLE_IDE_IRQ_ADD(_cpu_tag, _irq_num) \
|
||||
downcast<iteagle_ide_device *>(device)->set_irq_info(_cpu_tag, _irq_num);
|
||||
@ -34,10 +35,13 @@ class iteagle_fpga_device : public pci_device,
|
||||
public:
|
||||
iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
void set_init_info(int version, int seq_init) {m_version=version; m_seq_init=seq_init;}
|
||||
void set_irq_info(const char *tag, const int irq_num) {m_cpu_tag = tag; m_irq_num = irq_num;}
|
||||
|
||||
|
||||
protected:
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
|
||||
// device_nvram_interface overrides
|
||||
virtual void nvram_default();
|
||||
@ -45,11 +49,20 @@ protected:
|
||||
virtual void nvram_write(emu_file &file);
|
||||
|
||||
private:
|
||||
|
||||
emu_timer * m_timer;
|
||||
const char *m_cpu_tag;
|
||||
cpu_device *m_cpu;
|
||||
int m_irq_num;
|
||||
|
||||
UINT32 m_fpga_regs[0x20];
|
||||
UINT32 m_rtc_regs[0x200];
|
||||
UINT32 m_prev_reg;
|
||||
|
||||
UINT8 m_serial_idx;
|
||||
bool m_serial_data;
|
||||
UINT8 m_serial_reg1c[0x10];
|
||||
UINT8 m_serial_reg1d[0x10];
|
||||
|
||||
UINT32 m_version;
|
||||
UINT32 m_seq_init;
|
||||
UINT32 m_seq;
|
||||
@ -81,7 +94,7 @@ protected:
|
||||
private:
|
||||
UINT16 m_sw_version;
|
||||
UINT8 m_hw_version;
|
||||
|
||||
|
||||
DECLARE_ADDRESS_MAP(eeprom_map, 32);
|
||||
DECLARE_READ32_MEMBER( eeprom_r );
|
||||
DECLARE_WRITE32_MEMBER( eeprom_w );
|
||||
|
||||
Loading…
Reference in New Issue
Block a user