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misc: set_clock_scale takes a double, not a float

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hap 2025-01-21 12:36:20 +01:00
parent d7ff151c24
commit 3588c0a8cb
12 changed files with 77 additions and 66 deletions
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32
src/mame/acorn/electron_m.cpp
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@ -142,7 +142,7 @@ uint8_t electron_state::electron_mem_r(offs_t offset)
{
case 0x00: /* Normal */
/* The processor will run at 1MHz during an access cycle to the RAM */
m_maincpu->set_clock_scale(0.5f);
m_maincpu->set_clock_scale(0.5);
waitforramsync();
break;
@ -167,7 +167,7 @@ void electron_state::electron_mem_w(offs_t offset, uint8_t data)
{
case 0x00: /* Normal */
/* The processor will run at 1MHz during an access cycle to the RAM */
m_maincpu->set_clock_scale(0.5f);
m_maincpu->set_clock_scale(0.5);
waitforramsync();
break;
@ -204,7 +204,7 @@ uint8_t electron_state::electron_paged_r(offs_t offset)
uint8_t data = 0;
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
switch (m_ula.rompage)
{
@ -237,7 +237,7 @@ uint8_t electron_state::electron_paged_r(offs_t offset)
void electron_state::electron_paged_w(offs_t offset, uint8_t data)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
m_exp->expbus_w(0x8000 + offset, data);
}
@ -247,7 +247,7 @@ uint8_t electronsp_state::electron_paged_r(offs_t offset)
uint8_t data = 0;
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
if ((m_ula.rompage & 0x0e) == m_rompages->read())
{
@ -280,7 +280,7 @@ uint8_t electronsp_state::electron_paged_r(offs_t offset)
void electronsp_state::electron_paged_w(offs_t offset, uint8_t data)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
if ((m_ula.rompage & 0x0e) == m_rompages->read())
{
@ -308,7 +308,7 @@ void electronsp_state::electron_paged_w(offs_t offset, uint8_t data)
uint8_t electron_state::electron_mos_r(offs_t offset)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
return m_region_mos->base()[0x4000 | offset];
}
@ -316,7 +316,7 @@ uint8_t electron_state::electron_mos_r(offs_t offset)
void electron_state::electron_mos_w(offs_t offset, uint8_t data)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
logerror("MOS: write %04x %02x\n", offset + 0xc000, data);
m_exp->expbus_w(0xc000 + offset, data);
@ -325,7 +325,7 @@ void electron_state::electron_mos_w(offs_t offset, uint8_t data)
uint8_t electron_state::electron_fred_r(offs_t offset)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
/* The Issue 4 ULA returns data from OS ROM, whereas Issue 6 ULA will return 0xff */
//logerror("FRED: read fc%02x\n", offset);
@ -335,7 +335,7 @@ uint8_t electron_state::electron_fred_r(offs_t offset)
void electron_state::electron_fred_w(offs_t offset, uint8_t data)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
/* Master RAM Board */
if (offset == 0x7f) m_mrb_mapped = !(data & 0x80);
@ -349,7 +349,7 @@ uint8_t electronsp_state::electron_fred_r(offs_t offset)
uint8_t data = 0;
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
if ((offset & 0xf0) == 0xb0)
{
@ -365,7 +365,7 @@ uint8_t electronsp_state::electron_fred_r(offs_t offset)
void electronsp_state::electron_fred_w(offs_t offset, uint8_t data)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
electron_state::electron_fred_w(offset, data);
@ -382,7 +382,7 @@ void electronsp_state::electron_fred_w(offs_t offset, uint8_t data)
uint8_t electron_state::electron_jim_r(offs_t offset)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
/* The Issue 4 ULA returns data from OS ROM, whereas Issue 6 ULA will return 0xff */
//logerror("JIM: read fd%02x\n", offset);
@ -392,7 +392,7 @@ uint8_t electron_state::electron_jim_r(offs_t offset)
void electron_state::electron_jim_w(offs_t offset, uint8_t data)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
//logerror("JIM: write fd%02x\n", offset);
m_exp->expbus_w(0xfd00 + offset, data);
@ -401,7 +401,7 @@ void electron_state::electron_jim_w(offs_t offset, uint8_t data)
uint8_t electron_state::electron_sheila_r(offs_t offset)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
/* The Issue 4 ULA returns data from OS ROM, whereas Issue 6 ULA will return 0xfe */
uint8_t data = 0xff;
@ -430,7 +430,7 @@ static const int electron_mode_end[8] = { 255, 255, 255 ,249 ,255, 255, 249, 249
void electron_state::electron_sheila_w(offs_t offset, uint8_t data)
{
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
m_exp->expbus_w(0xfe00 + offset, data);

3
src/mame/capcom/cps2.cpp
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@ -10975,7 +10975,8 @@ void cps2_state::init_cps2nc()
init_digital_volume();
m_maincpu->set_clock_scale(0.7375f); // RAM access waitstates etc. aren't emulated - slow the CPU to compensate
// HACK: RAM access waitstates etc. aren't emulated - slow the CPU to compensate
m_maincpu->set_clock_scale(0.7375);
}
void cps2_state::init_pzloop2()

2
src/mame/dataeast/backfire.cpp
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@ -593,7 +593,7 @@ void backfire_state::init_backfire()
deco56_decrypt_gfx(machine(), "tiles1"); /* 141 */
deco56_decrypt_gfx(machine(), "tiles2"); /* 141 */
deco156_decrypt(machine());
m_maincpu->set_clock_scale(4.0f); /* core timings aren't accurate */
m_maincpu->set_clock_scale(4.0); /* core timings aren't accurate */
descramble_sound();
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0170018, 0x017001b, read32smo_delegate(*this, FUNC(backfire_state::backfire_speedup_r)));
}

4
src/mame/dataeast/deco_mlc.cpp
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@ -1057,7 +1057,7 @@ void deco_mlc_state::init_mlc()
/* The timing in the ARM core isn't as accurate as it should be, so bump up the
effective clock rate here to compensate otherwise we have slowdowns in
Skull Fang where there probably shouldn't be. */
m_maincpu->set_clock_scale(2.0f);
m_maincpu->set_clock_scale(2.0);
m_irqLevel = ARM_IRQ_LINE;
deco156_decrypt(machine());
descramble_sound();
@ -1065,7 +1065,7 @@ void deco_mlc_state::init_mlc()
void deco_mlc_state::init_acchi() // sound ROMs don't appear to be scrambled
{
m_maincpu->set_clock_scale(2.0f); // avoids hangs in attract mode / end of round, see init_mlc()
m_maincpu->set_clock_scale(2.0); // avoids hangs in attract mode / end of round, see init_mlc()
m_irqLevel = ARM_IRQ_LINE;
deco156_decrypt(machine());
}

11
src/mame/hegenerglaser/excalibur.cpp
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@ -83,6 +83,9 @@ public:
void excal(machine_config &config);
protected:
virtual void machine_start() override ATTR_COLD;
private:
required_device<cpu_device> m_maincpu;
required_device<ptm6840_device> m_ptm;
@ -97,6 +100,12 @@ private:
u8 input_r(offs_t offset);
};
void excal_state::machine_start()
{
// HACK: slow down CPU to account for suspected wait states
m_maincpu->set_clock_scale(5.0 / 8.0);
}
/*******************************************************************************
@ -191,7 +200,7 @@ INPUT_PORTS_END
void excal_state::excal(machine_config &config)
{
// basic machine hardware
M68000(config, m_maincpu, 16_MHz_XTAL / 3.2); // see driver notes
M68000(config, m_maincpu, 16_MHz_XTAL / 2);
m_maincpu->set_addrmap(AS_PROGRAM, &excal_state::excal_mem);
PTM6840(config, m_ptm, 16_MHz_XTAL / 20);

8
src/mame/homebrew/z80clock.cpp
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@ -85,7 +85,7 @@ public:
m_speaker->add_route(ALL_OUTPUTS, "mono", 0.25);
CLOCK(config, m_ne555, 8589).signal_handler().set(FUNC(z80clock_state::ne555));
m_ne555->set_clock_scale(0.0f);
m_ne555->set_clock_scale(0.0);
m_ne555->set_duty_cycle(2/3.0f);
Z80CTC(config, m_ctc, 6_MHz_XTAL);
@ -155,7 +155,7 @@ protected:
virtual void machine_reset() override
{
/// HACK: start the sio clock on first write for speed
m_sio_clock->set_clock_scale(0.0f);
m_sio_clock->set_clock_scale(0.0);
}
private:
@ -224,7 +224,7 @@ private:
void outputs_w(uint8_t data)
{
m_ne555->set_clock_scale(BIT(data, 7) ? 1.0f : 0.0f);
m_ne555->set_clock_scale(BIT(data, 7) ? 1.0 : 0.0);
}
void disp_data_w(uint8_t data)
@ -304,7 +304,7 @@ private:
void sio_cd_ba_w(offs_t offset, uint8_t data)
{
/// HACK: start the sio clock on first write for speed
m_sio_clock->set_clock_scale(1.0f);
m_sio_clock->set_clock_scale(1.0);
m_sio->cd_ba_w(offset, data);
}

13
src/mame/konami/konamigx.cpp
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@ -561,7 +561,7 @@ void konamigx_state::control_w(offs_t offset, uint32_t data, uint32_t mem_mask)
TIMER_CALLBACK_MEMBER(konamigx_state::boothack_callback)
{
// Restore main CPU normal operating frequency
m_maincpu->set_clock_scale(1.0f);
m_maincpu->set_clock_scale(1.0);
}
/*
@ -3890,7 +3890,7 @@ MACHINE_RESET_MEMBER(konamigx_state,konamigx)
// waiting for the sound system tests to complete.
// To hack around this, we underclock the 68020 for 12 seconds during POST (soccerss requires longest)
m_maincpu->set_clock_scale(0.66f);
m_maincpu->set_clock_scale(2.0 / 3.0);
m_boothack_timer->adjust(attotime::from_seconds(12));
}
@ -3925,15 +3925,16 @@ static const GXGameInfoT gameDefs[] =
{ "le2", 13, 1, BPP4 },
{ "le2u", 13, 1, BPP4 },
{ "le2j", 13, 1, BPP4 },
{ "gokuparo", 7, 0, BPP5 },
{ "fantjour", 7, 9, BPP5 },
{ "fantjoura", 7, 9, BPP5 },
{ "gokuparo", 7, 0, BPP5 },
{ "crzcross", 7, 0, BPP5 },
{ "puzldama", 7, 0, BPP5 },
{ "mtwinbee", 7, 8, BPP5 },
{ "tbyahhoo", 7, 8, BPP5 },
{ "mtwinbee", 7, 8, BPP5 },
{ "tkmmpzdm", 7, 2, BPP6 },
{ "dragoonj", 7, 3, BPP4 },
{ "dragoona", 7, 3, BPP4 },
{ "dragoonj", 7, 3, BPP4 },
{ "sexyparo", 7, 4, BPP5 },
{ "sexyparoa", 7, 4, BPP5 },
{ "daiskiss", 7, 5, BPP5 },
@ -3949,10 +3950,10 @@ static const GXGameInfoT gameDefs[] =
{ "soccerssj", 7, 0, BPP4 },
{ "soccerssja",7, 0, BPP4 },
{ "vsnetscr", 7, 0, BPP4 },
{ "vsnetscreb",7, 0, BPP4 },
{ "vsnetscru", 7, 0, BPP4 },
{ "vsnetscrj", 7, 0, BPP4 },
{ "vsnetscra", 7, 0, BPP4 },
{ "vsnetscreb",7, 0, BPP4 },
{ "rungun2", 7, 0, BPP4 },
{ "slamdnk2", 7, 0, BPP4 },
{ "rushhero", 7, 0, BPP4 },

2
src/mame/sega/megacd.cpp
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@ -1790,7 +1790,7 @@ void sega_segacd_device::device_reset()
// time. Changing the CDHock timer to 50hz from 75hz also stops the hang, but then the video is
// too slow and has bad sound. -- Investigate!
// Update: removed, otherwise megacdj and megacd2j will black screen with no cdrom inserted.
//m_scdcpu->set_clock_scale(1.5000f);
//m_scdcpu->set_clock_scale(1.5);
// initialize some stuff on reset

4
src/mame/sega/segas24.cpp
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@ -641,7 +641,7 @@ CPUs to worry about.
TIMER_CALLBACK_MEMBER(segas24_state::gground_hack_timer_callback)
{
m_subcpu->set_clock_scale(1.0f);
m_subcpu->set_clock_scale(1.0);
}
@ -660,7 +660,7 @@ void segas24_state::cnt1(int state)
//machine().debug_break();
if (m_gground_hack_timer)
{
m_subcpu->set_clock_scale(0.7f); // reduce clock speed temporarily so a check passes, see notes above
m_subcpu->set_clock_scale(0.7); // reduce clock speed temporarily so a check passes, see notes above
m_gground_hack_timer->adjust(attotime::from_seconds(2));
}
}

2
src/mame/tch/littlerb.cpp
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@ -331,7 +331,7 @@ void littlerb_state::init_littlerb()
{
/* various scenes flicker to the point of graphics being invisible (eg. the map screen at the very start of a game)
unless you overclock the TMS34010 to 120%, possible timing bug in the core? this is a hack */
m_indervid->subdevice<cpu_device>("tms")->set_clock_scale(1.2f);
m_indervid->subdevice<cpu_device>("tms")->set_clock_scale(1.2);
}
} // anonymous namespace

2
src/mame/tvgames/spg2xx_wiwi.cpp
View File

@ -156,7 +156,7 @@ void spg2xx_game_marc250_state::machine_start()
m_pulse_timer2->adjust(attotime::never);
// hack, makes x-racer3 and some others more stable, TODO: find out what is really wrong
m_maincpu->set_clock_scale(2.0000f);
m_maincpu->set_clock_scale(2.0);
}

6
src/mame/vtech/socrates.cpp
View File

@ -383,7 +383,7 @@ void socrates_state::init_socrates()
/* fill vram with its init powerup bit pattern, so startup has the checkerboard screen */
for (int i = 0; i < 0x10000; i++)
m_vram_reg[i] = (((i&0x1)?0x00:0xFF)^((i&0x100)?0x00:0xff));
m_maincpu->set_clock_scale(0.45f); /// TODO: RAM access waitstates etc. aren't emulated - slow the CPU to compensate
m_maincpu->set_clock_scale(0.45); /// TODO: RAM access waitstates etc. aren't emulated - slow the CPU to compensate
m_kbmcu_type = 0;
}
@ -392,7 +392,7 @@ void socrates_state::init_iqunlimz()
/* fill vram with its init powerup bit pattern, so startup has the checkerboard screen... is this even right for the iqunlimz? */
for (int i = 0; i < 0x20000; i++)
m_vram_reg[i] = (((i&0x1)?0x00:0xFF)^((i&0x100)?0x00:0xff));
//m_maincpu->set_clock_scale(0.45f); /// TODO: RAM access waitstates etc. aren't emulated - slow the CPU to compensate
//m_maincpu->set_clock_scale(0.45); /// TODO: RAM access waitstates etc. aren't emulated - slow the CPU to compensate
m_kbmcu_type = 1;
}
@ -401,7 +401,7 @@ void socrates_state::init_vpainter()
/* fill vram with its init powerup bit pattern, so startup has the checkerboard screen */
for (int i = 0; i < 0x10000; i++)
m_vram_reg[i] = (((i&0x1)?0x00:0xFF)^((i&0x100)?0x00:0xff));
m_maincpu->set_clock_scale(0.45f); /// TODO: RAM access waitstates etc. aren't emulated - slow the CPU to compensate
m_maincpu->set_clock_scale(0.45); /// TODO: RAM access waitstates etc. aren't emulated - slow the CPU to compensate
m_kbmcu_type = 2;
}