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minx.c: Modernized cpu core (nw)

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This commit is contained in:
Wilbert Pol 2013-07-31 14:35:21 +00:00
parent 83fe9c0837
commit 35ebecfd76
6 changed files with 1774 additions and 1058 deletions
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340
src/emu/cpu/minx/minx.c
View File

@ -65,98 +65,106 @@ TODO:
#define EXEC_01 0x01
struct minx_state {
// MINX_CONFIG config;
UINT16 PC;
UINT16 SP;
UINT16 BA;
UINT16 HL;
UINT16 X;
UINT16 Y;
UINT8 U;
UINT8 V;
UINT8 F;
UINT8 E;
UINT8 N;
UINT8 I;
UINT8 XI;
UINT8 YI;
UINT8 halted;
UINT8 interrupt_pending;
device_irq_acknowledge_callback irq_callback;
legacy_cpu_device *device;
address_space *program;
int icount;
};
#define RD(offset) m_program->read_byte( offset )
#define WR(offset,data) m_program->write_byte( offset, data )
#define GET_MINX_PC ( ( m_PC & 0x8000 ) ? ( m_V << 15 ) | (m_PC & 0x7FFF ) : m_PC )
#define RD(offset) minx->program->read_byte( offset )
#define WR(offset,data) minx->program->write_byte( offset, data )
#define GET_MINX_PC ( ( minx->PC & 0x8000 ) ? ( minx->V << 15 ) | (minx->PC & 0x7FFF ) : minx->PC )
INLINE minx_state *get_safe_token(device_t *device)
const device_type MINX = &device_creator<minx_cpu_device>;
minx_cpu_device::minx_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, MINX, "Nintendo Minx", tag, owner, clock, "minx", __FILE__)
, m_program_config("program", ENDIANNESS_BIG, 8, 24, 0)
{
assert(device != NULL);
assert(device->type() == MINX);
return (minx_state *)downcast<legacy_cpu_device *>(device)->token();
}
INLINE UINT16 rd16( minx_state *minx, UINT32 offset )
UINT16 minx_cpu_device::rd16( UINT32 offset )
{
return RD( offset ) | ( RD( offset + 1 ) << 8 );
}
INLINE void wr16( minx_state *minx, UINT32 offset, UINT16 data )
void minx_cpu_device::wr16( UINT32 offset, UINT16 data )
{
WR( offset, ( data & 0x00FF ) );
WR( offset + 1, ( data >> 8 ) );
}
static CPU_INIT( minx )
void minx_cpu_device::device_start()
{
minx_state *minx = get_safe_token(device);
minx->irq_callback = irqcallback;
minx->device = device;
minx->program = &device->space(AS_PROGRAM);
if ( device->static_config() != NULL )
{
}
else
m_program = &space(AS_PROGRAM);
state_add( MINX_PC, "PC", m_PC ).formatstr("%04X");
state_add( MINX_SP, "SP", m_SP ).formatstr("%04X");
state_add( MINX_BA, "BA", m_BA ).formatstr("%04X");
state_add( MINX_HL, "HL", m_HL ).formatstr("%04X");
state_add( MINX_X, "X", m_X ).formatstr("%04X");
state_add( MINX_Y, "Y", m_Y ).formatstr("%04X");
state_add( MINX_U, "U", m_U ).formatstr("%02X");
state_add( MINX_V, "V", m_V ).formatstr("%02X");
state_add( MINX_F, "F", m_F ).formatstr("%02X");
state_add( MINX_E, "E", m_E ).formatstr("%02X");
state_add( MINX_N, "N", m_N ).formatstr("%02X");
state_add( MINX_I, "I", m_I ).formatstr("%02X");
state_add( MINX_XI, "XI", m_XI ).formatstr("%02X");
state_add( MINX_YI, "YI", m_YI ).formatstr("%02X");
state_add(STATE_GENPC, "curpc", m_curpc).formatstr("%06X").noshow();
state_add(STATE_GENFLAGS, "GENFLAGS", m_flags).formatstr("%14s").noshow();
m_icountptr = &m_icount;
}
void minx_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
{
switch (entry.index())
{
case STATE_GENFLAGS:
string.printf( "%c%c%c%c%c%c%c%c-%c%c%c%c%c",
m_F & FLAG_I ? 'I' : '.',
m_F & FLAG_D ? 'D' : '.',
m_F & FLAG_L ? 'L' : '.',
m_F & FLAG_B ? 'B' : '.',
m_F & FLAG_S ? 'S' : '.',
m_F & FLAG_O ? 'O' : '.',
m_F & FLAG_C ? 'C' : '.',
m_F & FLAG_Z ? 'Z' : '.',
m_E & EXEC_X0 ? '0' : '.',
m_E & EXEC_X1 ? '1' : '.',
m_E & EXEC_X2 ? '2' : '.',
m_E & EXEC_DZ ? 'z' : '.',
m_E & EXEC_EN ? 'E' : '.' );
break;
}
}
static CPU_RESET( minx )
void minx_cpu_device::device_reset()
{
minx_state *minx = get_safe_token(device);
minx->SP = minx->BA = minx->HL = minx->X = minx->Y = 0;
minx->U = minx->V = minx->F = minx->E = minx->I = minx->XI = minx->YI = 0;
minx->halted = minx->interrupt_pending = 0;
m_SP = m_BA = m_HL = m_X = m_Y = 0;
m_U = m_V = m_F = m_E = m_I = m_XI = m_YI = 0;
m_halted = m_interrupt_pending = 0;
minx->PC = rd16( minx, 0 );
m_PC = rd16( 0 );
}
static CPU_EXIT( minx )
{
}
INLINE UINT8 rdop( minx_state *minx )
UINT8 minx_cpu_device::rdop()
{
UINT8 op = RD( GET_MINX_PC );
minx->PC++;
m_PC++;
return op;
}
INLINE UINT16 rdop16( minx_state *minx )
UINT16 minx_cpu_device::rdop16()
{
UINT16 op = rdop(minx);
op = op | ( rdop(minx) << 8 );
UINT16 op = rdop();
op = op | ( rdop() << 8 );
return op;
}
@ -167,231 +175,65 @@ INLINE UINT16 rdop16( minx_state *minx )
#include "minxops.h"
static CPU_EXECUTE( minx )
void minx_cpu_device::execute_run()
{
// UINT32 oldpc;
UINT8 op;
minx_state *minx = get_safe_token(device);
do
{
debugger_instruction_hook(device, GET_MINX_PC);
m_curpc = GET_MINX_PC;
debugger_instruction_hook(this, m_curpc);
// oldpc = GET_MINX_PC;
if ( minx->interrupt_pending )
if ( m_interrupt_pending )
{
minx->halted = 0;
if ( ! ( minx->F & 0xc0 ) && minx->U == minx->V )
m_halted = 0;
if ( ! ( m_F & 0xc0 ) && m_U == m_V )
{
//logerror("minx_execute(): taking IRQ\n");
PUSH8( minx, minx->V );
PUSH16( minx, minx->PC );
PUSH8( minx, minx->F );
PUSH8( m_V );
PUSH16( m_PC );
PUSH8( m_F );
/* Set Interrupt Branch flag */
minx->F |= 0x80;
minx->V = 0;
minx->PC = rd16( minx, minx->irq_callback( minx->device, 0 ) << 1 );
minx->icount -= 28; /* This cycle count is a guess */
m_F |= 0x80;
m_V = 0;
m_PC = rd16( standard_irq_callback( 0 ) << 1 );
m_icount -= 28; /* This cycle count is a guess */
}
}
if ( minx->halted )
if ( m_halted )
{
minx->icount -= insnminx_cycles_CE[0xAE];
m_icount -= insnminx_cycles_CE[0xAE];
}
else
{
op = rdop(minx);
insnminx[op](minx);
minx->icount -= insnminx_cycles[op];
op = rdop();
(this->*insnminx[op])();
m_icount -= insnminx_cycles[op];
}
} while ( minx->icount > 0 );
} while ( m_icount > 0 );
}
static CPU_BURN( minx )
{
minx_state *minx = get_safe_token(device);
minx->icount = 0;
}
static unsigned minx_get_reg( minx_state *minx, int regnum )
{
switch( regnum )
{
case STATE_GENPC: return GET_MINX_PC;
case MINX_PC: return minx->PC;
case STATE_GENSP:
case MINX_SP: return minx->SP;
case MINX_BA: return minx->BA;
case MINX_HL: return minx->HL;
case MINX_X: return minx->X;
case MINX_Y: return minx->Y;
case MINX_U: return minx->U;
case MINX_V: return minx->V;
case MINX_F: return minx->F;
case MINX_E: return minx->E;
case MINX_N: return minx->N;
case MINX_I: return minx->I;
case MINX_XI: return minx->XI;
case MINX_YI: return minx->YI;
}
return 0;
}
static void minx_set_reg( minx_state *minx, int regnum, unsigned val )
{
switch( regnum )
{
case STATE_GENPC: break;
case MINX_PC: minx->PC = val; break;
case STATE_GENSP:
case MINX_SP: minx->SP = val; break;
case MINX_BA: minx->BA = val; break;
case MINX_HL: minx->HL = val; break;
case MINX_X: minx->X = val; break;
case MINX_Y: minx->Y = val; break;
case MINX_U: minx->U = val; break;
case MINX_V: minx->V = val; break;
case MINX_F: minx->F = val; break;
case MINX_E: minx->E = val; break;
case MINX_N: minx->N = val; break;
case MINX_I: minx->I = val; break;
case MINX_XI: minx->XI = val; break;
case MINX_YI: minx->YI = val; break;
}
}
static void minx_set_irq_line( minx_state *minx, int irqline, int state )
void minx_cpu_device::execute_set_input(int inputnum, int state)
{
if ( state == ASSERT_LINE )
{
minx->interrupt_pending = 1;
m_interrupt_pending = 1;
}
else
{
minx->interrupt_pending = 0;
m_interrupt_pending = 0;
}
}
static CPU_SET_INFO( minx )
offs_t minx_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{
minx_state *minx = get_safe_token(device);
switch( state )
{
case CPUINFO_INT_INPUT_STATE + 0:
minx_set_irq_line( minx, state - CPUINFO_INT_INPUT_STATE, info->i ); break;
case CPUINFO_INT_REGISTER + MINX_PC:
case CPUINFO_INT_REGISTER + MINX_SP:
case CPUINFO_INT_REGISTER + MINX_BA:
case CPUINFO_INT_REGISTER + MINX_HL:
case CPUINFO_INT_REGISTER + MINX_X:
case CPUINFO_INT_REGISTER + MINX_Y:
case CPUINFO_INT_REGISTER + MINX_U:
case CPUINFO_INT_REGISTER + MINX_V:
case CPUINFO_INT_REGISTER + MINX_F:
case CPUINFO_INT_REGISTER + MINX_E:
case CPUINFO_INT_REGISTER + MINX_N:
case CPUINFO_INT_REGISTER + MINX_I:
case CPUINFO_INT_REGISTER + MINX_XI:
case CPUINFO_INT_REGISTER + MINX_YI:
minx_set_reg( minx, state - CPUINFO_INT_REGISTER, info->i ); break;
}
extern CPU_DISASSEMBLE( minx );
return CPU_DISASSEMBLE_NAME(minx)(this, buffer, pc, oprom, opram, options);
}
CPU_GET_INFO( minx )
{
minx_state *minx = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
switch( state )
{
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(minx_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0x00; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 4; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + 0: info->i = 0; break;
case CPUINFO_INT_REGISTER + STATE_GENPC: info->i = GET_MINX_PC; break;
case CPUINFO_INT_REGISTER + STATE_GENSP:
case CPUINFO_INT_REGISTER + MINX_PC:
case CPUINFO_INT_REGISTER + MINX_SP:
case CPUINFO_INT_REGISTER + MINX_BA:
case CPUINFO_INT_REGISTER + MINX_HL:
case CPUINFO_INT_REGISTER + MINX_X:
case CPUINFO_INT_REGISTER + MINX_Y:
case CPUINFO_INT_REGISTER + MINX_U:
case CPUINFO_INT_REGISTER + MINX_V:
case CPUINFO_INT_REGISTER + MINX_F:
case CPUINFO_INT_REGISTER + MINX_E:
case CPUINFO_INT_REGISTER + MINX_N:
case CPUINFO_INT_REGISTER + MINX_I:
case CPUINFO_INT_REGISTER + MINX_XI:
case CPUINFO_INT_REGISTER + MINX_YI: info->i = minx_get_reg( minx, state - CPUINFO_INT_REGISTER ); break;
case CPUINFO_INT_PREVIOUSPC: info->i = 0x0000; break;
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(minx); break;
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(minx); break;
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(minx); break;
case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(minx); break;
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(minx); break;
case CPUINFO_FCT_BURN: info->burn = CPU_BURN_NAME(minx); break;
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(minx); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &minx->icount; break;
case CPUINFO_STR_NAME: strcpy( info->s, "Minx" ); break;
case CPUINFO_STR_FAMILY: strcpy( info->s, "Nintendo Minx" ); break;
case CPUINFO_STR_VERSION: strcpy( info->s, "0.1" ); break;
case CPUINFO_STR_SOURCE_FILE: strcpy( info->s, __FILE__ ); break;
case CPUINFO_STR_CREDITS: strcpy( info->s, "Copyright The MESS Team." ); break;
case CPUINFO_STR_FLAGS:
sprintf( info->s, "%c%c%c%c%c%c%c%c-%c%c%c%c%c",
minx->F & FLAG_I ? 'I' : '.',
minx->F & FLAG_D ? 'D' : '.',
minx->F & FLAG_L ? 'L' : '.',
minx->F & FLAG_B ? 'B' : '.',
minx->F & FLAG_S ? 'S' : '.',
minx->F & FLAG_O ? 'O' : '.',
minx->F & FLAG_C ? 'C' : '.',
minx->F & FLAG_Z ? 'Z' : '.',
minx->E & EXEC_X0 ? '0' : '.',
minx->E & EXEC_X1 ? '1' : '.',
minx->E & EXEC_X2 ? '2' : '.',
minx->E & EXEC_DZ ? 'z' : '.',
minx->E & EXEC_EN ? 'E' : '.' );
break;
case CPUINFO_STR_REGISTER + MINX_PC: sprintf( info->s, "PC:%04X", minx->PC ); break;
case CPUINFO_STR_REGISTER + MINX_SP: sprintf( info->s, "SP:%04X", minx->SP ); break;
case CPUINFO_STR_REGISTER + MINX_BA: sprintf( info->s, "BA:%04X", minx->BA ); break;
case CPUINFO_STR_REGISTER + MINX_HL: sprintf( info->s, "HL:%04X", minx->HL ); break;
case CPUINFO_STR_REGISTER + MINX_X: sprintf( info->s, "X:%04X", minx->X ); break;
case CPUINFO_STR_REGISTER + MINX_Y: sprintf( info->s, "Y:%04X", minx->Y ); break;
case CPUINFO_STR_REGISTER + MINX_U: sprintf( info->s, "U:%02X", minx->U ); break;
case CPUINFO_STR_REGISTER + MINX_V: sprintf( info->s, "V:%02X", minx->V ); break;
case CPUINFO_STR_REGISTER + MINX_F: sprintf( info->s, "F:%02X", minx->F ); break;
case CPUINFO_STR_REGISTER + MINX_E: sprintf( info->s, "E:%02X", minx->E ); break;
case CPUINFO_STR_REGISTER + MINX_N: sprintf( info->s, "N:%02X", minx->N ); break;
case CPUINFO_STR_REGISTER + MINX_I: sprintf( info->s, "I:%02X", minx->I ); break;
case CPUINFO_STR_REGISTER + MINX_XI: sprintf( info->s, "XI:%02X", minx->XI ); break;
case CPUINFO_STR_REGISTER + MINX_YI: sprintf( info->s, "YI:%02X", minx->YI ); break;
}
}
DEFINE_LEGACY_CPU_DEVICE(MINX, minx);

878
src/emu/cpu/minx/minx.h
View File

@ -11,8 +11,882 @@ enum
MINX_XI, MINX_YI,
};
DECLARE_LEGACY_CPU_DEVICE(MINX, minx);
extern CPU_DISASSEMBLE( minx );
class minx_cpu_device : public cpu_device
{
public:
// construction/destruction
minx_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 4; }
virtual UINT32 execute_input_lines() const { return 1; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
// device_state_interface overrides
void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
virtual UINT32 disasm_max_opcode_bytes() const { return 5; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
address_space_config m_program_config;
UINT16 m_PC;
UINT16 m_SP;
UINT16 m_BA;
UINT16 m_HL;
UINT16 m_X;
UINT16 m_Y;
UINT8 m_U;
UINT8 m_V;
UINT8 m_F;
UINT8 m_E;
UINT8 m_N;
UINT8 m_I;
UINT8 m_XI;
UINT8 m_YI;
UINT8 m_halted;
UINT8 m_interrupt_pending;
address_space *m_program;
int m_icount;
// For debugger
UINT32 m_curpc;
UINT16 m_flags;
UINT16 rd16( UINT32 offset );
void wr16( UINT32 offset, UINT16 data );
UINT8 rdop();
UINT16 rdop16();
UINT8 ADD8( UINT8 arg1, UINT8 arg2 );
UINT16 ADD16( UINT16 arg1, UINT16 arg2 );
UINT8 ADDC8( UINT8 arg1, UINT8 arg2 );
UINT16 ADDC16( UINT16 arg1, UINT16 arg2 );
UINT8 INC8( UINT8 arg );
UINT16 INC16( UINT16 arg );
UINT8 SUB8( UINT8 arg1, UINT8 arg2 );
UINT16 SUB16( UINT16 arg1, UINT16 arg2 );
UINT8 SUBC8( UINT8 arg1, UINT8 arg2 );
UINT16 SUBC16( UINT16 arg1, UINT16 arg2 );
UINT8 DEC8( UINT8 arg );
UINT16 DEC16( UINT16 arg );
UINT8 AND8( UINT8 arg1, UINT8 arg2 );
UINT8 OR8( UINT8 arg1, UINT8 arg2 );
UINT8 XOR8( UINT8 arg1, UINT8 arg2 );
UINT8 NOT8( UINT8 arg );
UINT8 NEG8( UINT8 arg );
UINT8 SAL8( UINT8 arg );
UINT8 SAR8( UINT8 arg );
UINT8 SHL8( UINT8 arg );
UINT8 SHR8( UINT8 arg );
UINT8 ROLC8( UINT8 arg );
UINT8 RORC8( UINT8 arg );
UINT8 ROL8( UINT8 arg );
UINT8 ROR8( UINT8 arg );
void PUSH8( UINT8 arg );
void PUSH16( UINT16 arg );
UINT8 POP8();
UINT16 POP16();
void JMP( UINT16 arg );
void CALL( UINT16 arg );
void minx_00();
void minx_01();
void minx_02();
void minx_03();
void minx_04();
void minx_05();
void minx_06();
void minx_07();
void minx_08();
void minx_09();
void minx_0A();
void minx_0B();
void minx_0C();
void minx_0D();
void minx_0E();
void minx_0F();
void minx_10();
void minx_11();
void minx_12();
void minx_13();
void minx_14();
void minx_15();
void minx_16();
void minx_17();
void minx_18();
void minx_19();
void minx_1A();
void minx_1B();
void minx_1C();
void minx_1D();
void minx_1E();
void minx_1F();
void minx_20();
void minx_21();
void minx_22();
void minx_23();
void minx_24();
void minx_25();
void minx_26();
void minx_27();
void minx_28();
void minx_29();
void minx_2A();
void minx_2B();
void minx_2C();
void minx_2D();
void minx_2E();
void minx_2F();
void minx_30();
void minx_31();
void minx_32();
void minx_33();
void minx_34();
void minx_35();
void minx_36();
void minx_37();
void minx_38();
void minx_39();
void minx_3A();
void minx_3B();
void minx_3C();
void minx_3D();
void minx_3E();
void minx_3F();
void minx_40();
void minx_41();
void minx_42();
void minx_43();
void minx_44();
void minx_45();
void minx_46();
void minx_47();
void minx_48();
void minx_49();
void minx_4A();
void minx_4B();
void minx_4C();
void minx_4D();
void minx_4E();
void minx_4F();
void minx_50();
void minx_51();
void minx_52();
void minx_53();
void minx_54();
void minx_55();
void minx_56();
void minx_57();
void minx_58();
void minx_59();
void minx_5A();
void minx_5B();
void minx_5C();
void minx_5D();
void minx_5E();
void minx_5F();
void minx_60();
void minx_61();
void minx_62();
void minx_63();
void minx_64();
void minx_65();
void minx_66();
void minx_67();
void minx_68();
void minx_69();
void minx_6A();
void minx_6B();
void minx_6C();
void minx_6D();
void minx_6E();
void minx_6F();
void minx_70();
void minx_71();
void minx_72();
void minx_73();
void minx_74();
void minx_75();
void minx_76();
void minx_77();
void minx_78();
void minx_79();
void minx_7A();
void minx_7B();
void minx_7C();
void minx_7D();
void minx_7E();
void minx_7F();
void minx_80();
void minx_81();
void minx_82();
void minx_83();
void minx_84();
void minx_85();
void minx_86();
void minx_87();
void minx_88();
void minx_89();
void minx_8A();
void minx_8B();
void minx_8C();
void minx_8D();
void minx_8E();
void minx_8F();
void minx_90();
void minx_91();
void minx_92();
void minx_93();
void minx_94();
void minx_95();
void minx_96();
void minx_97();
void minx_98();
void minx_99();
void minx_9A();
void minx_9B();
void minx_9C();
void minx_9D();
void minx_9E();
void minx_9F();
void minx_A0();
void minx_A1();
void minx_A2();
void minx_A3();
void minx_A4();
void minx_A5();
void minx_A6();
void minx_A7();
void minx_A8();
void minx_A9();
void minx_AA();
void minx_AB();
void minx_AC();
void minx_AD();
void minx_AE();
void minx_AF();
void minx_B0();
void minx_B1();
void minx_B2();
void minx_B3();
void minx_B4();
void minx_B5();
void minx_B6();
void minx_B7();
void minx_B8();
void minx_B9();
void minx_BA();
void minx_BB();
void minx_BC();
void minx_BD();
void minx_BE();
void minx_BF();
void minx_C0();
void minx_C1();
void minx_C2();
void minx_C3();
void minx_C4();
void minx_C5();
void minx_C6();
void minx_C7();
void minx_C8();
void minx_C9();
void minx_CA();
void minx_CB();
void minx_CC();
void minx_CD();
void minx_CE();
void minx_CF();
void minx_D0();
void minx_D1();
void minx_D2();
void minx_D3();
void minx_D4();
void minx_D5();
void minx_D6();
void minx_D7();
void minx_D8();
void minx_D9();
void minx_DA();
void minx_DB();
void minx_DC();
void minx_DD();
void minx_DE();
void minx_DF();
void minx_E0();
void minx_E1();
void minx_E2();
void minx_E3();
void minx_E4();
void minx_E5();
void minx_E6();
void minx_E7();
void minx_E8();
void minx_E9();
void minx_EA();
void minx_EB();
void minx_EC();
void minx_ED();
void minx_EE();
void minx_EF();
void minx_F0();
void minx_F1();
void minx_F2();
void minx_F3();
void minx_F4();
void minx_F5();
void minx_F6();
void minx_F7();
void minx_F8();
void minx_F9();
void minx_FA();
void minx_FB();
void minx_FC();
void minx_FD();
void minx_FE();
void minx_FF();
void minx_CE_00();
void minx_CE_01();
void minx_CE_02();
void minx_CE_03();
void minx_CE_04();
void minx_CE_05();
void minx_CE_06();
void minx_CE_07();
void minx_CE_08();
void minx_CE_09();
void minx_CE_0A();
void minx_CE_0B();
void minx_CE_0C();
void minx_CE_0D();
void minx_CE_0E();
void minx_CE_0F();
void minx_CE_10();
void minx_CE_11();
void minx_CE_12();
void minx_CE_13();
void minx_CE_14();
void minx_CE_15();
void minx_CE_16();
void minx_CE_17();
void minx_CE_18();
void minx_CE_19();
void minx_CE_1A();
void minx_CE_1B();
void minx_CE_1C();
void minx_CE_1D();
void minx_CE_1E();
void minx_CE_1F();
void minx_CE_20();
void minx_CE_21();
void minx_CE_22();
void minx_CE_23();
void minx_CE_24();
void minx_CE_25();
void minx_CE_26();
void minx_CE_27();
void minx_CE_28();
void minx_CE_29();
void minx_CE_2A();
void minx_CE_2B();
void minx_CE_2C();
void minx_CE_2D();
void minx_CE_2E();
void minx_CE_2F();
void minx_CE_30();
void minx_CE_31();
void minx_CE_32();
void minx_CE_33();
void minx_CE_34();
void minx_CE_35();
void minx_CE_36();
void minx_CE_37();
void minx_CE_38();
void minx_CE_39();
void minx_CE_3A();
void minx_CE_3B();
void minx_CE_3C();
void minx_CE_3D();
void minx_CE_3E();
void minx_CE_3F();
void minx_CE_40();
void minx_CE_41();
void minx_CE_42();
void minx_CE_43();
void minx_CE_44();
void minx_CE_45();
void minx_CE_46();
void minx_CE_47();
void minx_CE_48();
void minx_CE_49();
void minx_CE_4A();
void minx_CE_4B();
void minx_CE_4C();
void minx_CE_4D();
void minx_CE_4E();
void minx_CE_4F();
void minx_CE_50();
void minx_CE_51();
void minx_CE_52();
void minx_CE_53();
void minx_CE_54();
void minx_CE_55();
void minx_CE_56();
void minx_CE_57();
void minx_CE_58();
void minx_CE_59();
void minx_CE_5A();
void minx_CE_5B();
void minx_CE_5C();
void minx_CE_5D();
void minx_CE_5E();
void minx_CE_5F();
void minx_CE_60();
void minx_CE_61();
void minx_CE_62();
void minx_CE_63();
void minx_CE_64();
void minx_CE_65();
void minx_CE_66();
void minx_CE_67();
void minx_CE_68();
void minx_CE_69();
void minx_CE_6A();
void minx_CE_6B();
void minx_CE_6C();
void minx_CE_6D();
void minx_CE_6E();
void minx_CE_6F();
void minx_CE_70();
void minx_CE_71();
void minx_CE_72();
void minx_CE_73();
void minx_CE_74();
void minx_CE_75();
void minx_CE_76();
void minx_CE_77();
void minx_CE_78();
void minx_CE_79();
void minx_CE_7A();
void minx_CE_7B();
void minx_CE_7C();
void minx_CE_7D();
void minx_CE_7E();
void minx_CE_7F();
void minx_CE_80();
void minx_CE_81();
void minx_CE_82();
void minx_CE_83();
void minx_CE_84();
void minx_CE_85();
void minx_CE_86();
void minx_CE_87();
void minx_CE_88();
void minx_CE_89();
void minx_CE_8A();
void minx_CE_8B();
void minx_CE_8C();
void minx_CE_8D();
void minx_CE_8E();
void minx_CE_8F();
void minx_CE_90();
void minx_CE_91();
void minx_CE_92();
void minx_CE_93();
void minx_CE_94();
void minx_CE_95();
void minx_CE_96();
void minx_CE_97();
void minx_CE_98();
void minx_CE_99();
void minx_CE_9A();
void minx_CE_9B();
void minx_CE_9C();
void minx_CE_9D();
void minx_CE_9E();
void minx_CE_9F();
void minx_CE_A0();
void minx_CE_A1();
void minx_CE_A2();
void minx_CE_A3();
void minx_CE_A4();
void minx_CE_A5();
void minx_CE_A6();
void minx_CE_A7();
void minx_CE_A8();
void minx_CE_A9();
void minx_CE_AA();
void minx_CE_AB();
void minx_CE_AC();
void minx_CE_AD();
void minx_CE_AE();
void minx_CE_AF();
void minx_CE_B0();
void minx_CE_B1();
void minx_CE_B2();
void minx_CE_B3();
void minx_CE_B4();
void minx_CE_B5();
void minx_CE_B6();
void minx_CE_B7();
void minx_CE_B8();
void minx_CE_B9();
void minx_CE_BA();
void minx_CE_BB();
void minx_CE_BC();
void minx_CE_BD();
void minx_CE_BE();
void minx_CE_BF();
void minx_CE_C0();
void minx_CE_C1();
void minx_CE_C2();
void minx_CE_C3();
void minx_CE_C4();
void minx_CE_C5();
void minx_CE_C6();
void minx_CE_C7();
void minx_CE_C8();
void minx_CE_C9();
void minx_CE_CA();
void minx_CE_CB();
void minx_CE_CC();
void minx_CE_CD();
void minx_CE_CE();
void minx_CE_CF();
void minx_CE_D0();
void minx_CE_D1();
void minx_CE_D2();
void minx_CE_D3();
void minx_CE_D4();
void minx_CE_D5();
void minx_CE_D6();
void minx_CE_D7();
void minx_CE_D8();
void minx_CE_D9();
void minx_CE_DA();
void minx_CE_DB();
void minx_CE_DC();
void minx_CE_DD();
void minx_CE_DE();
void minx_CE_DF();
void minx_CE_E0();
void minx_CE_E1();
void minx_CE_E2();
void minx_CE_E3();
void minx_CE_E4();
void minx_CE_E5();
void minx_CE_E6();
void minx_CE_E7();
void minx_CE_E8();
void minx_CE_E9();
void minx_CE_EA();
void minx_CE_EB();
void minx_CE_EC();
void minx_CE_ED();
void minx_CE_EE();
void minx_CE_EF();
void minx_CE_F0();
void minx_CE_F1();
void minx_CE_F2();
void minx_CE_F3();
void minx_CE_F4();
void minx_CE_F5();
void minx_CE_F6();
void minx_CE_F7();
void minx_CE_F8();
void minx_CE_F9();
void minx_CE_FA();
void minx_CE_FB();
void minx_CE_FC();
void minx_CE_FD();
void minx_CE_FE();
void minx_CE_FF();
void minx_CF_00();
void minx_CF_01();
void minx_CF_02();
void minx_CF_03();
void minx_CF_04();
void minx_CF_05();
void minx_CF_06();
void minx_CF_07();
void minx_CF_08();
void minx_CF_09();
void minx_CF_0A();
void minx_CF_0B();
void minx_CF_0C();
void minx_CF_0D();
void minx_CF_0E();
void minx_CF_0F();
void minx_CF_10();
void minx_CF_11();
void minx_CF_12();
void minx_CF_13();
void minx_CF_14();
void minx_CF_15();
void minx_CF_16();
void minx_CF_17();
void minx_CF_18();
void minx_CF_19();
void minx_CF_1A();
void minx_CF_1B();
void minx_CF_1C();
void minx_CF_1D();
void minx_CF_1E();
void minx_CF_1F();
void minx_CF_20();
void minx_CF_21();
void minx_CF_22();
void minx_CF_23();
void minx_CF_24();
void minx_CF_25();
void minx_CF_26();
void minx_CF_27();
void minx_CF_28();
void minx_CF_29();
void minx_CF_2A();
void minx_CF_2B();
void minx_CF_2C();
void minx_CF_2D();
void minx_CF_2E();
void minx_CF_2F();
void minx_CF_30();
void minx_CF_31();
void minx_CF_32();
void minx_CF_33();
void minx_CF_34();
void minx_CF_35();
void minx_CF_36();
void minx_CF_37();
void minx_CF_38();
void minx_CF_39();
void minx_CF_3A();
void minx_CF_3B();
void minx_CF_3C();
void minx_CF_3D();
void minx_CF_3E();
void minx_CF_3F();
void minx_CF_40();
void minx_CF_41();
void minx_CF_42();
void minx_CF_43();
void minx_CF_44();
void minx_CF_45();
void minx_CF_46();
void minx_CF_47();
void minx_CF_48();
void minx_CF_49();
void minx_CF_4A();
void minx_CF_4B();
void minx_CF_4C();
void minx_CF_4D();
void minx_CF_4E();
void minx_CF_4F();
void minx_CF_50();
void minx_CF_51();
void minx_CF_52();
void minx_CF_53();
void minx_CF_54();
void minx_CF_55();
void minx_CF_56();
void minx_CF_57();
void minx_CF_58();
void minx_CF_59();
void minx_CF_5A();
void minx_CF_5B();
void minx_CF_5C();
void minx_CF_5D();
void minx_CF_5E();
void minx_CF_5F();
void minx_CF_60();
void minx_CF_61();
void minx_CF_62();
void minx_CF_63();
void minx_CF_64();
void minx_CF_65();
void minx_CF_66();
void minx_CF_67();
void minx_CF_68();
void minx_CF_69();
void minx_CF_6A();
void minx_CF_6B();
void minx_CF_6C();
void minx_CF_6D();
void minx_CF_6E();
void minx_CF_6F();
void minx_CF_70();
void minx_CF_71();
void minx_CF_72();
void minx_CF_73();
void minx_CF_74();
void minx_CF_75();
void minx_CF_76();
void minx_CF_77();
void minx_CF_78();
void minx_CF_79();
void minx_CF_7A();
void minx_CF_7B();
void minx_CF_7C();
void minx_CF_7D();
void minx_CF_7E();
void minx_CF_7F();
void minx_CF_80();
void minx_CF_81();
void minx_CF_82();
void minx_CF_83();
void minx_CF_84();
void minx_CF_85();
void minx_CF_86();
void minx_CF_87();
void minx_CF_88();
void minx_CF_89();
void minx_CF_8A();
void minx_CF_8B();
void minx_CF_8C();
void minx_CF_8D();
void minx_CF_8E();
void minx_CF_8F();
void minx_CF_90();
void minx_CF_91();
void minx_CF_92();
void minx_CF_93();
void minx_CF_94();
void minx_CF_95();
void minx_CF_96();
void minx_CF_97();
void minx_CF_98();
void minx_CF_99();
void minx_CF_9A();
void minx_CF_9B();
void minx_CF_9C();
void minx_CF_9D();
void minx_CF_9E();
void minx_CF_9F();
void minx_CF_A0();
void minx_CF_A1();
void minx_CF_A2();
void minx_CF_A3();
void minx_CF_A4();
void minx_CF_A5();
void minx_CF_A6();
void minx_CF_A7();
void minx_CF_A8();
void minx_CF_A9();
void minx_CF_AA();
void minx_CF_AB();
void minx_CF_AC();
void minx_CF_AD();
void minx_CF_AE();
void minx_CF_AF();
void minx_CF_B0();
void minx_CF_B1();
void minx_CF_B2();
void minx_CF_B3();
void minx_CF_B4();
void minx_CF_B5();
void minx_CF_B6();
void minx_CF_B7();
void minx_CF_B8();
void minx_CF_B9();
void minx_CF_BA();
void minx_CF_BB();
void minx_CF_BC();
void minx_CF_BD();
void minx_CF_BE();
void minx_CF_BF();
void minx_CF_C0();
void minx_CF_C1();
void minx_CF_C2();
void minx_CF_C3();
void minx_CF_C4();
void minx_CF_C5();
void minx_CF_C6();
void minx_CF_C7();
void minx_CF_C8();
void minx_CF_C9();
void minx_CF_CA();
void minx_CF_CB();
void minx_CF_CC();
void minx_CF_CD();
void minx_CF_CE();
void minx_CF_CF();
void minx_CF_D0();
void minx_CF_D1();
void minx_CF_D2();
void minx_CF_D3();
void minx_CF_D4();
void minx_CF_D5();
void minx_CF_D6();
void minx_CF_D7();
void minx_CF_D8();
void minx_CF_D9();
void minx_CF_DA();
void minx_CF_DB();
void minx_CF_DC();
void minx_CF_DD();
void minx_CF_DE();
void minx_CF_DF();
void minx_CF_E0();
void minx_CF_E1();
void minx_CF_E2();
void minx_CF_E3();
void minx_CF_E4();
void minx_CF_E5();
void minx_CF_E6();
void minx_CF_E7();
void minx_CF_E8();
void minx_CF_E9();
void minx_CF_EA();
void minx_CF_EB();
void minx_CF_EC();
void minx_CF_ED();
void minx_CF_EE();
void minx_CF_EF();
void minx_CF_F0();
void minx_CF_F1();
void minx_CF_F2();
void minx_CF_F3();
void minx_CF_F4();
void minx_CF_F5();
void minx_CF_F6();
void minx_CF_F7();
void minx_CF_F8();
void minx_CF_F9();
void minx_CF_FA();
void minx_CF_FB();
void minx_CF_FC();
void minx_CF_FD();
void minx_CF_FE();
void minx_CF_FF();
typedef void (minx_cpu_device::*op_func)();
static const op_func insnminx[256];
static const int insnminx_cycles[256];
static const op_func insnminx_CE[256];
static const int insnminx_cycles_CE[256];
static const op_func insnminx_CF[256];
static const int insnminx_cycles_CF[256];
};
extern const device_type MINX;
#endif /* __MINX_H__ */

200
src/emu/cpu/minx/minxfunc.h
View File

@ -1,7 +1,7 @@
INLINE UINT8 ADD8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
UINT8 minx_cpu_device::ADD8( UINT8 arg1, UINT8 arg2 )
{
UINT32 res = arg1 + arg2;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( ( arg2 ^ arg1 ^ 0x80 ) & ( arg2 ^ res ) & 0x80 ) ? FLAG_O : 0 )
| ( ( res & 0xFF00 ) ? FLAG_C : 0 )
@ -11,10 +11,10 @@ INLINE UINT8 ADD8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
}
INLINE UINT16 ADD16( minx_state *minx, UINT16 arg1, UINT16 arg2 )
UINT16 minx_cpu_device::ADD16( UINT16 arg1, UINT16 arg2 )
{
UINT32 res = arg1 + arg2;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x8000 ) ? FLAG_S : 0 )
| ( ( ( arg2 ^ arg1 ^ 0x8000 ) & ( arg2 ^ res ) & 0x8000 ) ? FLAG_O : 0 )
| ( ( res & 0xFF0000 ) ? FLAG_C : 0 )
@ -24,10 +24,10 @@ INLINE UINT16 ADD16( minx_state *minx, UINT16 arg1, UINT16 arg2 )
}
INLINE UINT8 ADDC8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
UINT8 minx_cpu_device::ADDC8( UINT8 arg1, UINT8 arg2 )
{
UINT32 res = arg1 + arg2 + ( ( minx->F & FLAG_C ) ? 1 : 0 );
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
UINT32 res = arg1 + arg2 + ( ( m_F & FLAG_C ) ? 1 : 0 );
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( ( arg2 ^ arg1 ^ 0x80 ) & ( arg2 ^ res ) & 0x80 ) ? FLAG_O : 0 )
| ( ( res & 0xFF00 ) ? FLAG_C : 0 )
@ -37,10 +37,10 @@ INLINE UINT8 ADDC8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
}
INLINE UINT16 ADDC16( minx_state *minx, UINT16 arg1, UINT16 arg2 )
UINT16 minx_cpu_device::ADDC16( UINT16 arg1, UINT16 arg2 )
{
UINT32 res = arg1 + arg2 + ( ( minx->F & FLAG_C ) ? 1 : 0 );
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
UINT32 res = arg1 + arg2 + ( ( m_F & FLAG_C ) ? 1 : 0 );
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x8000 ) ? FLAG_S : 0 )
| ( ( ( arg2 ^ arg1 ^ 0x8000 ) & ( arg2 ^ res ) & 0x8000 ) ? FLAG_O : 0 )
| ( ( res & 0xFF0000 ) ? FLAG_C : 0 )
@ -50,32 +50,32 @@ INLINE UINT16 ADDC16( minx_state *minx, UINT16 arg1, UINT16 arg2 )
}
INLINE UINT8 INC8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::INC8( UINT8 arg )
{
UINT8 old_F = minx->F;
UINT8 res = ADD8( minx, arg, 1 );
minx->F = ( old_F & ~ ( FLAG_Z ) )
UINT8 old_F = m_F;
UINT8 res = ADD8( arg, 1 );
m_F = ( old_F & ~ ( FLAG_Z ) )
| ( ( res ) ? 0 : FLAG_Z )
;
return res;
}
INLINE UINT16 INC16( minx_state *minx, UINT16 arg )
UINT16 minx_cpu_device::INC16( UINT16 arg )
{
UINT8 old_F = minx->F;
UINT16 res = ADD16( minx, arg, 1 );
minx->F = ( old_F & ~ ( FLAG_Z ) )
UINT8 old_F = m_F;
UINT16 res = ADD16( arg, 1 );
m_F = ( old_F & ~ ( FLAG_Z ) )
| ( ( res ) ? 0 : FLAG_Z )
;
return res;
}
INLINE UINT8 SUB8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
UINT8 minx_cpu_device::SUB8( UINT8 arg1, UINT8 arg2 )
{
UINT32 res = arg1 - arg2;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( ( arg2 ^ arg1 ) & ( arg1 ^ res ) & 0x80 ) ? FLAG_O : 0 )
| ( ( res & 0xFF00 ) ? FLAG_C : 0 )
@ -85,10 +85,10 @@ INLINE UINT8 SUB8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
}
INLINE UINT16 SUB16( minx_state *minx, UINT16 arg1, UINT16 arg2 )
UINT16 minx_cpu_device::SUB16( UINT16 arg1, UINT16 arg2 )
{
UINT32 res = arg1 - arg2;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x8000 ) ? FLAG_S : 0 )
| ( ( ( arg2 ^ arg1 ) & ( arg1 ^ res ) & 0x8000 ) ? FLAG_O : 0 )
| ( ( res & 0xFF0000 ) ? FLAG_C : 0 )
@ -98,10 +98,10 @@ INLINE UINT16 SUB16( minx_state *minx, UINT16 arg1, UINT16 arg2 )
}
INLINE UINT8 SUBC8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
UINT8 minx_cpu_device::SUBC8( UINT8 arg1, UINT8 arg2 )
{
UINT32 res = arg1 - arg2 - ( ( minx->F & FLAG_C ) ? 1 : 0 );
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
UINT32 res = arg1 - arg2 - ( ( m_F & FLAG_C ) ? 1 : 0 );
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( ( arg2 ^ arg1 ) & ( arg1 ^ res ) & 0x80 ) ? FLAG_O : 0 )
| ( ( res & 0xFF00 ) ? FLAG_C : 0 )
@ -111,10 +111,10 @@ INLINE UINT8 SUBC8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
}
INLINE UINT16 SUBC16( minx_state *minx, UINT16 arg1, UINT16 arg2 )
UINT16 minx_cpu_device::SUBC16( UINT16 arg1, UINT16 arg2 )
{
UINT32 res = arg1 - arg2 - ( ( minx->F & FLAG_C ) ? 1 : 0 );
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
UINT32 res = arg1 - arg2 - ( ( m_F & FLAG_C ) ? 1 : 0 );
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x8000 ) ? FLAG_S : 0 )
| ( ( ( arg2 ^ arg1 ) & ( arg1 ^ res ) & 0x8000 ) ? FLAG_O : 0 )
| ( ( res & 0xFF0000 ) ? FLAG_C : 0 )
@ -124,32 +124,32 @@ INLINE UINT16 SUBC16( minx_state *minx, UINT16 arg1, UINT16 arg2 )
}
INLINE UINT8 DEC8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::DEC8( UINT8 arg )
{
UINT8 old_F = minx->F;
UINT8 res = SUB8( minx, arg, 1 );
minx->F = ( old_F & ~ ( FLAG_Z ) )
UINT8 old_F = m_F;
UINT8 res = SUB8( arg, 1 );
m_F = ( old_F & ~ ( FLAG_Z ) )
| ( ( res ) ? 0 : FLAG_Z )
;
return res;
}
INLINE UINT16 DEC16( minx_state *minx, UINT16 arg )
UINT16 minx_cpu_device::DEC16( UINT16 arg )
{
UINT8 old_F = minx->F;
UINT16 res = SUB16( minx, arg, 1 );
minx->F = ( old_F & ~ ( FLAG_Z ) )
UINT8 old_F = m_F;
UINT16 res = SUB16( arg, 1 );
m_F = ( old_F & ~ ( FLAG_Z ) )
| ( ( res ) ? 0 : FLAG_Z )
;
return res;
}
INLINE UINT8 AND8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
UINT8 minx_cpu_device::AND8( UINT8 arg1, UINT8 arg2 )
{
UINT8 res = arg1 & arg2;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( res ) ? 0 : FLAG_Z )
;
@ -157,10 +157,10 @@ INLINE UINT8 AND8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
}
INLINE UINT8 OR8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
UINT8 minx_cpu_device::OR8( UINT8 arg1, UINT8 arg2 )
{
UINT8 res = arg1 | arg2;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( res ) ? 0 : FLAG_Z )
;
@ -168,10 +168,10 @@ INLINE UINT8 OR8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
}
INLINE UINT8 XOR8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
UINT8 minx_cpu_device::XOR8( UINT8 arg1, UINT8 arg2 )
{
UINT8 res = arg1 ^ arg2;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( res ) ? 0 : FLAG_Z )
;
@ -179,10 +179,10 @@ INLINE UINT8 XOR8( minx_state *minx, UINT8 arg1, UINT8 arg2 )
}
INLINE UINT8 NOT8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::NOT8( UINT8 arg )
{
UINT8 res = ~arg;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( res ) ? 0 : FLAG_Z )
;
@ -190,10 +190,10 @@ INLINE UINT8 NOT8( minx_state *minx, UINT8 arg )
}
INLINE UINT8 NEG8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::NEG8( UINT8 arg )
{
UINT8 res = -arg;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( res ) ? 0 : FLAG_Z )
;
@ -201,10 +201,10 @@ INLINE UINT8 NEG8( minx_state *minx, UINT8 arg )
}
INLINE UINT8 SAL8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::SAL8( UINT8 arg )
{
UINT16 res = arg << 1;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( arg != 0 && res == 0 ) ? FLAG_O : 0 )
| ( ( arg & 0x80 ) ? FLAG_C : 0 )
@ -214,10 +214,10 @@ INLINE UINT8 SAL8( minx_state *minx, UINT8 arg )
}
INLINE UINT8 SAR8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::SAR8( UINT8 arg )
{
UINT16 res = ( arg >> 1 ) | ( arg & 0x80 );
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( arg != 0x80 && res == 0x80 ) ? FLAG_O : 0 )
| ( ( arg & 0x01 ) ? FLAG_C : 0 )
@ -227,10 +227,10 @@ INLINE UINT8 SAR8( minx_state *minx, UINT8 arg )
}
INLINE UINT8 SHL8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::SHL8( UINT8 arg )
{
UINT16 res = arg << 1;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( arg & 0x80 ) ? FLAG_C : 0 )
| ( ( res ) ? 0 : FLAG_Z )
@ -239,10 +239,10 @@ INLINE UINT8 SHL8( minx_state *minx, UINT8 arg )
}
INLINE UINT8 SHR8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::SHR8( UINT8 arg )
{
UINT16 res = arg >> 1;
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( arg & 0x01 ) ? FLAG_C : 0 )
| ( ( res ) ? 0 : FLAG_Z )
@ -251,10 +251,10 @@ INLINE UINT8 SHR8( minx_state *minx, UINT8 arg )
}
INLINE UINT8 ROLC8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::ROLC8( UINT8 arg )
{
UINT16 res = ( arg << 1 ) | ( ( minx->F & FLAG_C ) ? 1 : 0 );
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
UINT16 res = ( arg << 1 ) | ( ( m_F & FLAG_C ) ? 1 : 0 );
m_F = ( m_F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( arg & 0x80 ) ? FLAG_C : 0 )
| ( ( res ) ? 0 : FLAG_Z )
@ -263,10 +263,10 @@ INLINE UINT8 ROLC8( minx_state *minx, UINT8 arg )
}
INLINE UINT8 RORC8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::RORC8( UINT8 arg )
{
UINT16 res = ( arg >> 1 ) | ( ( minx->F & FLAG_C ) ? 0x80 : 0 );
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
UINT16 res = ( arg >> 1 ) | ( ( m_F & FLAG_C ) ? 0x80 : 0 );
m_F = ( m_F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( arg & 0x01 ) ? FLAG_C : 0 )
| ( ( res ) ? 0 : FLAG_Z )
@ -275,10 +275,10 @@ INLINE UINT8 RORC8( minx_state *minx, UINT8 arg )
}
INLINE UINT8 ROL8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::ROL8( UINT8 arg )
{
UINT16 res = ( arg << 1 ) | ( ( arg & 0x80 ) ? 1 : 0 );
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( arg & 0x80 ) ? FLAG_C : 0 )
| ( ( res ) ? 0 : FLAG_Z )
@ -287,10 +287,10 @@ INLINE UINT8 ROL8( minx_state *minx, UINT8 arg )
}
INLINE UINT8 ROR8( minx_state *minx, UINT8 arg )
UINT8 minx_cpu_device::ROR8( UINT8 arg )
{
UINT16 res = ( arg >> 1 ) | ( ( arg & 0x01 ) ? 0x80 : 0 );
minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
m_F = ( m_F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) )
| ( ( res & 0x80 ) ? FLAG_S : 0 )
| ( ( arg & 0x01 ) ? FLAG_C : 0 )
| ( ( res ) ? 0 : FLAG_Z )
@ -299,64 +299,64 @@ INLINE UINT8 ROR8( minx_state *minx, UINT8 arg )
}
INLINE void PUSH8( minx_state *minx, UINT8 arg )
void minx_cpu_device::PUSH8( UINT8 arg )
{
minx->SP = minx->SP - 1;
WR( minx->SP, arg );
m_SP = m_SP - 1;
WR( m_SP, arg );
}
INLINE void PUSH16( minx_state *minx, UINT16 arg )
void minx_cpu_device::PUSH16( UINT16 arg )
{
PUSH8( minx, arg >> 8 );
PUSH8( minx, arg & 0x00FF );
PUSH8( arg >> 8 );
PUSH8( arg & 0x00FF );
}
INLINE UINT8 POP8( minx_state *minx )
UINT8 minx_cpu_device::POP8()
{
UINT8 res = RD( minx->SP );
minx->SP = minx->SP + 1;
UINT8 res = RD( m_SP );
m_SP = m_SP + 1;
return res;
}
INLINE UINT16 POP16( minx_state *minx )
UINT16 minx_cpu_device::POP16()
{
return POP8(minx) | ( POP8(minx) << 8 );
return POP8() | ( POP8() << 8 );
}
INLINE void JMP( minx_state *minx, UINT16 arg )
void minx_cpu_device::JMP( UINT16 arg )
{
minx->V = minx->U;
minx->PC = arg;
m_V = m_U;
m_PC = arg;
}
INLINE void CALL( minx_state *minx, UINT16 arg )
void minx_cpu_device::CALL( UINT16 arg )
{
PUSH8( minx, minx->V );
PUSH16( minx, minx->PC );
JMP( minx, arg );
PUSH8( m_V );
PUSH16( m_PC );
JMP( arg );
}
#define AD1_IHL UINT32 addr1 = ( minx->I << 16 ) | minx->HL
#define AD1_IN8 UINT32 addr1 = ( minx->I << 16 ) | ( minx->N << 8 ) | rdop(minx)
#define AD1_I16 UINT32 addr1 = ( minx->I << 16 ) | rdop16(minx)
#define AD1_XIX UINT32 addr1 = ( minx->XI << 16 ) | minx->X
#define AD1_YIY UINT32 addr1 = ( minx->YI << 16 ) | minx->Y
#define AD1_X8 UINT32 addr1 = ( minx->XI << 16 ) | ( minx->X + rdop(minx) )
#define AD1_Y8 UINT32 addr1 = ( minx->YI << 16 ) | ( minx->Y + rdop(minx) )
#define AD1_XL UINT32 addr1 = ( minx->XI << 16 ) | ( minx->X + ( minx->HL & 0x00FF ) )
#define AD1_YL UINT32 addr1 = ( minx->YI << 16 ) | ( minx->Y + ( minx->HL & 0x00FF ) )
#define AD2_IHL UINT32 addr2 = ( minx->I << 16 ) | minx->HL
#define AD2_IN8 UINT32 addr2 = ( minx->I << 16 ) | ( minx->N << 8 ) | rdop(minx)
#define AD2_I16 UINT32 addr2 = ( minx->I << 16 ) | rdop(minx); addr2 |= ( rdop(minx) << 8 )
#define AD2_XIX UINT32 addr2 = ( minx->XI << 16 ) | minx->X
#define AD2_YIY UINT32 addr2 = ( minx->YI << 16 ) | minx->Y
#define AD2_X8 UINT32 addr2 = ( minx->XI << 16 ) | ( minx->X + rdop(minx) )
#define AD2_Y8 UINT32 addr2 = ( minx->YI << 16 ) | ( minx->Y + rdop(minx) )
#define AD2_XL UINT32 addr2 = ( minx->XI << 16 ) | ( minx->X + ( minx->HL & 0x00FF ) )
#define AD2_YL UINT32 addr2 = ( minx->YI << 16 ) | ( minx->Y + ( minx->HL & 0x00FF ) )
#define AD1_IHL UINT32 addr1 = ( m_I << 16 ) | m_HL
#define AD1_IN8 UINT32 addr1 = ( m_I << 16 ) | ( m_N << 8 ) | rdop()
#define AD1_I16 UINT32 addr1 = ( m_I << 16 ) | rdop16()
#define AD1_XIX UINT32 addr1 = ( m_XI << 16 ) | m_X
#define AD1_YIY UINT32 addr1 = ( m_YI << 16 ) | m_Y
#define AD1_X8 UINT32 addr1 = ( m_XI << 16 ) | ( m_X + rdop() )
#define AD1_Y8 UINT32 addr1 = ( m_YI << 16 ) | ( m_Y + rdop() )
#define AD1_XL UINT32 addr1 = ( m_XI << 16 ) | ( m_X + ( m_HL & 0x00FF ) )
#define AD1_YL UINT32 addr1 = ( m_YI << 16 ) | ( m_Y + ( m_HL & 0x00FF ) )
#define AD2_IHL UINT32 addr2 = ( m_I << 16 ) | m_HL
#define AD2_IN8 UINT32 addr2 = ( m_I << 16 ) | ( m_N << 8 ) | rdop()
#define AD2_I16 UINT32 addr2 = ( m_I << 16 ) | rdop(); addr2 |= ( rdop() << 8 )
#define AD2_XIX UINT32 addr2 = ( m_XI << 16 ) | m_X
#define AD2_YIY UINT32 addr2 = ( m_YI << 16 ) | m_Y
#define AD2_X8 UINT32 addr2 = ( m_XI << 16 ) | ( m_X + rdop() )
#define AD2_Y8 UINT32 addr2 = ( m_YI << 16 ) | ( m_Y + rdop() )
#define AD2_XL UINT32 addr2 = ( m_XI << 16 ) | ( m_X + ( m_HL & 0x00FF ) )
#define AD2_YL UINT32 addr2 = ( m_YI << 16 ) | ( m_Y + ( m_HL & 0x00FF ) )

492
src/emu/cpu/minx/minxopce.h
View File

@ -1,107 +1,107 @@
#undef OP
#define OP(nn) INLINE void minx_CE_##nn(minx_state *minx)
#define OP(nn) void minx_cpu_device::minx_CE_##nn()
OP(00) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(01) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(02) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(03) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(04) { AD1_IHL; WR( addr1, ADD8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); }
OP(05) { AD1_IHL; WR( addr1, ADD8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(06) { AD1_IHL; AD2_XIX; WR( addr1, ADD8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(07) { AD1_IHL; AD2_YIY; WR( addr1, ADD8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(08) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(09) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(0A) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(0B) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(0C) { AD1_IHL; WR( addr1, ADDC8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); }
OP(0D) { AD1_IHL; WR( addr1, ADDC8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(0E) { AD1_IHL; AD2_XIX; WR( addr1, ADDC8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(0F) { AD1_IHL; AD2_YIY; WR( addr1, ADDC8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(00) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(01) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(02) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(03) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(04) { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
OP(05) { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), rdop() ) ); }
OP(06) { AD1_IHL; AD2_XIX; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); }
OP(07) { AD1_IHL; AD2_YIY; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); }
OP(08) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(09) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(0A) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(0B) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(0C) { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
OP(0D) { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), rdop() ) ); }
OP(0E) { AD1_IHL; AD2_XIX; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); }
OP(0F) { AD1_IHL; AD2_YIY; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); }
OP(10) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(11) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(12) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(13) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(14) { AD1_IHL; WR( addr1, SUB8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); }
OP(15) { AD1_IHL; WR( addr1, SUB8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(16) { AD1_IHL; AD2_XIX; WR( addr1, SUB8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(17) { AD1_IHL; AD2_YIY; WR( addr1, SUB8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(18) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(19) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(1A) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(1B) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(1C) { AD1_IHL; WR( addr1, SUBC8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); }
OP(1D) { AD1_IHL; WR( addr1, SUBC8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(1E) { AD1_IHL; AD2_XIX; WR( addr1, SUBC8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(1F) { AD1_IHL; AD2_YIY; WR( addr1, SUBC8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(10) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(11) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(12) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(13) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(14) { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
OP(15) { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), rdop() ) ); }
OP(16) { AD1_IHL; AD2_XIX; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); }
OP(17) { AD1_IHL; AD2_YIY; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); }
OP(18) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(19) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(1A) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(1B) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(1C) { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
OP(1D) { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), rdop() ) ); }
OP(1E) { AD1_IHL; AD2_XIX; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); }
OP(1F) { AD1_IHL; AD2_YIY; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); }
OP(20) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(21) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(22) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(23) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(24) { AD1_IHL; WR( addr1, AND8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); }
OP(25) { AD1_IHL; WR( addr1, AND8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(26) { AD1_IHL; AD2_XIX; WR( addr1, AND8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(27) { AD1_IHL; AD2_YIY; WR( addr1, AND8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(28) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(29) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(2A) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(2B) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(2C) { AD1_IHL; WR( addr1, OR8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); }
OP(2D) { AD1_IHL; WR( addr1, OR8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(2E) { AD1_IHL; AD2_XIX; WR( addr1, OR8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(2F) { AD1_IHL; AD2_YIY; WR( addr1, OR8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(20) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(21) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(22) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(23) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(24) { AD1_IHL; WR( addr1, AND8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
OP(25) { AD1_IHL; WR( addr1, AND8( RD( addr1 ), rdop() ) ); }
OP(26) { AD1_IHL; AD2_XIX; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); }
OP(27) { AD1_IHL; AD2_YIY; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); }
OP(28) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(29) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(2A) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(2B) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(2C) { AD1_IHL; WR( addr1, OR8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
OP(2D) { AD1_IHL; WR( addr1, OR8( RD( addr1 ), rdop() ) ); }
OP(2E) { AD1_IHL; AD2_XIX; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); }
OP(2F) { AD1_IHL; AD2_YIY; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); }
OP(30) { AD2_X8; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(31) { AD2_Y8; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(32) { AD2_XL; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(33) { AD2_YL; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(34) { AD1_IHL; SUB8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ); }
OP(35) { AD1_IHL; SUB8( minx, RD( addr1 ), rdop(minx) ); }
OP(36) { AD1_IHL; AD2_XIX; SUB8( minx, RD( addr1 ), RD( addr2 ) ); }
OP(37) { AD1_IHL; AD2_YIY; SUB8( minx, RD( addr1 ), RD( addr2 ) ); }
OP(38) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(39) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(3A) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(3B) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(3C) { AD1_IHL; WR( addr1, XOR8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); }
OP(3D) { AD1_IHL; WR( addr1, XOR8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(3E) { AD1_IHL; AD2_XIX; WR( addr1, XOR8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(3F) { AD1_IHL; AD2_YIY; WR( addr1, XOR8( minx, RD( addr1 ), RD( addr2 ) ) ); }
OP(30) { AD2_X8; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(31) { AD2_Y8; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(32) { AD2_XL; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(33) { AD2_YL; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(34) { AD1_IHL; SUB8( RD( addr1 ), ( m_BA & 0x00FF ) ); }
OP(35) { AD1_IHL; SUB8( RD( addr1 ), rdop() ); }
OP(36) { AD1_IHL; AD2_XIX; SUB8( RD( addr1 ), RD( addr2 ) ); }
OP(37) { AD1_IHL; AD2_YIY; SUB8( RD( addr1 ), RD( addr2 ) ); }
OP(38) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(39) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(3A) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(3B) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(3C) { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
OP(3D) { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); }
OP(3E) { AD1_IHL; AD2_XIX; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); }
OP(3F) { AD1_IHL; AD2_YIY; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); }
OP(40) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); }
OP(41) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); }
OP(42) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); }
OP(43) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); }
OP(44) { AD1_X8; WR( addr1, ( minx->BA & 0x00FF ) ); }
OP(45) { AD1_Y8; WR( addr1, ( minx->BA & 0x00FF ) ); }
OP(46) { AD1_XL; WR( addr1, ( minx->BA & 0x00FF ) ); }
OP(47) { AD1_YL; WR( addr1, ( minx->BA & 0x00FF ) ); }
OP(48) { AD2_X8; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(49) { AD2_Y8; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4A) { AD2_XL; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4B) { AD2_YL; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4C) { AD1_X8; WR( addr1, ( minx->BA >> 8 ) ); }
OP(4D) { AD1_Y8; WR( addr1, ( minx->BA >> 8 ) ); }
OP(4E) { AD1_XL; WR( addr1, ( minx->BA >> 8 ) ); }
OP(4F) { AD1_YL; WR( addr1, ( minx->BA >> 8 ) ); }
OP(40) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
OP(41) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
OP(42) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
OP(43) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
OP(44) { AD1_X8; WR( addr1, ( m_BA & 0x00FF ) ); }
OP(45) { AD1_Y8; WR( addr1, ( m_BA & 0x00FF ) ); }
OP(46) { AD1_XL; WR( addr1, ( m_BA & 0x00FF ) ); }
OP(47) { AD1_YL; WR( addr1, ( m_BA & 0x00FF ) ); }
OP(48) { AD2_X8; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(49) { AD2_Y8; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4A) { AD2_XL; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4B) { AD2_YL; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4C) { AD1_X8; WR( addr1, ( m_BA >> 8 ) ); }
OP(4D) { AD1_Y8; WR( addr1, ( m_BA >> 8 ) ); }
OP(4E) { AD1_XL; WR( addr1, ( m_BA >> 8 ) ); }
OP(4F) { AD1_YL; WR( addr1, ( m_BA >> 8 ) ); }
OP(50) { AD2_X8; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); }
OP(51) { AD2_Y8; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); }
OP(52) { AD2_XL; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); }
OP(53) { AD2_YL; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); }
OP(54) { AD1_X8; WR( addr1, ( minx->HL & 0x00FF ) ); }
OP(55) { AD1_Y8; WR( addr1, ( minx->HL & 0x00FF ) ); }
OP(56) { AD1_XL; WR( addr1, ( minx->HL & 0x00FF ) ); }
OP(57) { AD1_YL; WR( addr1, ( minx->HL & 0x00FF ) ); }
OP(58) { AD2_X8; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(59) { AD2_Y8; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5A) { AD2_XL; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5B) { AD2_YL; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5C) { AD1_X8; WR( addr1, ( minx->HL >> 8 ) ); }
OP(5D) { AD1_Y8; WR( addr1, ( minx->HL >> 8 ) ); }
OP(5E) { AD1_XL; WR( addr1, ( minx->HL >> 8 ) ); }
OP(5F) { AD1_YL; WR( addr1, ( minx->HL >> 8 ) ); }
OP(50) { AD2_X8; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
OP(51) { AD2_Y8; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
OP(52) { AD2_XL; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
OP(53) { AD2_YL; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
OP(54) { AD1_X8; WR( addr1, ( m_HL & 0x00FF ) ); }
OP(55) { AD1_Y8; WR( addr1, ( m_HL & 0x00FF ) ); }
OP(56) { AD1_XL; WR( addr1, ( m_HL & 0x00FF ) ); }
OP(57) { AD1_YL; WR( addr1, ( m_HL & 0x00FF ) ); }
OP(58) { AD2_X8; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(59) { AD2_Y8; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5A) { AD2_XL; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5B) { AD2_YL; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5C) { AD1_X8; WR( addr1, ( m_HL >> 8 ) ); }
OP(5D) { AD1_Y8; WR( addr1, ( m_HL >> 8 ) ); }
OP(5E) { AD1_XL; WR( addr1, ( m_HL >> 8 ) ); }
OP(5F) { AD1_YL; WR( addr1, ( m_HL >> 8 ) ); }
OP(60) { AD1_IHL; AD2_X8; WR( addr1, RD( addr2 ) ); }
OP(61) { AD1_IHL; AD2_Y8; WR( addr1, RD( addr2 ) ); }
@ -137,101 +137,101 @@ OP(7D) { /* illegal operation? */ }
OP(7E) { /* illegal operation? */ }
OP(7F) { /* illegal operation? */ }
OP(80) { minx->BA = ( minx->BA & 0xFF00 ) | SAL8( minx, minx->BA & 0x00FF ); }
OP(81) { minx->BA = ( minx->BA & 0x00FF ) | ( SAL8( minx, minx->BA >> 8 )<< 8 ); }
OP(82) { AD1_IN8; WR( addr1, SAL8( minx, RD( addr1 ) ) ); }
OP(83) { AD1_IHL; WR( addr1, SAL8( minx, RD( addr1 ) ) ); }
OP(84) { minx->BA = ( minx->BA & 0xFF00 ) | SHL8( minx, minx->BA & 0x00FF ); }
OP(85) { minx->BA = ( minx->BA & 0x00FF ) | ( SHL8( minx, minx->BA >> 8 ) << 8 ); }
OP(86) { AD1_IN8; WR( addr1, SHL8( minx, RD( addr1 ) ) ); }
OP(87) { AD1_IHL; WR( addr1, SHL8( minx, RD( addr1 ) ) ); }
OP(88) { minx->BA = ( minx->BA & 0xFF00 ) | SAR8( minx, minx->BA & 0x00FF ); }
OP(89) { minx->BA = ( minx->BA & 0x00FF ) | ( SAR8( minx, minx->BA >> 8 ) << 8 ); }
OP(8A) { AD1_IN8; WR( addr1, SAR8( minx, RD( addr1 ) ) ); }
OP(8B) { AD1_IHL; WR( addr1, SAR8( minx, RD( addr1 ) ) ); }
OP(8C) { minx->BA = ( minx->BA & 0xFF00 ) | SHR8( minx, minx->BA & 0x00FF ); }
OP(8D) { minx->BA = ( minx->BA & 0x00FF ) | ( SHR8( minx, minx->BA >> 8 ) << 8 ); }
OP(8E) { AD1_IN8; WR( addr1, SHR8( minx, RD( addr1 ) ) ); }
OP(8F) { AD1_IHL; WR( addr1, SHR8( minx, RD( addr1 ) ) ); }
OP(80) { m_BA = ( m_BA & 0xFF00 ) | SAL8( m_BA & 0x00FF ); }
OP(81) { m_BA = ( m_BA & 0x00FF ) | ( SAL8( m_BA >> 8 )<< 8 ); }
OP(82) { AD1_IN8; WR( addr1, SAL8( RD( addr1 ) ) ); }
OP(83) { AD1_IHL; WR( addr1, SAL8( RD( addr1 ) ) ); }
OP(84) { m_BA = ( m_BA & 0xFF00 ) | SHL8( m_BA & 0x00FF ); }
OP(85) { m_BA = ( m_BA & 0x00FF ) | ( SHL8( m_BA >> 8 ) << 8 ); }
OP(86) { AD1_IN8; WR( addr1, SHL8( RD( addr1 ) ) ); }
OP(87) { AD1_IHL; WR( addr1, SHL8( RD( addr1 ) ) ); }
OP(88) { m_BA = ( m_BA & 0xFF00 ) | SAR8( m_BA & 0x00FF ); }
OP(89) { m_BA = ( m_BA & 0x00FF ) | ( SAR8( m_BA >> 8 ) << 8 ); }
OP(8A) { AD1_IN8; WR( addr1, SAR8( RD( addr1 ) ) ); }
OP(8B) { AD1_IHL; WR( addr1, SAR8( RD( addr1 ) ) ); }
OP(8C) { m_BA = ( m_BA & 0xFF00 ) | SHR8( m_BA & 0x00FF ); }
OP(8D) { m_BA = ( m_BA & 0x00FF ) | ( SHR8( m_BA >> 8 ) << 8 ); }
OP(8E) { AD1_IN8; WR( addr1, SHR8( RD( addr1 ) ) ); }
OP(8F) { AD1_IHL; WR( addr1, SHR8( RD( addr1 ) ) ); }
OP(90) { minx->BA = ( minx->BA & 0xFF00 ) | ROLC8( minx, minx->BA & 0x00FF ); }
OP(91) { minx->BA = ( minx->BA & 0x00FF ) | ( ROLC8( minx, minx->BA >> 8 ) << 8 ); }
OP(92) { AD1_IN8; WR( addr1, ROLC8( minx, RD( addr1 ) ) ); }
OP(93) { AD1_IHL; WR( addr1, ROLC8( minx, RD( addr1 ) ) ); }
OP(94) { minx->BA = ( minx->BA & 0xFF00 ) | ROL8( minx, minx->BA & 0x00FF ); }
OP(95) { minx->BA = ( minx->BA & 0x00FF ) | ( ROL8( minx, minx->BA >> 8 ) << 8 ); }
OP(96) { AD1_IN8; WR( addr1, ROL8( minx, RD( addr1 ) ) ); }
OP(97) { AD1_IHL; WR( addr1, ROL8( minx, RD( addr1 ) ) ); }
OP(98) { minx->BA = ( minx->BA & 0xFF00 ) | RORC8( minx, minx->BA & 0x00FF ); }
OP(99) { minx->BA = ( minx->BA & 0x00FF ) | ( RORC8( minx, minx->BA >> 8 ) << 8 ); }
OP(9A) { AD1_IN8; WR( addr1, RORC8( minx, RD( addr1 ) ) ); }
OP(9B) { AD1_IHL; WR( addr1, RORC8( minx, RD( addr1 ) ) ); }
OP(9C) { minx->BA = ( minx->BA & 0xFF00 ) | ROR8( minx, minx->BA & 0x00FF ); }
OP(9D) { minx->BA = ( minx->BA & 0x00FF ) | ( ROR8( minx, minx->BA >> 8 ) << 8 ); }
OP(9E) { AD1_IN8; WR( addr1, ROR8( minx, RD( addr1 ) ) ); }
OP(9F) { AD1_IHL; WR( addr1, ROR8( minx, RD( addr1 ) ) ); }
OP(90) { m_BA = ( m_BA & 0xFF00 ) | ROLC8( m_BA & 0x00FF ); }
OP(91) { m_BA = ( m_BA & 0x00FF ) | ( ROLC8( m_BA >> 8 ) << 8 ); }
OP(92) { AD1_IN8; WR( addr1, ROLC8( RD( addr1 ) ) ); }
OP(93) { AD1_IHL; WR( addr1, ROLC8( RD( addr1 ) ) ); }
OP(94) { m_BA = ( m_BA & 0xFF00 ) | ROL8( m_BA & 0x00FF ); }
OP(95) { m_BA = ( m_BA & 0x00FF ) | ( ROL8( m_BA >> 8 ) << 8 ); }
OP(96) { AD1_IN8; WR( addr1, ROL8( RD( addr1 ) ) ); }
OP(97) { AD1_IHL; WR( addr1, ROL8( RD( addr1 ) ) ); }
OP(98) { m_BA = ( m_BA & 0xFF00 ) | RORC8( m_BA & 0x00FF ); }
OP(99) { m_BA = ( m_BA & 0x00FF ) | ( RORC8( m_BA >> 8 ) << 8 ); }
OP(9A) { AD1_IN8; WR( addr1, RORC8( RD( addr1 ) ) ); }
OP(9B) { AD1_IHL; WR( addr1, RORC8( RD( addr1 ) ) ); }
OP(9C) { m_BA = ( m_BA & 0xFF00 ) | ROR8( m_BA & 0x00FF ); }
OP(9D) { m_BA = ( m_BA & 0x00FF ) | ( ROR8( m_BA >> 8 ) << 8 ); }
OP(9E) { AD1_IN8; WR( addr1, ROR8( RD( addr1 ) ) ); }
OP(9F) { AD1_IHL; WR( addr1, ROR8( RD( addr1 ) ) ); }
OP(A0) { minx->BA = ( minx->BA & 0xFF00 ) | NOT8( minx, minx->BA & 0x00FF ); }
OP(A1) { minx->BA = ( minx->BA & 0x00FF ) | ( NOT8( minx, minx->BA >> 8 ) << 8 ); }
OP(A2) { AD1_IN8; WR( addr1, NOT8( minx, RD( addr1 ) ) ); }
OP(A3) { AD1_IHL; WR( addr1, NOT8( minx, RD( addr1 ) ) ); }
OP(A4) { minx->BA = ( minx->BA & 0xFF00 ) | NEG8( minx, minx->BA & 0x00FF ); }
OP(A5) { minx->BA = ( minx->BA & 0x00FF ) | ( NEG8( minx, minx->BA >> 8 ) << 8 ); }
OP(A6) { AD1_IN8; WR( addr1, NEG8( minx, RD( addr1 ) ) ); }
OP(A7) { AD1_IHL; WR( addr1, NEG8( minx, RD( addr1 ) ) ); }
OP(A8) { minx->BA = ( ( minx->BA & 0x0080 ) ? ( 0xFF00 | minx->BA ) : ( minx->BA & 0x00FF ) ); }
OP(A0) { m_BA = ( m_BA & 0xFF00 ) | NOT8( m_BA & 0x00FF ); }
OP(A1) { m_BA = ( m_BA & 0x00FF ) | ( NOT8( m_BA >> 8 ) << 8 ); }
OP(A2) { AD1_IN8; WR( addr1, NOT8( RD( addr1 ) ) ); }
OP(A3) { AD1_IHL; WR( addr1, NOT8( RD( addr1 ) ) ); }
OP(A4) { m_BA = ( m_BA & 0xFF00 ) | NEG8( m_BA & 0x00FF ); }
OP(A5) { m_BA = ( m_BA & 0x00FF ) | ( NEG8( m_BA >> 8 ) << 8 ); }
OP(A6) { AD1_IN8; WR( addr1, NEG8( RD( addr1 ) ) ); }
OP(A7) { AD1_IHL; WR( addr1, NEG8( RD( addr1 ) ) ); }
OP(A8) { m_BA = ( ( m_BA & 0x0080 ) ? ( 0xFF00 | m_BA ) : ( m_BA & 0x00FF ) ); }
OP(A9) { /* illegal operation? */ }
OP(AA) { /* illegal operation? */ }
OP(AB) { /* illegal operation? */ }
OP(AC) { /* illegal operation? */ }
OP(AD) { /* illegal operation? */ }
OP(AE) { /* HALT */ minx->halted = 1; }
OP(AE) { /* HALT */ m_halted = 1; }
OP(AF) { }
OP(B0) { minx->BA = ( minx->BA & 0x00FF ) | ( AND8( minx, ( minx->BA >> 8 ), rdop(minx) ) << 8 ); }
OP(B1) { minx->HL = ( minx->HL & 0xFF00 ) | AND8( minx, ( minx->HL & 0x00FF ), rdop(minx) ); }
OP(B2) { minx->HL = ( minx->HL & 0x00FF ) | ( AND8( minx, ( minx->HL >> 8 ), rdop(minx) ) << 8 ); }
OP(B0) { m_BA = ( m_BA & 0x00FF ) | ( AND8( ( m_BA >> 8 ), rdop() ) << 8 ); }
OP(B1) { m_HL = ( m_HL & 0xFF00 ) | AND8( ( m_HL & 0x00FF ), rdop() ); }
OP(B2) { m_HL = ( m_HL & 0x00FF ) | ( AND8( ( m_HL >> 8 ), rdop() ) << 8 ); }
OP(B3) { /* illegal operation? */ }
OP(B4) { minx->BA = ( minx->BA & 0x00FF ) | ( OR8( minx, ( minx->BA >> 8 ), rdop(minx) ) << 8 ); }
OP(B5) { minx->HL = ( minx->HL & 0xFF00 ) | OR8( minx, ( minx->HL & 0x00FF ), rdop(minx) ); }
OP(B6) { minx->HL = ( minx->HL & 0x00FF ) | ( OR8( minx, ( minx->HL >> 8 ), rdop(minx) ) << 8 ); }
OP(B4) { m_BA = ( m_BA & 0x00FF ) | ( OR8( ( m_BA >> 8 ), rdop() ) << 8 ); }
OP(B5) { m_HL = ( m_HL & 0xFF00 ) | OR8( ( m_HL & 0x00FF ), rdop() ); }
OP(B6) { m_HL = ( m_HL & 0x00FF ) | ( OR8( ( m_HL >> 8 ), rdop() ) << 8 ); }
OP(B7) { /* illegal operation? */ }
OP(B8) { minx->BA = ( minx->BA & 0x00FF ) | ( XOR8( minx, ( minx->BA >> 8 ), rdop(minx) ) << 8 ); }
OP(B9) { minx->HL = ( minx->HL & 0xFF00 ) | XOR8( minx, ( minx->HL & 0x00FF ), rdop(minx) ); }
OP(BA) { minx->HL = ( minx->HL & 0x00FF ) | ( XOR8( minx, ( minx->HL >> 8 ), rdop(minx) ) << 8 ); }
OP(B8) { m_BA = ( m_BA & 0x00FF ) | ( XOR8( ( m_BA >> 8 ), rdop() ) << 8 ); }
OP(B9) { m_HL = ( m_HL & 0xFF00 ) | XOR8( ( m_HL & 0x00FF ), rdop() ); }
OP(BA) { m_HL = ( m_HL & 0x00FF ) | ( XOR8( ( m_HL >> 8 ), rdop() ) << 8 ); }
OP(BB) { /* illegal operation? */ }
OP(BC) { SUB8( minx, ( minx->BA >> 8 ), rdop(minx) ); }
OP(BD) { SUB8( minx, ( minx->HL & 0x00FF), rdop(minx) ); }
OP(BE) { SUB8( minx, ( minx->HL >> 8 ), rdop(minx) ); }
OP(BF) { SUB8( minx, minx->N, rdop(minx) ); }
OP(BC) { SUB8( ( m_BA >> 8 ), rdop() ); }
OP(BD) { SUB8( ( m_HL & 0x00FF), rdop() ); }
OP(BE) { SUB8( ( m_HL >> 8 ), rdop() ); }
OP(BF) { SUB8( m_N, rdop() ); }
OP(C0) { minx->BA = ( minx->BA & 0xFF00 ) | minx->N; }
OP(C1) { minx->BA = ( minx->BA & 0xFF00 ) | minx->F; }
OP(C2) { minx->N = ( minx->BA & 0x00FF ); }
OP(C3) { minx->F = ( minx->BA & 0x00FF ); }
OP(C4) { minx->U = rdop(minx); }
OP(C5) { minx->I = rdop(minx); }
OP(C6) { minx->XI = rdop(minx); }
OP(C7) { minx->YI = rdop(minx); }
OP(C8) { minx->BA = ( minx->BA & 0xFF00 ) | minx->V; }
OP(C9) { minx->BA = ( minx->BA & 0xFF00 ) | minx->I; }
OP(CA) { minx->BA = ( minx->BA & 0xFF00 ) | minx->XI; }
OP(CB) { minx->BA = ( minx->BA & 0xFF00 ) | minx->YI; }
OP(CC) { minx->U = ( minx->BA & 0x00FF ); }
OP(CD) { minx->I = ( minx->BA & 0x00FF ); }
OP(CE) { minx->XI = ( minx->BA & 0x00FF ); }
OP(CF) { minx->YI = ( minx->BA & 0x00FF ); }
OP(C0) { m_BA = ( m_BA & 0xFF00 ) | m_N; }
OP(C1) { m_BA = ( m_BA & 0xFF00 ) | m_F; }
OP(C2) { m_N = ( m_BA & 0x00FF ); }
OP(C3) { m_F = ( m_BA & 0x00FF ); }
OP(C4) { m_U = rdop(); }
OP(C5) { m_I = rdop(); }
OP(C6) { m_XI = rdop(); }
OP(C7) { m_YI = rdop(); }
OP(C8) { m_BA = ( m_BA & 0xFF00 ) | m_V; }
OP(C9) { m_BA = ( m_BA & 0xFF00 ) | m_I; }
OP(CA) { m_BA = ( m_BA & 0xFF00 ) | m_XI; }
OP(CB) { m_BA = ( m_BA & 0xFF00 ) | m_YI; }
OP(CC) { m_U = ( m_BA & 0x00FF ); }
OP(CD) { m_I = ( m_BA & 0x00FF ); }
OP(CE) { m_XI = ( m_BA & 0x00FF ); }
OP(CF) { m_YI = ( m_BA & 0x00FF ); }
OP(D0) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); }
OP(D1) { AD2_I16; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(D2) { AD2_I16; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); }
OP(D3) { AD2_I16; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(D4) { AD1_I16; WR( addr1, ( minx->BA & 0x00FF ) ); }
OP(D5) { AD1_I16; WR( addr1, ( minx->BA >> 8 ) ); }
OP(D6) { AD1_I16; WR( addr1, ( minx->HL & 0x00FF ) ); }
OP(D7) { AD1_I16; WR( addr1, ( minx->HL >> 8 ) ); }
OP(D8) { minx->HL = ( minx->HL & 0x00FF ) * ( minx->BA & 0x00FF ); }
OP(D9) { int d = minx->HL / ( minx->BA & 0x00FF ); minx->HL = ( ( minx->HL - ( ( minx->BA & 0x00FF ) * d ) ) << 8 ) | d; }
OP(D0) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
OP(D1) { AD2_I16; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(D2) { AD2_I16; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
OP(D3) { AD2_I16; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(D4) { AD1_I16; WR( addr1, ( m_BA & 0x00FF ) ); }
OP(D5) { AD1_I16; WR( addr1, ( m_BA >> 8 ) ); }
OP(D6) { AD1_I16; WR( addr1, ( m_HL & 0x00FF ) ); }
OP(D7) { AD1_I16; WR( addr1, ( m_HL >> 8 ) ); }
OP(D8) { m_HL = ( m_HL & 0x00FF ) * ( m_BA & 0x00FF ); }
OP(D9) { int d = m_HL / ( m_BA & 0x00FF ); m_HL = ( ( m_HL - ( ( m_BA & 0x00FF ) * d ) ) << 8 ) | d; }
OP(DA) { /* illegal operation? */ }
OP(DB) { /* illegal operation? */ }
OP(DC) { /* illegal operation? */ }
@ -239,76 +239,76 @@ OP(DD) { /* illegal operation? */ }
OP(DE) { /* illegal operation? */ }
OP(DF) { /* illegal operation? */ }
OP(E0) { INT8 d8 = rdop(minx); if ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E1) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_Z ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E2) { INT8 d8 = rdop(minx); if ( !( minx->F & FLAG_Z ) && ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E3) { INT8 d8 = rdop(minx); if ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E4) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_O ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E5) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_O ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E6) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_S ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E7) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_S ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E8) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X0 ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E9) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X1 ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(EA) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X2 ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(EB) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_DZ ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(EC) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X0 ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(ED) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X1 ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(EE) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X2 ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(EF) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_DZ ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E0) { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E1) { INT8 d8 = rdop(); if ( ( m_F & FLAG_Z ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E2) { INT8 d8 = rdop(); if ( !( m_F & FLAG_Z ) && ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E3) { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E4) { INT8 d8 = rdop(); if ( ( m_F & FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E5) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E6) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_S ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E7) { INT8 d8 = rdop(); if ( ( m_F & FLAG_S ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E8) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X0 ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E9) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X1 ) ) { JMP( m_PC + d8 - 1 ); } }
OP(EA) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X2 ) ) { JMP( m_PC + d8 - 1 ); } }
OP(EB) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_DZ ) ) { JMP( m_PC + d8 - 1 ); } }
OP(EC) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X0 ) ) { JMP( m_PC + d8 - 1 ); } }
OP(ED) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X1 ) ) { JMP( m_PC + d8 - 1 ); } }
OP(EE) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X2 ) ) { JMP( m_PC + d8 - 1 ); } }
OP(EF) { INT8 d8 = rdop(); if ( ( m_E & EXEC_DZ ) ) { JMP( m_PC + d8 - 1 ); } }
OP(F0) { INT8 d8 = rdop(minx); if ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(F1) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_Z ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(F2) { INT8 d8 = rdop(minx); if ( !( minx->F & FLAG_Z ) && ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(F3) { INT8 d8 = rdop(minx); if ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { CALL( minx, minx->PC + d8 - 1 ); } }
OP(F4) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_O ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(F5) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_O ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(F6) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_S ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(F7) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_S ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(F8) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X0 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(F9) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X1 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(FA) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X2 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(FB) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_DZ ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(FC) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X0 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(FD) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X1 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(FE) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X2 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(FF) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_DZ ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(F0) { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(F1) { INT8 d8 = rdop(); if ( ( m_F & FLAG_Z ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(F2) { INT8 d8 = rdop(); if ( !( m_F & FLAG_Z ) && ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(F3) { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { CALL( m_PC + d8 - 1 ); } }
OP(F4) { INT8 d8 = rdop(); if ( ( m_F & FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(F5) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(F6) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_S ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(F7) { INT8 d8 = rdop(); if ( ( m_F & FLAG_S ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(F8) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X0 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(F9) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X1 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(FA) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X2 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(FB) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_DZ ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(FC) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X0 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(FD) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X1 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(FE) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X2 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(FF) { INT8 d8 = rdop(); if ( ( m_E & EXEC_DZ ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
static void (*const insnminx_CE[256])(minx_state *minx) = {
minx_CE_00, minx_CE_01, minx_CE_02, minx_CE_03, minx_CE_04, minx_CE_05, minx_CE_06, minx_CE_07,
minx_CE_08, minx_CE_09, minx_CE_0A, minx_CE_0B, minx_CE_0C, minx_CE_0D, minx_CE_0E, minx_CE_0F,
minx_CE_10, minx_CE_11, minx_CE_12, minx_CE_13, minx_CE_14, minx_CE_15, minx_CE_16, minx_CE_17,
minx_CE_18, minx_CE_19, minx_CE_1A, minx_CE_1B, minx_CE_1C, minx_CE_1D, minx_CE_1E, minx_CE_1F,
minx_CE_20, minx_CE_21, minx_CE_22, minx_CE_23, minx_CE_24, minx_CE_25, minx_CE_26, minx_CE_27,
minx_CE_28, minx_CE_29, minx_CE_2A, minx_CE_2B, minx_CE_2C, minx_CE_2D, minx_CE_2E, minx_CE_2F,
minx_CE_30, minx_CE_31, minx_CE_32, minx_CE_33, minx_CE_34, minx_CE_35, minx_CE_36, minx_CE_37,
minx_CE_38, minx_CE_39, minx_CE_3A, minx_CE_3B, minx_CE_3C, minx_CE_3D, minx_CE_3E, minx_CE_3F,
minx_CE_40, minx_CE_41, minx_CE_42, minx_CE_43, minx_CE_44, minx_CE_45, minx_CE_46, minx_CE_47,
minx_CE_48, minx_CE_49, minx_CE_4A, minx_CE_4B, minx_CE_4C, minx_CE_4D, minx_CE_4E, minx_CE_4F,
minx_CE_50, minx_CE_51, minx_CE_52, minx_CE_53, minx_CE_54, minx_CE_55, minx_CE_56, minx_CE_57,
minx_CE_58, minx_CE_59, minx_CE_5A, minx_CE_5B, minx_CE_5C, minx_CE_5D, minx_CE_5E, minx_CE_5F,
minx_CE_60, minx_CE_61, minx_CE_62, minx_CE_63, minx_CE_64, minx_CE_65, minx_CE_66, minx_CE_67,
minx_CE_68, minx_CE_69, minx_CE_6A, minx_CE_6B, minx_CE_6C, minx_CE_6D, minx_CE_6E, minx_CE_6F,
minx_CE_70, minx_CE_71, minx_CE_72, minx_CE_73, minx_CE_74, minx_CE_75, minx_CE_76, minx_CE_77,
minx_CE_78, minx_CE_79, minx_CE_7A, minx_CE_7B, minx_CE_7C, minx_CE_7D, minx_CE_7E, minx_CE_7F,
minx_CE_80, minx_CE_81, minx_CE_82, minx_CE_83, minx_CE_84, minx_CE_85, minx_CE_86, minx_CE_87,
minx_CE_88, minx_CE_89, minx_CE_8A, minx_CE_8B, minx_CE_8C, minx_CE_8D, minx_CE_8E, minx_CE_8F,
minx_CE_90, minx_CE_91, minx_CE_92, minx_CE_93, minx_CE_94, minx_CE_95, minx_CE_96, minx_CE_97,
minx_CE_98, minx_CE_99, minx_CE_9A, minx_CE_9B, minx_CE_9C, minx_CE_9D, minx_CE_9E, minx_CE_9F,
minx_CE_A0, minx_CE_A1, minx_CE_A2, minx_CE_A3, minx_CE_A4, minx_CE_A5, minx_CE_A6, minx_CE_A7,
minx_CE_A8, minx_CE_A9, minx_CE_AA, minx_CE_AB, minx_CE_AC, minx_CE_AD, minx_CE_AE, minx_CE_AF,
minx_CE_B0, minx_CE_B1, minx_CE_B2, minx_CE_B3, minx_CE_B4, minx_CE_B5, minx_CE_B6, minx_CE_B7,
minx_CE_B8, minx_CE_B9, minx_CE_BA, minx_CE_BB, minx_CE_BC, minx_CE_BD, minx_CE_BE, minx_CE_BF,
minx_CE_C0, minx_CE_C1, minx_CE_C2, minx_CE_C3, minx_CE_C4, minx_CE_C5, minx_CE_C6, minx_CE_C7,
minx_CE_C8, minx_CE_C9, minx_CE_CA, minx_CE_CB, minx_CE_CC, minx_CE_CD, minx_CE_CE, minx_CE_CF,
minx_CE_D0, minx_CE_D1, minx_CE_D2, minx_CE_D3, minx_CE_D4, minx_CE_D5, minx_CE_D6, minx_CE_D7,
minx_CE_D8, minx_CE_D9, minx_CE_DA, minx_CE_DB, minx_CE_DC, minx_CE_DD, minx_CE_DE, minx_CE_DF,
minx_CE_E0, minx_CE_E1, minx_CE_E2, minx_CE_E3, minx_CE_E4, minx_CE_E5, minx_CE_E6, minx_CE_E7,
minx_CE_E8, minx_CE_E9, minx_CE_EA, minx_CE_EB, minx_CE_EC, minx_CE_ED, minx_CE_EE, minx_CE_EF,
minx_CE_F0, minx_CE_F1, minx_CE_F2, minx_CE_F3, minx_CE_F4, minx_CE_F5, minx_CE_F6, minx_CE_F7,
minx_CE_F8, minx_CE_F9, minx_CE_FA, minx_CE_FB, minx_CE_FC, minx_CE_FD, minx_CE_FE, minx_CE_FF
const minx_cpu_device::op_func minx_cpu_device::insnminx_CE[256] = {
&minx_cpu_device::minx_CE_00, &minx_cpu_device::minx_CE_01, &minx_cpu_device::minx_CE_02, &minx_cpu_device::minx_CE_03, &minx_cpu_device::minx_CE_04, &minx_cpu_device::minx_CE_05, &minx_cpu_device::minx_CE_06, &minx_cpu_device::minx_CE_07,
&minx_cpu_device::minx_CE_08, &minx_cpu_device::minx_CE_09, &minx_cpu_device::minx_CE_0A, &minx_cpu_device::minx_CE_0B, &minx_cpu_device::minx_CE_0C, &minx_cpu_device::minx_CE_0D, &minx_cpu_device::minx_CE_0E, &minx_cpu_device::minx_CE_0F,
&minx_cpu_device::minx_CE_10, &minx_cpu_device::minx_CE_11, &minx_cpu_device::minx_CE_12, &minx_cpu_device::minx_CE_13, &minx_cpu_device::minx_CE_14, &minx_cpu_device::minx_CE_15, &minx_cpu_device::minx_CE_16, &minx_cpu_device::minx_CE_17,
&minx_cpu_device::minx_CE_18, &minx_cpu_device::minx_CE_19, &minx_cpu_device::minx_CE_1A, &minx_cpu_device::minx_CE_1B, &minx_cpu_device::minx_CE_1C, &minx_cpu_device::minx_CE_1D, &minx_cpu_device::minx_CE_1E, &minx_cpu_device::minx_CE_1F,
&minx_cpu_device::minx_CE_20, &minx_cpu_device::minx_CE_21, &minx_cpu_device::minx_CE_22, &minx_cpu_device::minx_CE_23, &minx_cpu_device::minx_CE_24, &minx_cpu_device::minx_CE_25, &minx_cpu_device::minx_CE_26, &minx_cpu_device::minx_CE_27,
&minx_cpu_device::minx_CE_28, &minx_cpu_device::minx_CE_29, &minx_cpu_device::minx_CE_2A, &minx_cpu_device::minx_CE_2B, &minx_cpu_device::minx_CE_2C, &minx_cpu_device::minx_CE_2D, &minx_cpu_device::minx_CE_2E, &minx_cpu_device::minx_CE_2F,
&minx_cpu_device::minx_CE_30, &minx_cpu_device::minx_CE_31, &minx_cpu_device::minx_CE_32, &minx_cpu_device::minx_CE_33, &minx_cpu_device::minx_CE_34, &minx_cpu_device::minx_CE_35, &minx_cpu_device::minx_CE_36, &minx_cpu_device::minx_CE_37,
&minx_cpu_device::minx_CE_38, &minx_cpu_device::minx_CE_39, &minx_cpu_device::minx_CE_3A, &minx_cpu_device::minx_CE_3B, &minx_cpu_device::minx_CE_3C, &minx_cpu_device::minx_CE_3D, &minx_cpu_device::minx_CE_3E, &minx_cpu_device::minx_CE_3F,
&minx_cpu_device::minx_CE_40, &minx_cpu_device::minx_CE_41, &minx_cpu_device::minx_CE_42, &minx_cpu_device::minx_CE_43, &minx_cpu_device::minx_CE_44, &minx_cpu_device::minx_CE_45, &minx_cpu_device::minx_CE_46, &minx_cpu_device::minx_CE_47,
&minx_cpu_device::minx_CE_48, &minx_cpu_device::minx_CE_49, &minx_cpu_device::minx_CE_4A, &minx_cpu_device::minx_CE_4B, &minx_cpu_device::minx_CE_4C, &minx_cpu_device::minx_CE_4D, &minx_cpu_device::minx_CE_4E, &minx_cpu_device::minx_CE_4F,
&minx_cpu_device::minx_CE_50, &minx_cpu_device::minx_CE_51, &minx_cpu_device::minx_CE_52, &minx_cpu_device::minx_CE_53, &minx_cpu_device::minx_CE_54, &minx_cpu_device::minx_CE_55, &minx_cpu_device::minx_CE_56, &minx_cpu_device::minx_CE_57,
&minx_cpu_device::minx_CE_58, &minx_cpu_device::minx_CE_59, &minx_cpu_device::minx_CE_5A, &minx_cpu_device::minx_CE_5B, &minx_cpu_device::minx_CE_5C, &minx_cpu_device::minx_CE_5D, &minx_cpu_device::minx_CE_5E, &minx_cpu_device::minx_CE_5F,
&minx_cpu_device::minx_CE_60, &minx_cpu_device::minx_CE_61, &minx_cpu_device::minx_CE_62, &minx_cpu_device::minx_CE_63, &minx_cpu_device::minx_CE_64, &minx_cpu_device::minx_CE_65, &minx_cpu_device::minx_CE_66, &minx_cpu_device::minx_CE_67,
&minx_cpu_device::minx_CE_68, &minx_cpu_device::minx_CE_69, &minx_cpu_device::minx_CE_6A, &minx_cpu_device::minx_CE_6B, &minx_cpu_device::minx_CE_6C, &minx_cpu_device::minx_CE_6D, &minx_cpu_device::minx_CE_6E, &minx_cpu_device::minx_CE_6F,
&minx_cpu_device::minx_CE_70, &minx_cpu_device::minx_CE_71, &minx_cpu_device::minx_CE_72, &minx_cpu_device::minx_CE_73, &minx_cpu_device::minx_CE_74, &minx_cpu_device::minx_CE_75, &minx_cpu_device::minx_CE_76, &minx_cpu_device::minx_CE_77,
&minx_cpu_device::minx_CE_78, &minx_cpu_device::minx_CE_79, &minx_cpu_device::minx_CE_7A, &minx_cpu_device::minx_CE_7B, &minx_cpu_device::minx_CE_7C, &minx_cpu_device::minx_CE_7D, &minx_cpu_device::minx_CE_7E, &minx_cpu_device::minx_CE_7F,
&minx_cpu_device::minx_CE_80, &minx_cpu_device::minx_CE_81, &minx_cpu_device::minx_CE_82, &minx_cpu_device::minx_CE_83, &minx_cpu_device::minx_CE_84, &minx_cpu_device::minx_CE_85, &minx_cpu_device::minx_CE_86, &minx_cpu_device::minx_CE_87,
&minx_cpu_device::minx_CE_88, &minx_cpu_device::minx_CE_89, &minx_cpu_device::minx_CE_8A, &minx_cpu_device::minx_CE_8B, &minx_cpu_device::minx_CE_8C, &minx_cpu_device::minx_CE_8D, &minx_cpu_device::minx_CE_8E, &minx_cpu_device::minx_CE_8F,
&minx_cpu_device::minx_CE_90, &minx_cpu_device::minx_CE_91, &minx_cpu_device::minx_CE_92, &minx_cpu_device::minx_CE_93, &minx_cpu_device::minx_CE_94, &minx_cpu_device::minx_CE_95, &minx_cpu_device::minx_CE_96, &minx_cpu_device::minx_CE_97,
&minx_cpu_device::minx_CE_98, &minx_cpu_device::minx_CE_99, &minx_cpu_device::minx_CE_9A, &minx_cpu_device::minx_CE_9B, &minx_cpu_device::minx_CE_9C, &minx_cpu_device::minx_CE_9D, &minx_cpu_device::minx_CE_9E, &minx_cpu_device::minx_CE_9F,
&minx_cpu_device::minx_CE_A0, &minx_cpu_device::minx_CE_A1, &minx_cpu_device::minx_CE_A2, &minx_cpu_device::minx_CE_A3, &minx_cpu_device::minx_CE_A4, &minx_cpu_device::minx_CE_A5, &minx_cpu_device::minx_CE_A6, &minx_cpu_device::minx_CE_A7,
&minx_cpu_device::minx_CE_A8, &minx_cpu_device::minx_CE_A9, &minx_cpu_device::minx_CE_AA, &minx_cpu_device::minx_CE_AB, &minx_cpu_device::minx_CE_AC, &minx_cpu_device::minx_CE_AD, &minx_cpu_device::minx_CE_AE, &minx_cpu_device::minx_CE_AF,
&minx_cpu_device::minx_CE_B0, &minx_cpu_device::minx_CE_B1, &minx_cpu_device::minx_CE_B2, &minx_cpu_device::minx_CE_B3, &minx_cpu_device::minx_CE_B4, &minx_cpu_device::minx_CE_B5, &minx_cpu_device::minx_CE_B6, &minx_cpu_device::minx_CE_B7,
&minx_cpu_device::minx_CE_B8, &minx_cpu_device::minx_CE_B9, &minx_cpu_device::minx_CE_BA, &minx_cpu_device::minx_CE_BB, &minx_cpu_device::minx_CE_BC, &minx_cpu_device::minx_CE_BD, &minx_cpu_device::minx_CE_BE, &minx_cpu_device::minx_CE_BF,
&minx_cpu_device::minx_CE_C0, &minx_cpu_device::minx_CE_C1, &minx_cpu_device::minx_CE_C2, &minx_cpu_device::minx_CE_C3, &minx_cpu_device::minx_CE_C4, &minx_cpu_device::minx_CE_C5, &minx_cpu_device::minx_CE_C6, &minx_cpu_device::minx_CE_C7,
&minx_cpu_device::minx_CE_C8, &minx_cpu_device::minx_CE_C9, &minx_cpu_device::minx_CE_CA, &minx_cpu_device::minx_CE_CB, &minx_cpu_device::minx_CE_CC, &minx_cpu_device::minx_CE_CD, &minx_cpu_device::minx_CE_CE, &minx_cpu_device::minx_CE_CF,
&minx_cpu_device::minx_CE_D0, &minx_cpu_device::minx_CE_D1, &minx_cpu_device::minx_CE_D2, &minx_cpu_device::minx_CE_D3, &minx_cpu_device::minx_CE_D4, &minx_cpu_device::minx_CE_D5, &minx_cpu_device::minx_CE_D6, &minx_cpu_device::minx_CE_D7,
&minx_cpu_device::minx_CE_D8, &minx_cpu_device::minx_CE_D9, &minx_cpu_device::minx_CE_DA, &minx_cpu_device::minx_CE_DB, &minx_cpu_device::minx_CE_DC, &minx_cpu_device::minx_CE_DD, &minx_cpu_device::minx_CE_DE, &minx_cpu_device::minx_CE_DF,
&minx_cpu_device::minx_CE_E0, &minx_cpu_device::minx_CE_E1, &minx_cpu_device::minx_CE_E2, &minx_cpu_device::minx_CE_E3, &minx_cpu_device::minx_CE_E4, &minx_cpu_device::minx_CE_E5, &minx_cpu_device::minx_CE_E6, &minx_cpu_device::minx_CE_E7,
&minx_cpu_device::minx_CE_E8, &minx_cpu_device::minx_CE_E9, &minx_cpu_device::minx_CE_EA, &minx_cpu_device::minx_CE_EB, &minx_cpu_device::minx_CE_EC, &minx_cpu_device::minx_CE_ED, &minx_cpu_device::minx_CE_EE, &minx_cpu_device::minx_CE_EF,
&minx_cpu_device::minx_CE_F0, &minx_cpu_device::minx_CE_F1, &minx_cpu_device::minx_CE_F2, &minx_cpu_device::minx_CE_F3, &minx_cpu_device::minx_CE_F4, &minx_cpu_device::minx_CE_F5, &minx_cpu_device::minx_CE_F6, &minx_cpu_device::minx_CE_F7,
&minx_cpu_device::minx_CE_F8, &minx_cpu_device::minx_CE_F9, &minx_cpu_device::minx_CE_FA, &minx_cpu_device::minx_CE_FB, &minx_cpu_device::minx_CE_FC, &minx_cpu_device::minx_CE_FD, &minx_cpu_device::minx_CE_FE, &minx_cpu_device::minx_CE_FF
};
static const int insnminx_cycles_CE[256] = {
const int minx_cpu_device::insnminx_cycles_CE[256] = {
16, 16, 16, 16, 16, 20, 20, 20, 16, 16, 16, 16, 16, 20, 20, 20,
16, 16, 16, 16, 16, 20, 20, 20, 16, 16, 16, 16, 16, 20, 20, 20,
16, 16, 16, 16, 16, 20, 20, 20, 16, 16, 16, 16, 16, 20, 20, 20,
@ -317,14 +317,14 @@ static const int insnminx_cycles_CE[256] = {
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
20, 20, 20, 20, 1, 1, 1, 1, 20, 20, 20, 20, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 20, 20, 20, 20, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 20, 20, 20, 20, 1, 1, 1, 1,
12, 12, 20, 16, 12, 12, 20, 16, 12, 12, 20, 16, 12, 12, 20, 16,
12, 12, 20, 16, 12, 12, 20, 16, 12, 12, 20, 16, 12, 12, 20, 16,
12, 12, 20, 16, 12, 12, 20, 16, 12, 1, 1, 1, 1, 1, 8, 8,
12, 12, 12, 1, 12, 12, 12, 1, 20, 20, 20, 20, 12, 12, 12, 1,
8, 8, 8, 12, 16, 12, 12, 12, 8, 8, 8, 8, 12, 8, 8, 8,
8, 8, 8, 12, 16, 12, 12, 12, 8, 8, 8, 8, 12, 8, 8, 8,
20, 20, 20, 20, 20, 20, 20, 20, 48, 52, 1, 1, 1, 1, 1, 1,
12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12

354
src/emu/cpu/minx/minxopcf.h
View File

@ -1,22 +1,22 @@
#undef OP
#define OP(nn) INLINE void minx_CF_##nn(minx_state *minx)
#define OP(nn) void minx_cpu_device::minx_CF_##nn()
OP(00) { minx->BA = ADD16( minx, minx->BA, minx->BA ); }
OP(01) { minx->BA = ADD16( minx, minx->BA, minx->HL ); }
OP(02) { minx->BA = ADD16( minx, minx->BA, minx->X ); }
OP(03) { minx->BA = ADD16( minx, minx->BA, minx->Y ); }
OP(04) { minx->BA = ADDC16( minx, minx->BA, minx->BA ); }
OP(05) { minx->BA = ADDC16( minx, minx->BA, minx->HL ); }
OP(06) { minx->BA = ADDC16( minx, minx->BA, minx->X ); }
OP(07) { minx->BA = ADDC16( minx, minx->BA, minx->Y ); }
OP(08) { minx->BA = SUB16( minx, minx->BA, minx->BA ); }
OP(09) { minx->BA = SUB16( minx, minx->BA, minx->HL ); }
OP(0A) { minx->BA = SUB16( minx, minx->BA, minx->X ); }
OP(0B) { minx->BA = SUB16( minx, minx->BA, minx->Y ); }
OP(0C) { minx->BA = SUBC16( minx, minx->BA, minx->BA ); }
OP(0D) { minx->BA = SUBC16( minx, minx->BA, minx->HL ); }
OP(0E) { minx->BA = SUBC16( minx, minx->BA, minx->X ); }
OP(0F) { minx->BA = SUBC16( minx, minx->BA, minx->Y ); }
OP(00) { m_BA = ADD16( m_BA, m_BA ); }
OP(01) { m_BA = ADD16( m_BA, m_HL ); }
OP(02) { m_BA = ADD16( m_BA, m_X ); }
OP(03) { m_BA = ADD16( m_BA, m_Y ); }
OP(04) { m_BA = ADDC16( m_BA, m_BA ); }
OP(05) { m_BA = ADDC16( m_BA, m_HL ); }
OP(06) { m_BA = ADDC16( m_BA, m_X ); }
OP(07) { m_BA = ADDC16( m_BA, m_Y ); }
OP(08) { m_BA = SUB16( m_BA, m_BA ); }
OP(09) { m_BA = SUB16( m_BA, m_HL ); }
OP(0A) { m_BA = SUB16( m_BA, m_X ); }
OP(0B) { m_BA = SUB16( m_BA, m_Y ); }
OP(0C) { m_BA = SUBC16( m_BA, m_BA ); }
OP(0D) { m_BA = SUBC16( m_BA, m_HL ); }
OP(0E) { m_BA = SUBC16( m_BA, m_X ); }
OP(0F) { m_BA = SUBC16( m_BA, m_Y ); }
OP(10) { /* illegal instruction? */ }
OP(11) { /* illegal instruction? */ }
@ -26,31 +26,31 @@ OP(14) { /* illegal instruction? */ }
OP(15) { /* illegal instruction? */ }
OP(16) { /* illegal instruction? */ }
OP(17) { /* illegal instruction? */ }
OP(18) { SUB16( minx, minx->BA, minx->BA ); }
OP(19) { SUB16( minx, minx->BA, minx->HL ); }
OP(1A) { SUB16( minx, minx->BA, minx->X ); }
OP(1B) { SUB16( minx, minx->BA, minx->Y ); }
OP(18) { SUB16( m_BA, m_BA ); }
OP(19) { SUB16( m_BA, m_HL ); }
OP(1A) { SUB16( m_BA, m_X ); }
OP(1B) { SUB16( m_BA, m_Y ); }
OP(1C) { /* illegal instruction? */ }
OP(1D) { /* illegal instruction? */ }
OP(1E) { /* illegal instruction? */ }
OP(1F) { /* illegal instruction? */ }
OP(20) { minx->HL = ADD16( minx, minx->HL, minx->BA ); }
OP(21) { minx->HL = ADD16( minx, minx->HL, minx->HL ); }
OP(22) { minx->HL = ADD16( minx, minx->HL, minx->X ); }
OP(23) { minx->HL = ADD16( minx, minx->HL, minx->Y ); }
OP(24) { minx->HL = ADDC16( minx, minx->HL, minx->BA ); }
OP(25) { minx->HL = ADDC16( minx, minx->HL, minx->HL ); }
OP(26) { minx->HL = ADDC16( minx, minx->HL, minx->X ); }
OP(27) { minx->HL = ADDC16( minx, minx->HL, minx->Y ); }
OP(28) { minx->HL = SUB16( minx, minx->HL, minx->BA ); }
OP(29) { minx->HL = SUB16( minx, minx->HL, minx->HL ); }
OP(2A) { minx->HL = SUB16( minx, minx->HL, minx->X ); }
OP(2B) { minx->HL = SUB16( minx, minx->HL, minx->Y ); }
OP(2C) { minx->HL = SUBC16( minx, minx->HL, minx->BA ); }
OP(2D) { minx->HL = SUBC16( minx, minx->HL, minx->HL ); }
OP(2E) { minx->HL = SUBC16( minx, minx->HL, minx->X ); }
OP(2F) { minx->HL = SUBC16( minx, minx->HL, minx->Y ); }
OP(20) { m_HL = ADD16( m_HL, m_BA ); }
OP(21) { m_HL = ADD16( m_HL, m_HL ); }
OP(22) { m_HL = ADD16( m_HL, m_X ); }
OP(23) { m_HL = ADD16( m_HL, m_Y ); }
OP(24) { m_HL = ADDC16( m_HL, m_BA ); }
OP(25) { m_HL = ADDC16( m_HL, m_HL ); }
OP(26) { m_HL = ADDC16( m_HL, m_X ); }
OP(27) { m_HL = ADDC16( m_HL, m_Y ); }
OP(28) { m_HL = SUB16( m_HL, m_BA ); }
OP(29) { m_HL = SUB16( m_HL, m_HL ); }
OP(2A) { m_HL = SUB16( m_HL, m_X ); }
OP(2B) { m_HL = SUB16( m_HL, m_Y ); }
OP(2C) { m_HL = SUBC16( m_HL, m_BA ); }
OP(2D) { m_HL = SUBC16( m_HL, m_HL ); }
OP(2E) { m_HL = SUBC16( m_HL, m_X ); }
OP(2F) { m_HL = SUBC16( m_HL, m_Y ); }
OP(30) { /* illegal instruction? */ }
OP(31) { /* illegal instruction? */ }
@ -60,29 +60,29 @@ OP(34) { /* illegal instruction? */ }
OP(35) { /* illegal instruction? */ }
OP(36) { /* illegal instruction? */ }
OP(37) { /* illegal instruction? */ }
OP(38) { SUB16( minx, minx->HL, minx->BA ); }
OP(39) { SUB16( minx, minx->HL, minx->HL ); }
OP(3A) { SUB16( minx, minx->HL, minx->X ); }
OP(3B) { SUB16( minx, minx->HL, minx->Y ); }
OP(38) { SUB16( m_HL, m_BA ); }
OP(39) { SUB16( m_HL, m_HL ); }
OP(3A) { SUB16( m_HL, m_X ); }
OP(3B) { SUB16( m_HL, m_Y ); }
OP(3C) { /* illegal instruction? */ }
OP(3D) { /* illegal instruction? */ }
OP(3E) { /* illegal instruction? */ }
OP(3F) { /* illegal instruction? */ }
OP(40) { minx->X = ADD16( minx, minx->X, minx->BA ); }
OP(41) { minx->X = ADD16( minx, minx->X, minx->HL ); }
OP(42) { minx->Y = ADD16( minx, minx->Y, minx->BA ); }
OP(43) { minx->Y = ADD16( minx, minx->Y, minx->HL ); }
OP(44) { minx->SP = ADD16( minx, minx->SP, minx->BA ); }
OP(45) { minx->SP = ADD16( minx, minx->SP, minx->HL ); }
OP(40) { m_X = ADD16( m_X, m_BA ); }
OP(41) { m_X = ADD16( m_X, m_HL ); }
OP(42) { m_Y = ADD16( m_Y, m_BA ); }
OP(43) { m_Y = ADD16( m_Y, m_HL ); }
OP(44) { m_SP = ADD16( m_SP, m_BA ); }
OP(45) { m_SP = ADD16( m_SP, m_HL ); }
OP(46) { /* illegal instruction? */ }
OP(47) { /* illegal instruction? */ }
OP(48) { minx->X = SUB16( minx, minx->X, minx->BA ); }
OP(49) { minx->X = SUB16( minx, minx->X, minx->HL ); }
OP(4A) { minx->Y = SUB16( minx, minx->Y, minx->BA ); }
OP(4B) { minx->Y = SUB16( minx, minx->Y, minx->HL ); }
OP(4C) { minx->SP = SUB16( minx, minx->SP, minx->BA ); }
OP(4D) { minx->SP = SUB16( minx, minx->SP, minx->HL ); }
OP(48) { m_X = SUB16( m_X, m_BA ); }
OP(49) { m_X = SUB16( m_X, m_HL ); }
OP(4A) { m_Y = SUB16( m_Y, m_BA ); }
OP(4B) { m_Y = SUB16( m_Y, m_HL ); }
OP(4C) { m_SP = SUB16( m_SP, m_BA ); }
OP(4D) { m_SP = SUB16( m_SP, m_HL ); }
OP(4E) { /* illegal instruction? */ }
OP(4F) { /* illegal instruction? */ }
@ -98,41 +98,41 @@ OP(58) { /* illegal instruction? */ }
OP(59) { /* illegal instruction? */ }
OP(5A) { /* illegal instruction? */ }
OP(5B) { /* illegal instruction? */ }
OP(5C) { SUB16( minx, minx->SP, minx->BA ); }
OP(5D) { SUB16( minx, minx->SP, minx->HL ); }
OP(5C) { SUB16( m_SP, m_BA ); }
OP(5D) { SUB16( m_SP, m_HL ); }
OP(5E) { /* illegal instruction? */ }
OP(5F) { /* illegal instruction? */ }
OP(60) { ADDC16( minx, minx->BA, rdop16(minx) ); /* ??? */ }
OP(61) { ADDC16( minx, minx->HL, rdop16(minx) ); /* ??? */ }
OP(62) { ADDC16( minx, minx->X, rdop16(minx) ); /* ??? */ }
OP(63) { ADDC16( minx, minx->Y, rdop16(minx) ); /* ??? */ }
OP(60) { ADDC16( m_BA, rdop16() ); /* ??? */ }
OP(61) { ADDC16( m_HL, rdop16() ); /* ??? */ }
OP(62) { ADDC16( m_X, rdop16() ); /* ??? */ }
OP(63) { ADDC16( m_Y, rdop16() ); /* ??? */ }
OP(64) { /* illegal instruction? */ }
OP(65) { /* illegal instruction? */ }
OP(66) { /* illegal instruction? */ }
OP(67) { /* illegal instruction? */ }
OP(68) { minx->SP = ADD16( minx, minx->SP, rdop16(minx) ); }
OP(68) { m_SP = ADD16( m_SP, rdop16() ); }
OP(69) { /* illegal instruction? */ }
OP(6A) { minx->SP = SUB16( minx, minx->SP, rdop16(minx) ); }
OP(6A) { m_SP = SUB16( m_SP, rdop16() ); }
OP(6B) { /* illegal instruction? */ }
OP(6C) { SUB16( minx, minx->SP, rdop16(minx) ); }
OP(6C) { SUB16( m_SP, rdop16() ); }
OP(6D) { /* illegal instruction? */ }
OP(6E) { minx->SP = rdop16(minx); }
OP(6E) { m_SP = rdop16(); }
OP(6F) { /* illegal instruction? */ }
OP(70) { UINT8 ofs8 = rdop(minx); minx->BA = rd16( minx, minx->SP + ofs8 ); }
OP(71) { UINT8 ofs8 = rdop(minx); minx->HL = rd16( minx, minx->SP + ofs8 ); }
OP(72) { UINT8 ofs8 = rdop(minx); minx->X = rd16( minx, minx->SP + ofs8 ); }
OP(73) { UINT8 ofs8 = rdop(minx); minx->Y = rd16( minx, minx->SP + ofs8 ); }
OP(74) { UINT8 ofs8 = rdop(minx); wr16( minx, minx->SP + ofs8, minx->BA ); }
OP(75) { UINT8 ofs8 = rdop(minx); wr16( minx, minx->SP + ofs8, minx->HL ); }
OP(76) { UINT8 ofs8 = rdop(minx); wr16( minx, minx->SP + ofs8, minx->X ); }
OP(77) { UINT8 ofs8 = rdop(minx); wr16( minx, minx->SP + ofs8, minx->Y ); }
OP(78) { AD2_I16; minx->SP = rd16( minx, addr2 ); }
OP(70) { UINT8 ofs8 = rdop(); m_BA = rd16( m_SP + ofs8 ); }
OP(71) { UINT8 ofs8 = rdop(); m_HL = rd16( m_SP + ofs8 ); }
OP(72) { UINT8 ofs8 = rdop(); m_X = rd16( m_SP + ofs8 ); }
OP(73) { UINT8 ofs8 = rdop(); m_Y = rd16( m_SP + ofs8 ); }
OP(74) { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_BA ); }
OP(75) { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_HL ); }
OP(76) { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_X ); }
OP(77) { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_Y ); }
OP(78) { AD2_I16; m_SP = rd16( addr2 ); }
OP(79) { /* illegal instruction? */ }
OP(7A) { /* illegal instruction? */ }
OP(7B) { /* illegal instruction? */ }
OP(7C) { AD1_I16; wr16( minx, addr1, minx->SP ); }
OP(7C) { AD1_I16; wr16( addr1, m_SP ); }
OP(7D) { /* illegal instruction? */ }
OP(7E) { /* illegal instruction? */ }
OP(7F) { /* illegal instruction? */ }
@ -188,31 +188,31 @@ OP(AD) { /* illegal instruction? */ }
OP(AE) { /* illegal instruction? */ }
OP(AF) { /* illegal instruction? */ }
OP(B0) { PUSH8( minx, minx->BA & 0x00FF ); }
OP(B1) { PUSH8( minx, minx->BA >> 8 ); }
OP(B2) { PUSH8( minx, minx->HL & 0x00FF ); }
OP(B3) { PUSH8( minx, minx->HL >> 8 ); }
OP(B4) { minx->BA = ( minx->BA & 0xFF00 ) | POP8(minx); }
OP(B5) { minx->BA = ( minx->BA & 0x00FF ) | ( POP8(minx) << 8 ); }
OP(B6) { minx->HL = ( minx->HL & 0xFF00 ) | POP8(minx); }
OP(B7) { minx->HL = ( minx->HL & 0x00FF ) | ( POP8(minx) << 8 ); }
OP(B8) { PUSH16( minx, minx->BA ); PUSH16( minx, minx->HL ); PUSH16( minx, minx->X ); PUSH16( minx, minx->Y ); PUSH8( minx, minx->N ); }
OP(B9) { PUSH16( minx, minx->BA ); PUSH16( minx, minx->HL ); PUSH16( minx, minx->X ); PUSH16( minx, minx->Y ); PUSH8( minx, minx->N ); PUSH8( minx, minx->I ); PUSH8( minx, minx->XI ); PUSH8( minx, minx->YI ); }
OP(B0) { PUSH8( m_BA & 0x00FF ); }
OP(B1) { PUSH8( m_BA >> 8 ); }
OP(B2) { PUSH8( m_HL & 0x00FF ); }
OP(B3) { PUSH8( m_HL >> 8 ); }
OP(B4) { m_BA = ( m_BA & 0xFF00 ) | POP8(); }
OP(B5) { m_BA = ( m_BA & 0x00FF ) | ( POP8() << 8 ); }
OP(B6) { m_HL = ( m_HL & 0xFF00 ) | POP8(); }
OP(B7) { m_HL = ( m_HL & 0x00FF ) | ( POP8() << 8 ); }
OP(B8) { PUSH16( m_BA ); PUSH16( m_HL ); PUSH16( m_X ); PUSH16( m_Y ); PUSH8( m_N ); }
OP(B9) { PUSH16( m_BA ); PUSH16( m_HL ); PUSH16( m_X ); PUSH16( m_Y ); PUSH8( m_N ); PUSH8( m_I ); PUSH8( m_XI ); PUSH8( m_YI ); }
OP(BA) { /* illegal instruction? */ }
OP(BB) { /* illegal instruction? */ }
OP(BC) { minx->N = POP8(minx); minx->Y = POP16(minx); minx->X = POP16(minx); minx->HL = POP16(minx); minx->BA = POP16(minx); }
OP(BD) { minx->YI = POP8(minx); minx->XI = POP8(minx); minx->I = POP8(minx); minx->N = POP8(minx); minx->Y = POP16(minx); minx->X = POP16(minx); minx->HL = POP16(minx); minx->BA = POP16(minx); }
OP(BC) { m_N = POP8(); m_Y = POP16(); m_X = POP16(); m_HL = POP16(); m_BA = POP16(); }
OP(BD) { m_YI = POP8(); m_XI = POP8(); m_I = POP8(); m_N = POP8(); m_Y = POP16(); m_X = POP16(); m_HL = POP16(); m_BA = POP16(); }
OP(BE) { /* illegal instruction? */ }
OP(BF) { /* illegal instruction? */ }
OP(C0) { AD2_IHL; minx->BA = rd16( minx, addr2 ); }
OP(C1) { AD2_IHL; minx->HL = rd16( minx, addr2 ); }
OP(C2) { AD2_IHL; minx->X = rd16( minx, addr2 ); }
OP(C3) { AD2_IHL; minx->Y = rd16( minx, addr2 ); }
OP(C4) { AD1_IHL; wr16( minx, addr1, minx->BA ); }
OP(C5) { AD1_IHL; wr16( minx, addr1, minx->HL ); }
OP(C6) { AD1_IHL; wr16( minx, addr1, minx->X ); }
OP(C7) { AD1_IHL; wr16( minx, addr1, minx->Y ); }
OP(C0) { AD2_IHL; m_BA = rd16( addr2 ); }
OP(C1) { AD2_IHL; m_HL = rd16( addr2 ); }
OP(C2) { AD2_IHL; m_X = rd16( addr2 ); }
OP(C3) { AD2_IHL; m_Y = rd16( addr2 ); }
OP(C4) { AD1_IHL; wr16( addr1, m_BA ); }
OP(C5) { AD1_IHL; wr16( addr1, m_HL ); }
OP(C6) { AD1_IHL; wr16( addr1, m_X ); }
OP(C7) { AD1_IHL; wr16( addr1, m_Y ); }
OP(C8) { /* illegal instruction? */ }
OP(C9) { /* illegal instruction? */ }
OP(CA) { /* illegal instruction? */ }
@ -222,110 +222,110 @@ OP(CD) { /* illegal instruction? */ }
OP(CE) { /* illegal instruction? */ }
OP(CF) { /* illegal instruction? */ }
OP(D0) { AD2_XIX; minx->BA = rd16( minx, addr2 ); }
OP(D1) { AD2_XIX; minx->HL = rd16( minx, addr2 ); }
OP(D2) { AD2_XIX; minx->X = rd16( minx, addr2 ); }
OP(D3) { AD2_XIX; minx->Y = rd16( minx, addr2 ); }
OP(D4) { AD1_XIX; wr16( minx, addr1, minx->BA ); }
OP(D5) { AD1_XIX; wr16( minx, addr1, minx->HL ); }
OP(D6) { AD1_XIX; wr16( minx, addr1, minx->X ); }
OP(D7) { AD1_XIX; wr16( minx, addr1, minx->Y ); }
OP(D8) { AD2_YIY; minx->BA = rd16( minx, addr2 ); }
OP(D9) { AD2_YIY; minx->HL = rd16( minx, addr2 ); }
OP(DA) { AD2_YIY; minx->X = rd16( minx, addr2 ); }
OP(DB) { AD2_YIY; minx->Y = rd16( minx, addr2 ); }
OP(DC) { AD1_YIY; wr16( minx, addr1, minx->BA ); }
OP(DD) { AD1_YIY; wr16( minx, addr1, minx->HL ); }
OP(DE) { AD1_YIY; wr16( minx, addr1, minx->X ); }
OP(DF) { AD1_YIY; wr16( minx, addr1, minx->Y ); }
OP(D0) { AD2_XIX; m_BA = rd16( addr2 ); }
OP(D1) { AD2_XIX; m_HL = rd16( addr2 ); }
OP(D2) { AD2_XIX; m_X = rd16( addr2 ); }
OP(D3) { AD2_XIX; m_Y = rd16( addr2 ); }
OP(D4) { AD1_XIX; wr16( addr1, m_BA ); }
OP(D5) { AD1_XIX; wr16( addr1, m_HL ); }
OP(D6) { AD1_XIX; wr16( addr1, m_X ); }
OP(D7) { AD1_XIX; wr16( addr1, m_Y ); }
OP(D8) { AD2_YIY; m_BA = rd16( addr2 ); }
OP(D9) { AD2_YIY; m_HL = rd16( addr2 ); }
OP(DA) { AD2_YIY; m_X = rd16( addr2 ); }
OP(DB) { AD2_YIY; m_Y = rd16( addr2 ); }
OP(DC) { AD1_YIY; wr16( addr1, m_BA ); }
OP(DD) { AD1_YIY; wr16( addr1, m_HL ); }
OP(DE) { AD1_YIY; wr16( addr1, m_X ); }
OP(DF) { AD1_YIY; wr16( addr1, m_Y ); }
OP(E0) { minx->BA = minx->BA; }
OP(E1) { minx->BA = minx->HL; }
OP(E2) { minx->BA = minx->X; }
OP(E3) { minx->BA = minx->Y; }
OP(E4) { minx->HL = minx->BA; }
OP(E5) { minx->HL = minx->HL; }
OP(E6) { minx->HL = minx->X; }
OP(E7) { minx->HL = minx->Y; }
OP(E8) { minx->X = minx->BA; }
OP(E9) { minx->X = minx->HL; }
OP(EA) { minx->X = minx->X; }
OP(EB) { minx->X = minx->Y; }
OP(EC) { minx->Y = minx->BA; }
OP(ED) { minx->Y = minx->HL; }
OP(EE) { minx->Y = minx->X; }
OP(EF) { minx->Y = minx->Y; }
OP(E0) { m_BA = m_BA; }
OP(E1) { m_BA = m_HL; }
OP(E2) { m_BA = m_X; }
OP(E3) { m_BA = m_Y; }
OP(E4) { m_HL = m_BA; }
OP(E5) { m_HL = m_HL; }
OP(E6) { m_HL = m_X; }
OP(E7) { m_HL = m_Y; }
OP(E8) { m_X = m_BA; }
OP(E9) { m_X = m_HL; }
OP(EA) { m_X = m_X; }
OP(EB) { m_X = m_Y; }
OP(EC) { m_Y = m_BA; }
OP(ED) { m_Y = m_HL; }
OP(EE) { m_Y = m_X; }
OP(EF) { m_Y = m_Y; }
OP(F0) { minx->SP = minx->BA; }
OP(F1) { minx->SP = minx->HL; }
OP(F2) { minx->SP = minx->X; }
OP(F3) { minx->SP = minx->Y; }
OP(F4) { minx->HL = minx->SP; }
OP(F5) { minx->HL = minx->PC; }
OP(F0) { m_SP = m_BA; }
OP(F1) { m_SP = m_HL; }
OP(F2) { m_SP = m_X; }
OP(F3) { m_SP = m_Y; }
OP(F4) { m_HL = m_SP; }
OP(F5) { m_HL = m_PC; }
OP(F6) { /* illegal instruction? */ }
OP(F7) { /* illegal instruction? */ }
OP(F8) { minx->BA = minx->SP; }
OP(F9) { minx->BA = minx->PC; }
OP(FA) { minx->X = minx->SP; }
OP(F8) { m_BA = m_SP; }
OP(F9) { m_BA = m_PC; }
OP(FA) { m_X = m_SP; }
OP(FB) { /* illegal instruction? */ }
OP(FC) { /* illegal instruction? */ }
OP(FD) { /* illegal instruction? */ }
OP(FE) { minx->Y = minx->SP; }
OP(FE) { m_Y = m_SP; }
OP(FF) { /* illegal instruction? */ }
static void (*const insnminx_CF[256])(minx_state *minx) = {
minx_CF_00, minx_CF_01, minx_CF_02, minx_CF_03, minx_CF_04, minx_CF_05, minx_CF_06, minx_CF_07,
minx_CF_08, minx_CF_09, minx_CF_0A, minx_CF_0B, minx_CF_0C, minx_CF_0D, minx_CF_0E, minx_CF_0F,
minx_CF_10, minx_CF_11, minx_CF_12, minx_CF_13, minx_CF_14, minx_CF_15, minx_CF_16, minx_CF_17,
minx_CF_18, minx_CF_19, minx_CF_1A, minx_CF_1B, minx_CF_1C, minx_CF_1D, minx_CF_1E, minx_CF_1F,
minx_CF_20, minx_CF_21, minx_CF_22, minx_CF_23, minx_CF_24, minx_CF_25, minx_CF_26, minx_CF_27,
minx_CF_28, minx_CF_29, minx_CF_2A, minx_CF_2B, minx_CF_2C, minx_CF_2D, minx_CF_2E, minx_CF_2F,
minx_CF_30, minx_CF_31, minx_CF_32, minx_CF_33, minx_CF_34, minx_CF_35, minx_CF_36, minx_CF_37,
minx_CF_38, minx_CF_39, minx_CF_3A, minx_CF_3B, minx_CF_3C, minx_CF_3D, minx_CF_3E, minx_CF_3F,
minx_CF_40, minx_CF_41, minx_CF_42, minx_CF_43, minx_CF_44, minx_CF_45, minx_CF_46, minx_CF_47,
minx_CF_48, minx_CF_49, minx_CF_4A, minx_CF_4B, minx_CF_4C, minx_CF_4D, minx_CF_4E, minx_CF_4F,
minx_CF_50, minx_CF_51, minx_CF_52, minx_CF_53, minx_CF_54, minx_CF_55, minx_CF_56, minx_CF_57,
minx_CF_58, minx_CF_59, minx_CF_5A, minx_CF_5B, minx_CF_5C, minx_CF_5D, minx_CF_5E, minx_CF_5F,
minx_CF_60, minx_CF_61, minx_CF_62, minx_CF_63, minx_CF_64, minx_CF_65, minx_CF_66, minx_CF_67,
minx_CF_68, minx_CF_69, minx_CF_6A, minx_CF_6B, minx_CF_6C, minx_CF_6D, minx_CF_6E, minx_CF_6F,
minx_CF_70, minx_CF_71, minx_CF_72, minx_CF_73, minx_CF_74, minx_CF_75, minx_CF_76, minx_CF_77,
minx_CF_78, minx_CF_79, minx_CF_7A, minx_CF_7B, minx_CF_7C, minx_CF_7D, minx_CF_7E, minx_CF_7F,
minx_CF_80, minx_CF_81, minx_CF_82, minx_CF_83, minx_CF_84, minx_CF_85, minx_CF_86, minx_CF_87,
minx_CF_88, minx_CF_89, minx_CF_8A, minx_CF_8B, minx_CF_8C, minx_CF_8D, minx_CF_8E, minx_CF_8F,
minx_CF_90, minx_CF_91, minx_CF_92, minx_CF_93, minx_CF_94, minx_CF_95, minx_CF_96, minx_CF_97,
minx_CF_98, minx_CF_99, minx_CF_9A, minx_CF_9B, minx_CF_9C, minx_CF_9D, minx_CF_9E, minx_CF_9F,
minx_CF_A0, minx_CF_A1, minx_CF_A2, minx_CF_A3, minx_CF_A4, minx_CF_A5, minx_CF_A6, minx_CF_A7,
minx_CF_A8, minx_CF_A9, minx_CF_AA, minx_CF_AB, minx_CF_AC, minx_CF_AD, minx_CF_AE, minx_CF_AF,
minx_CF_B0, minx_CF_B1, minx_CF_B2, minx_CF_B3, minx_CF_B4, minx_CF_B5, minx_CF_B6, minx_CF_B7,
minx_CF_B8, minx_CF_B9, minx_CF_BA, minx_CF_BB, minx_CF_BC, minx_CF_BD, minx_CF_BE, minx_CF_BF,
minx_CF_C0, minx_CF_C1, minx_CF_C2, minx_CF_C3, minx_CF_C4, minx_CF_C5, minx_CF_C6, minx_CF_C7,
minx_CF_C8, minx_CF_C9, minx_CF_CA, minx_CF_CB, minx_CF_CC, minx_CF_CD, minx_CF_CE, minx_CF_CF,
minx_CF_D0, minx_CF_D1, minx_CF_D2, minx_CF_D3, minx_CF_D4, minx_CF_D5, minx_CF_D6, minx_CF_D7,
minx_CF_D8, minx_CF_D9, minx_CF_DA, minx_CF_DB, minx_CF_DC, minx_CF_DD, minx_CF_DE, minx_CF_DF,
minx_CF_E0, minx_CF_E1, minx_CF_E2, minx_CF_E3, minx_CF_E4, minx_CF_E5, minx_CF_E6, minx_CF_E7,
minx_CF_E8, minx_CF_E9, minx_CF_EA, minx_CF_EB, minx_CF_EC, minx_CF_ED, minx_CF_EE, minx_CF_EF,
minx_CF_F0, minx_CF_F1, minx_CF_F2, minx_CF_F3, minx_CF_F4, minx_CF_F5, minx_CF_F6, minx_CF_F7,
minx_CF_F8, minx_CF_F9, minx_CF_FA, minx_CF_FB, minx_CF_FC, minx_CF_FD, minx_CF_FE, minx_CF_FF
const minx_cpu_device::op_func minx_cpu_device::insnminx_CF[256] = {
&minx_cpu_device::minx_CF_00, &minx_cpu_device::minx_CF_01, &minx_cpu_device::minx_CF_02, &minx_cpu_device::minx_CF_03, &minx_cpu_device::minx_CF_04, &minx_cpu_device::minx_CF_05, &minx_cpu_device::minx_CF_06, &minx_cpu_device::minx_CF_07,
&minx_cpu_device::minx_CF_08, &minx_cpu_device::minx_CF_09, &minx_cpu_device::minx_CF_0A, &minx_cpu_device::minx_CF_0B, &minx_cpu_device::minx_CF_0C, &minx_cpu_device::minx_CF_0D, &minx_cpu_device::minx_CF_0E, &minx_cpu_device::minx_CF_0F,
&minx_cpu_device::minx_CF_10, &minx_cpu_device::minx_CF_11, &minx_cpu_device::minx_CF_12, &minx_cpu_device::minx_CF_13, &minx_cpu_device::minx_CF_14, &minx_cpu_device::minx_CF_15, &minx_cpu_device::minx_CF_16, &minx_cpu_device::minx_CF_17,
&minx_cpu_device::minx_CF_18, &minx_cpu_device::minx_CF_19, &minx_cpu_device::minx_CF_1A, &minx_cpu_device::minx_CF_1B, &minx_cpu_device::minx_CF_1C, &minx_cpu_device::minx_CF_1D, &minx_cpu_device::minx_CF_1E, &minx_cpu_device::minx_CF_1F,
&minx_cpu_device::minx_CF_20, &minx_cpu_device::minx_CF_21, &minx_cpu_device::minx_CF_22, &minx_cpu_device::minx_CF_23, &minx_cpu_device::minx_CF_24, &minx_cpu_device::minx_CF_25, &minx_cpu_device::minx_CF_26, &minx_cpu_device::minx_CF_27,
&minx_cpu_device::minx_CF_28, &minx_cpu_device::minx_CF_29, &minx_cpu_device::minx_CF_2A, &minx_cpu_device::minx_CF_2B, &minx_cpu_device::minx_CF_2C, &minx_cpu_device::minx_CF_2D, &minx_cpu_device::minx_CF_2E, &minx_cpu_device::minx_CF_2F,
&minx_cpu_device::minx_CF_30, &minx_cpu_device::minx_CF_31, &minx_cpu_device::minx_CF_32, &minx_cpu_device::minx_CF_33, &minx_cpu_device::minx_CF_34, &minx_cpu_device::minx_CF_35, &minx_cpu_device::minx_CF_36, &minx_cpu_device::minx_CF_37,
&minx_cpu_device::minx_CF_38, &minx_cpu_device::minx_CF_39, &minx_cpu_device::minx_CF_3A, &minx_cpu_device::minx_CF_3B, &minx_cpu_device::minx_CF_3C, &minx_cpu_device::minx_CF_3D, &minx_cpu_device::minx_CF_3E, &minx_cpu_device::minx_CF_3F,
&minx_cpu_device::minx_CF_40, &minx_cpu_device::minx_CF_41, &minx_cpu_device::minx_CF_42, &minx_cpu_device::minx_CF_43, &minx_cpu_device::minx_CF_44, &minx_cpu_device::minx_CF_45, &minx_cpu_device::minx_CF_46, &minx_cpu_device::minx_CF_47,
&minx_cpu_device::minx_CF_48, &minx_cpu_device::minx_CF_49, &minx_cpu_device::minx_CF_4A, &minx_cpu_device::minx_CF_4B, &minx_cpu_device::minx_CF_4C, &minx_cpu_device::minx_CF_4D, &minx_cpu_device::minx_CF_4E, &minx_cpu_device::minx_CF_4F,
&minx_cpu_device::minx_CF_50, &minx_cpu_device::minx_CF_51, &minx_cpu_device::minx_CF_52, &minx_cpu_device::minx_CF_53, &minx_cpu_device::minx_CF_54, &minx_cpu_device::minx_CF_55, &minx_cpu_device::minx_CF_56, &minx_cpu_device::minx_CF_57,
&minx_cpu_device::minx_CF_58, &minx_cpu_device::minx_CF_59, &minx_cpu_device::minx_CF_5A, &minx_cpu_device::minx_CF_5B, &minx_cpu_device::minx_CF_5C, &minx_cpu_device::minx_CF_5D, &minx_cpu_device::minx_CF_5E, &minx_cpu_device::minx_CF_5F,
&minx_cpu_device::minx_CF_60, &minx_cpu_device::minx_CF_61, &minx_cpu_device::minx_CF_62, &minx_cpu_device::minx_CF_63, &minx_cpu_device::minx_CF_64, &minx_cpu_device::minx_CF_65, &minx_cpu_device::minx_CF_66, &minx_cpu_device::minx_CF_67,
&minx_cpu_device::minx_CF_68, &minx_cpu_device::minx_CF_69, &minx_cpu_device::minx_CF_6A, &minx_cpu_device::minx_CF_6B, &minx_cpu_device::minx_CF_6C, &minx_cpu_device::minx_CF_6D, &minx_cpu_device::minx_CF_6E, &minx_cpu_device::minx_CF_6F,
&minx_cpu_device::minx_CF_70, &minx_cpu_device::minx_CF_71, &minx_cpu_device::minx_CF_72, &minx_cpu_device::minx_CF_73, &minx_cpu_device::minx_CF_74, &minx_cpu_device::minx_CF_75, &minx_cpu_device::minx_CF_76, &minx_cpu_device::minx_CF_77,
&minx_cpu_device::minx_CF_78, &minx_cpu_device::minx_CF_79, &minx_cpu_device::minx_CF_7A, &minx_cpu_device::minx_CF_7B, &minx_cpu_device::minx_CF_7C, &minx_cpu_device::minx_CF_7D, &minx_cpu_device::minx_CF_7E, &minx_cpu_device::minx_CF_7F,
&minx_cpu_device::minx_CF_80, &minx_cpu_device::minx_CF_81, &minx_cpu_device::minx_CF_82, &minx_cpu_device::minx_CF_83, &minx_cpu_device::minx_CF_84, &minx_cpu_device::minx_CF_85, &minx_cpu_device::minx_CF_86, &minx_cpu_device::minx_CF_87,
&minx_cpu_device::minx_CF_88, &minx_cpu_device::minx_CF_89, &minx_cpu_device::minx_CF_8A, &minx_cpu_device::minx_CF_8B, &minx_cpu_device::minx_CF_8C, &minx_cpu_device::minx_CF_8D, &minx_cpu_device::minx_CF_8E, &minx_cpu_device::minx_CF_8F,
&minx_cpu_device::minx_CF_90, &minx_cpu_device::minx_CF_91, &minx_cpu_device::minx_CF_92, &minx_cpu_device::minx_CF_93, &minx_cpu_device::minx_CF_94, &minx_cpu_device::minx_CF_95, &minx_cpu_device::minx_CF_96, &minx_cpu_device::minx_CF_97,
&minx_cpu_device::minx_CF_98, &minx_cpu_device::minx_CF_99, &minx_cpu_device::minx_CF_9A, &minx_cpu_device::minx_CF_9B, &minx_cpu_device::minx_CF_9C, &minx_cpu_device::minx_CF_9D, &minx_cpu_device::minx_CF_9E, &minx_cpu_device::minx_CF_9F,
&minx_cpu_device::minx_CF_A0, &minx_cpu_device::minx_CF_A1, &minx_cpu_device::minx_CF_A2, &minx_cpu_device::minx_CF_A3, &minx_cpu_device::minx_CF_A4, &minx_cpu_device::minx_CF_A5, &minx_cpu_device::minx_CF_A6, &minx_cpu_device::minx_CF_A7,
&minx_cpu_device::minx_CF_A8, &minx_cpu_device::minx_CF_A9, &minx_cpu_device::minx_CF_AA, &minx_cpu_device::minx_CF_AB, &minx_cpu_device::minx_CF_AC, &minx_cpu_device::minx_CF_AD, &minx_cpu_device::minx_CF_AE, &minx_cpu_device::minx_CF_AF,
&minx_cpu_device::minx_CF_B0, &minx_cpu_device::minx_CF_B1, &minx_cpu_device::minx_CF_B2, &minx_cpu_device::minx_CF_B3, &minx_cpu_device::minx_CF_B4, &minx_cpu_device::minx_CF_B5, &minx_cpu_device::minx_CF_B6, &minx_cpu_device::minx_CF_B7,
&minx_cpu_device::minx_CF_B8, &minx_cpu_device::minx_CF_B9, &minx_cpu_device::minx_CF_BA, &minx_cpu_device::minx_CF_BB, &minx_cpu_device::minx_CF_BC, &minx_cpu_device::minx_CF_BD, &minx_cpu_device::minx_CF_BE, &minx_cpu_device::minx_CF_BF,
&minx_cpu_device::minx_CF_C0, &minx_cpu_device::minx_CF_C1, &minx_cpu_device::minx_CF_C2, &minx_cpu_device::minx_CF_C3, &minx_cpu_device::minx_CF_C4, &minx_cpu_device::minx_CF_C5, &minx_cpu_device::minx_CF_C6, &minx_cpu_device::minx_CF_C7,
&minx_cpu_device::minx_CF_C8, &minx_cpu_device::minx_CF_C9, &minx_cpu_device::minx_CF_CA, &minx_cpu_device::minx_CF_CB, &minx_cpu_device::minx_CF_CC, &minx_cpu_device::minx_CF_CD, &minx_cpu_device::minx_CF_CE, &minx_cpu_device::minx_CF_CF,
&minx_cpu_device::minx_CF_D0, &minx_cpu_device::minx_CF_D1, &minx_cpu_device::minx_CF_D2, &minx_cpu_device::minx_CF_D3, &minx_cpu_device::minx_CF_D4, &minx_cpu_device::minx_CF_D5, &minx_cpu_device::minx_CF_D6, &minx_cpu_device::minx_CF_D7,
&minx_cpu_device::minx_CF_D8, &minx_cpu_device::minx_CF_D9, &minx_cpu_device::minx_CF_DA, &minx_cpu_device::minx_CF_DB, &minx_cpu_device::minx_CF_DC, &minx_cpu_device::minx_CF_DD, &minx_cpu_device::minx_CF_DE, &minx_cpu_device::minx_CF_DF,
&minx_cpu_device::minx_CF_E0, &minx_cpu_device::minx_CF_E1, &minx_cpu_device::minx_CF_E2, &minx_cpu_device::minx_CF_E3, &minx_cpu_device::minx_CF_E4, &minx_cpu_device::minx_CF_E5, &minx_cpu_device::minx_CF_E6, &minx_cpu_device::minx_CF_E7,
&minx_cpu_device::minx_CF_E8, &minx_cpu_device::minx_CF_E9, &minx_cpu_device::minx_CF_EA, &minx_cpu_device::minx_CF_EB, &minx_cpu_device::minx_CF_EC, &minx_cpu_device::minx_CF_ED, &minx_cpu_device::minx_CF_EE, &minx_cpu_device::minx_CF_EF,
&minx_cpu_device::minx_CF_F0, &minx_cpu_device::minx_CF_F1, &minx_cpu_device::minx_CF_F2, &minx_cpu_device::minx_CF_F3, &minx_cpu_device::minx_CF_F4, &minx_cpu_device::minx_CF_F5, &minx_cpu_device::minx_CF_F6, &minx_cpu_device::minx_CF_F7,
&minx_cpu_device::minx_CF_F8, &minx_cpu_device::minx_CF_F9, &minx_cpu_device::minx_CF_FA, &minx_cpu_device::minx_CF_FB, &minx_cpu_device::minx_CF_FC, &minx_cpu_device::minx_CF_FD, &minx_cpu_device::minx_CF_FE, &minx_cpu_device::minx_CF_FF
};
static const int insnminx_cycles_CF[256] = {
const int minx_cpu_device::insnminx_cycles_CF[256] = {
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 16, 16, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 16, 16, 1, 1, 1, 1,
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 16, 16, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 16, 16, 1, 1, 1, 1,
16, 16, 16, 16, 16, 16, 1, 1, 16, 16, 16, 16, 16, 16, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 1, 1,
16, 16, 16, 16, 1, 1, 1, 1, 16, 1, 16, 1, 16, 1, 16, 1,
24, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 24, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
12, 12, 12, 12, 12, 12, 12, 12, 48, 60, 1, 1, 32, 40, 1, 1,
20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 1, 1, 8, 8, 8, 1, 1, 1, 8, 1
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 1, 1, 8, 8, 8, 1, 1, 1, 8, 1
};

568
src/emu/cpu/minx/minxops.h
View File

@ -1,331 +1,331 @@
#undef OP
#define OP(nn) INLINE void minx_##nn(minx_state *minx)
#define OP(nn) void minx_cpu_device::minx_##nn()
OP(00) { minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); }
OP(01) { minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); }
OP(02) { minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); }
OP(03) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(04) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(05) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(06) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(07) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(08) { minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); }
OP(09) { minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); }
OP(0A) { minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); }
OP(0B) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(0C) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(0D) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(0E) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(0F) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(00) { m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
OP(01) { m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
OP(02) { m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), rdop() ); }
OP(03) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(04) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(05) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(06) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(07) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(08) { m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
OP(09) { m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
OP(0A) { m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), rdop() ); }
OP(0B) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(0C) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(0D) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(0E) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(0F) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(10) { minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); }
OP(11) { minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); }
OP(12) { minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); }
OP(13) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(14) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(15) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(16) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(17) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(18) { minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); }
OP(19) { minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); }
OP(1A) { minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); }
OP(1B) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(1C) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(1D) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(1E) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(1F) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(10) { m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
OP(11) { m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
OP(12) { m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), rdop() ); }
OP(13) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(14) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(15) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(16) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(17) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(18) { m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
OP(19) { m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
OP(1A) { m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), rdop() ); }
OP(1B) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(1C) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(1D) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(1E) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(1F) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(20) { minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); }
OP(21) { minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); }
OP(22) { minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); }
OP(23) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(24) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(25) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(26) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(27) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(28) { minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); }
OP(29) { minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); }
OP(2A) { minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); }
OP(2B) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(2C) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(2D) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(2E) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(2F) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(20) { m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
OP(21) { m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
OP(22) { m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), rdop() ); }
OP(23) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(24) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(25) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(26) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(27) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(28) { m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
OP(29) { m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
OP(2A) { m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), rdop() ); }
OP(2B) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(2C) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(2D) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(2E) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(2F) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(30) { SUB8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); }
OP(31) { SUB8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); }
OP(32) { SUB8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); }
OP(33) { AD2_IHL; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(34) { AD2_IN8; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(35) { AD2_I16; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(36) { AD2_XIX; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(37) { AD2_YIY; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(38) { minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); }
OP(39) { minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); }
OP(3A) { minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); }
OP(3B) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(3C) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(3D) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(3E) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(3F) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); }
OP(30) { SUB8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
OP(31) { SUB8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
OP(32) { SUB8( ( m_BA & 0x00FF ), rdop() ); }
OP(33) { AD2_IHL; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(34) { AD2_IN8; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(35) { AD2_I16; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(36) { AD2_XIX; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(37) { AD2_YIY; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(38) { m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
OP(39) { m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
OP(3A) { m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), rdop() ); }
OP(3B) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(3C) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(3D) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(3E) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(3F) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
OP(40) { minx->BA = ( minx->BA & 0xFF00 ) | ( minx->BA & 0x00FF); }
OP(41) { minx->BA = ( minx->BA & 0xFF00 ) | ( minx->BA >> 8 ); }
OP(42) { minx->BA = ( minx->BA & 0xFF00 ) | ( minx->HL & 0x00FF); }
OP(43) { minx->BA = ( minx->BA & 0xFF00 ) | ( minx->HL >> 8 ); }
OP(44) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); }
OP(45) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); }
OP(46) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); }
OP(47) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); }
OP(48) { minx->BA = ( minx->BA & 0x00FF ) | ( ( minx->BA & 0x00FF) << 8 ); }
OP(49) { minx->BA = ( minx->BA & 0x00FF ) | ( ( minx->BA >> 8 ) << 8 ); }
OP(4A) { minx->BA = ( minx->BA & 0x00FF ) | ( ( minx->HL & 0x00FF) << 8 ); }
OP(4B) { minx->BA = ( minx->BA & 0x00FF ) | ( ( minx->HL >> 8 ) << 8 ); }
OP(4C) { AD2_IN8; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4D) { AD2_IHL; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4E) { AD2_XIX; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4F) { AD2_YIY; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(40) { m_BA = ( m_BA & 0xFF00 ) | ( m_BA & 0x00FF); }
OP(41) { m_BA = ( m_BA & 0xFF00 ) | ( m_BA >> 8 ); }
OP(42) { m_BA = ( m_BA & 0xFF00 ) | ( m_HL & 0x00FF); }
OP(43) { m_BA = ( m_BA & 0xFF00 ) | ( m_HL >> 8 ); }
OP(44) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
OP(45) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
OP(46) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
OP(47) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
OP(48) { m_BA = ( m_BA & 0x00FF ) | ( ( m_BA & 0x00FF) << 8 ); }
OP(49) { m_BA = ( m_BA & 0x00FF ) | ( ( m_BA >> 8 ) << 8 ); }
OP(4A) { m_BA = ( m_BA & 0x00FF ) | ( ( m_HL & 0x00FF) << 8 ); }
OP(4B) { m_BA = ( m_BA & 0x00FF ) | ( ( m_HL >> 8 ) << 8 ); }
OP(4C) { AD2_IN8; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4D) { AD2_IHL; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4E) { AD2_XIX; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(4F) { AD2_YIY; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(50) { minx->HL = ( minx->HL & 0xFF00 ) | ( minx->BA & 0x00FF); }
OP(51) { minx->HL = ( minx->HL & 0xFF00 ) | ( minx->BA >> 8 ); }
OP(52) { minx->HL = ( minx->HL & 0xFF00 ) | ( minx->HL & 0x00FF); }
OP(53) { minx->HL = ( minx->HL & 0xFF00 ) | ( minx->HL >> 8 ); }
OP(54) { AD2_IN8; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); }
OP(55) { AD2_IHL; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); }
OP(56) { AD2_XIX; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); }
OP(57) { AD2_YIY; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); }
OP(58) { minx->HL = ( minx->HL & 0x00FF ) | ( ( minx->BA & 0x00FF) << 8 ); }
OP(59) { minx->HL = ( minx->HL & 0x00FF ) | ( ( minx->BA >> 8 ) << 8 ); }
OP(5A) { minx->HL = ( minx->HL & 0x00FF ) | ( ( minx->HL & 0x00FF) << 8 ); }
OP(5B) { minx->HL = ( minx->HL & 0x00FF ) | ( ( minx->HL >> 8 ) << 8 ); }
OP(5C) { AD2_IN8; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5D) { AD2_IHL; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5E) { AD2_XIX; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5F) { AD2_YIY; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(50) { m_HL = ( m_HL & 0xFF00 ) | ( m_BA & 0x00FF); }
OP(51) { m_HL = ( m_HL & 0xFF00 ) | ( m_BA >> 8 ); }
OP(52) { m_HL = ( m_HL & 0xFF00 ) | ( m_HL & 0x00FF); }
OP(53) { m_HL = ( m_HL & 0xFF00 ) | ( m_HL >> 8 ); }
OP(54) { AD2_IN8; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
OP(55) { AD2_IHL; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
OP(56) { AD2_XIX; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
OP(57) { AD2_YIY; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
OP(58) { m_HL = ( m_HL & 0x00FF ) | ( ( m_BA & 0x00FF) << 8 ); }
OP(59) { m_HL = ( m_HL & 0x00FF ) | ( ( m_BA >> 8 ) << 8 ); }
OP(5A) { m_HL = ( m_HL & 0x00FF ) | ( ( m_HL & 0x00FF) << 8 ); }
OP(5B) { m_HL = ( m_HL & 0x00FF ) | ( ( m_HL >> 8 ) << 8 ); }
OP(5C) { AD2_IN8; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5D) { AD2_IHL; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5E) { AD2_XIX; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(5F) { AD2_YIY; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
OP(60) { AD1_XIX; WR( addr1, ( minx->BA & 0x00FF ) ); }
OP(61) { AD1_XIX; WR( addr1, ( minx->BA >> 8 ) ); }
OP(62) { AD1_XIX; WR( addr1, ( minx->HL & 0x00FF ) ); }
OP(63) { AD1_XIX; WR( addr1, ( minx->HL >> 8 ) ); }
OP(60) { AD1_XIX; WR( addr1, ( m_BA & 0x00FF ) ); }
OP(61) { AD1_XIX; WR( addr1, ( m_BA >> 8 ) ); }
OP(62) { AD1_XIX; WR( addr1, ( m_HL & 0x00FF ) ); }
OP(63) { AD1_XIX; WR( addr1, ( m_HL >> 8 ) ); }
OP(64) { AD1_XIX; AD2_IN8; WR( addr1, RD( addr2 ) ); }
OP(65) { AD1_XIX; AD2_IHL; WR( addr1, RD( addr2 ) ); }
OP(66) { AD1_XIX; AD2_XIX; WR( addr1, RD( addr2 ) ); }
OP(67) { AD1_XIX; AD2_YIY; WR( addr1, RD( addr2 ) ); }
OP(68) { AD1_IHL; WR( addr1, ( minx->BA & 0x00FF ) ); }
OP(69) { AD1_IHL; WR( addr1, ( minx->BA >> 8 ) ); }
OP(6A) { AD1_IHL; WR( addr1, ( minx->HL & 0x00FF ) ); }
OP(6B) { AD1_IHL; WR( addr1, ( minx->HL >> 8 ) ); }
OP(68) { AD1_IHL; WR( addr1, ( m_BA & 0x00FF ) ); }
OP(69) { AD1_IHL; WR( addr1, ( m_BA >> 8 ) ); }
OP(6A) { AD1_IHL; WR( addr1, ( m_HL & 0x00FF ) ); }
OP(6B) { AD1_IHL; WR( addr1, ( m_HL >> 8 ) ); }
OP(6C) { AD1_IHL; AD2_IN8; WR( addr1, RD( addr2 ) ); }
OP(6D) { AD1_IHL; AD2_IHL; WR( addr1, RD( addr2 ) ); }
OP(6E) { AD1_IHL; AD2_XIX; WR( addr1, RD( addr2 ) ); }
OP(6F) { AD1_IHL; AD2_YIY; WR( addr1, RD( addr2 ) ); }
OP(70) { AD1_YIY; WR( addr1, ( minx->BA & 0x00FF ) ); }
OP(71) { AD1_YIY; WR( addr1, ( minx->BA >> 8 ) ); }
OP(72) { AD1_YIY; WR( addr1, ( minx->HL & 0x00FF ) ); }
OP(73) { AD1_YIY; WR( addr1, ( minx->HL >> 8 ) ); }
OP(70) { AD1_YIY; WR( addr1, ( m_BA & 0x00FF ) ); }
OP(71) { AD1_YIY; WR( addr1, ( m_BA >> 8 ) ); }
OP(72) { AD1_YIY; WR( addr1, ( m_HL & 0x00FF ) ); }
OP(73) { AD1_YIY; WR( addr1, ( m_HL >> 8 ) ); }
OP(74) { AD1_YIY; AD2_IN8; WR( addr1, RD( addr2 ) ); }
OP(75) { AD1_YIY; AD2_IHL; WR( addr1, RD( addr2 ) ); }
OP(76) { AD1_YIY; AD2_XIX; WR( addr1, RD( addr2 ) ); }
OP(77) { AD1_YIY; AD2_YIY; WR( addr1, RD( addr2 ) ); }
OP(78) { AD1_IN8; WR( addr1, ( minx->BA & 0x00FF ) ); }
OP(79) { AD1_IN8; WR( addr1, ( minx->BA >> 8 ) ); }
OP(7A) { AD1_IN8; WR( addr1, ( minx->HL & 0x00FF ) ); }
OP(7B) { AD1_IN8; WR( addr1, ( minx->HL >> 8 ) ); }
OP(78) { AD1_IN8; WR( addr1, ( m_BA & 0x00FF ) ); }
OP(79) { AD1_IN8; WR( addr1, ( m_BA >> 8 ) ); }
OP(7A) { AD1_IN8; WR( addr1, ( m_HL & 0x00FF ) ); }
OP(7B) { AD1_IN8; WR( addr1, ( m_HL >> 8 ) ); }
OP(7C) { /* illegal operation? */ }
OP(7D) { AD1_IN8; AD2_IHL; WR( addr1, RD( addr2 ) ); }
OP(7E) { AD1_IN8; AD2_XIX; WR( addr1, RD( addr2 ) ); }
OP(7F) { AD1_IN8; AD2_YIY; WR( addr1, RD( addr2 ) ); }
OP(80) { minx->BA = ( minx->BA & 0xFF00 ) | INC8( minx, minx->BA & 0x00FF ); }
OP(81) { minx->BA = ( minx->BA & 0x00FF ) | ( INC8( minx, minx->BA >> 8 ) << 8 ); }
OP(82) { minx->HL = ( minx->HL & 0xFF00 ) | INC8( minx, minx->HL & 0x00FF ); }
OP(83) { minx->HL = ( minx->HL & 0x00FF ) | ( INC8( minx, minx->HL >> 8 ) << 8 ); }
OP(84) { minx->N = INC8( minx, minx->N ); }
OP(85) { AD1_IN8; WR( addr1, INC8( minx, RD( addr1 ) ) ); }
OP(86) { AD1_IHL; WR( addr1, INC8( minx, RD( addr1 ) ) ); }
OP(87) { minx->SP = INC16( minx, minx->SP ); }
OP(88) { minx->BA = ( minx->BA & 0xFF00 ) | DEC8( minx, minx->BA & 0x00FF ); }
OP(89) { minx->BA = ( minx->BA & 0x00FF ) | ( DEC8( minx, minx->BA >> 8 ) << 8 ); }
OP(8A) { minx->HL = ( minx->HL & 0xFF00 ) | DEC8( minx, minx->HL & 0x00FF ); }
OP(8B) { minx->HL = ( minx->HL & 0x00FF ) | ( DEC8( minx, minx->HL >> 8 ) << 8 ); }
OP(8C) { minx->N = DEC8( minx, minx->N ); }
OP(8D) { AD1_IN8; WR( addr1, DEC8( minx, RD( addr1 ) ) ); }
OP(8E) { AD1_IHL; WR( addr1, DEC8( minx, RD( addr1 ) ) ); }
OP(8F) { minx->SP = DEC8( minx, minx->SP ); }
OP(80) { m_BA = ( m_BA & 0xFF00 ) | INC8( m_BA & 0x00FF ); }
OP(81) { m_BA = ( m_BA & 0x00FF ) | ( INC8( m_BA >> 8 ) << 8 ); }
OP(82) { m_HL = ( m_HL & 0xFF00 ) | INC8( m_HL & 0x00FF ); }
OP(83) { m_HL = ( m_HL & 0x00FF ) | ( INC8( m_HL >> 8 ) << 8 ); }
OP(84) { m_N = INC8( m_N ); }
OP(85) { AD1_IN8; WR( addr1, INC8( RD( addr1 ) ) ); }
OP(86) { AD1_IHL; WR( addr1, INC8( RD( addr1 ) ) ); }
OP(87) { m_SP = INC16( m_SP ); }
OP(88) { m_BA = ( m_BA & 0xFF00 ) | DEC8( m_BA & 0x00FF ); }
OP(89) { m_BA = ( m_BA & 0x00FF ) | ( DEC8( m_BA >> 8 ) << 8 ); }
OP(8A) { m_HL = ( m_HL & 0xFF00 ) | DEC8( m_HL & 0x00FF ); }
OP(8B) { m_HL = ( m_HL & 0x00FF ) | ( DEC8( m_HL >> 8 ) << 8 ); }
OP(8C) { m_N = DEC8( m_N ); }
OP(8D) { AD1_IN8; WR( addr1, DEC8( RD( addr1 ) ) ); }
OP(8E) { AD1_IHL; WR( addr1, DEC8( RD( addr1 ) ) ); }
OP(8F) { m_SP = DEC8( m_SP ); }
OP(90) { minx->BA = INC16( minx, minx->BA ); }
OP(91) { minx->HL = INC16( minx, minx->HL ); }
OP(92) { minx->X = INC16( minx, minx->X ); }
OP(93) { minx->Y = INC16( minx, minx->Y ); }
OP(94) { minx->F = ( AND8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z;}
OP(95) { AD1_IHL; minx->F = ( AND8( minx, RD( addr1 ), rdop(minx) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z; }
OP(96) { minx->F = ( AND8( minx, ( minx->BA & 0x00FF ), rdop(minx) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z; }
OP(97) { minx->F = ( AND8( minx, ( minx->BA >> 8 ), rdop(minx) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z; }
OP(98) { minx->BA = DEC16( minx, minx->BA ); }
OP(99) { minx->HL = DEC16( minx, minx->HL ); }
OP(9A) { minx->X = DEC16( minx, minx->X ); }
OP(9B) { minx->Y = DEC16( minx, minx->Y ); }
OP(9C) { minx->F = minx->F & rdop(minx); }
OP(9D) { minx->F = minx->F | rdop(minx); }
OP(9E) { minx->F = minx->F ^ rdop(minx); }
OP(9F) { minx->F = rdop(minx); }
OP(90) { m_BA = INC16( m_BA ); }
OP(91) { m_HL = INC16( m_HL ); }
OP(92) { m_X = INC16( m_X ); }
OP(93) { m_Y = INC16( m_Y ); }
OP(94) { m_F = ( AND8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z;}
OP(95) { AD1_IHL; m_F = ( AND8( RD( addr1 ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
OP(96) { m_F = ( AND8( ( m_BA & 0x00FF ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
OP(97) { m_F = ( AND8( ( m_BA >> 8 ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
OP(98) { m_BA = DEC16( m_BA ); }
OP(99) { m_HL = DEC16( m_HL ); }
OP(9A) { m_X = DEC16( m_X ); }
OP(9B) { m_Y = DEC16( m_Y ); }
OP(9C) { m_F = m_F & rdop(); }
OP(9D) { m_F = m_F | rdop(); }
OP(9E) { m_F = m_F ^ rdop(); }
OP(9F) { m_F = rdop(); }
OP(A0) { PUSH16( minx, minx->BA ); }
OP(A1) { PUSH16( minx, minx->HL ); }
OP(A2) { PUSH16( minx, minx->X ); }
OP(A3) { PUSH16( minx, minx->Y ); }
OP(A4) { PUSH8( minx, minx->N ); }
OP(A5) { PUSH8( minx, minx->I ); }
OP(A6) { PUSH8( minx, minx->XI ); PUSH8( minx, minx->YI ); }
OP(A7) { PUSH8( minx, minx->F ); }
OP(A8) { minx->BA = POP16(minx); }
OP(A9) { minx->HL = POP16(minx);}
OP(AA) { minx->X = POP16(minx); }
OP(AB) { minx->Y = POP16(minx); }
OP(AC) { minx->N = POP8(minx); }
OP(AD) { minx->I = POP8(minx); }
OP(AE) { minx->YI = POP8(minx); minx->XI = POP8(minx); }
OP(AF) { minx->F = POP8(minx); }
OP(A0) { PUSH16( m_BA ); }
OP(A1) { PUSH16( m_HL ); }
OP(A2) { PUSH16( m_X ); }
OP(A3) { PUSH16( m_Y ); }
OP(A4) { PUSH8( m_N ); }
OP(A5) { PUSH8( m_I ); }
OP(A6) { PUSH8( m_XI ); PUSH8( m_YI ); }
OP(A7) { PUSH8( m_F ); }
OP(A8) { m_BA = POP16(); }
OP(A9) { m_HL = POP16();}
OP(AA) { m_X = POP16(); }
OP(AB) { m_Y = POP16(); }
OP(AC) { m_N = POP8(); }
OP(AD) { m_I = POP8(); }
OP(AE) { m_YI = POP8(); m_XI = POP8(); }
OP(AF) { m_F = POP8(); }
OP(B0) { UINT8 op = rdop(minx); minx->BA = ( minx->BA & 0xFF00 ) | op; }
OP(B1) { UINT8 op = rdop(minx); minx->BA = ( minx->BA & 0x00FF ) | ( op << 8 ); }
OP(B2) { UINT8 op = rdop(minx); minx->HL = ( minx->HL & 0xFF00 ) | op; }
OP(B3) { UINT8 op = rdop(minx); minx->HL = ( minx->HL & 0x00FF ) | ( op << 8 ); }
OP(B4) { UINT8 op = rdop(minx); minx->N = op; }
OP(B5) { AD1_IHL; UINT8 op = rdop(minx); WR( addr1, op); }
OP(B6) { AD1_XIX; UINT8 op = rdop(minx); WR( addr1, op ); }
OP(B7) { AD1_YIY; UINT8 op = rdop(minx); WR( addr1, op ); }
OP(B8) { AD2_I16; minx->BA = rd16( minx, addr2 ); }
OP(B9) { AD2_I16; minx->HL = rd16( minx, addr2 ); }
OP(BA) { AD2_I16; minx->X = rd16( minx, addr2 ); }
OP(BB) { AD2_I16; minx->Y = rd16( minx, addr2 ); }
OP(BC) { AD1_I16; wr16( minx, addr1, minx->BA ); }
OP(BD) { AD1_I16; wr16( minx, addr1, minx->HL ); }
OP(BE) { AD1_I16; wr16( minx, addr1, minx->X ); }
OP(BF) { AD1_I16; wr16( minx, addr1, minx->Y ); }
OP(B0) { UINT8 op = rdop(); m_BA = ( m_BA & 0xFF00 ) | op; }
OP(B1) { UINT8 op = rdop(); m_BA = ( m_BA & 0x00FF ) | ( op << 8 ); }
OP(B2) { UINT8 op = rdop(); m_HL = ( m_HL & 0xFF00 ) | op; }
OP(B3) { UINT8 op = rdop(); m_HL = ( m_HL & 0x00FF ) | ( op << 8 ); }
OP(B4) { UINT8 op = rdop(); m_N = op; }
OP(B5) { AD1_IHL; UINT8 op = rdop(); WR( addr1, op); }
OP(B6) { AD1_XIX; UINT8 op = rdop(); WR( addr1, op ); }
OP(B7) { AD1_YIY; UINT8 op = rdop(); WR( addr1, op ); }
OP(B8) { AD2_I16; m_BA = rd16( addr2 ); }
OP(B9) { AD2_I16; m_HL = rd16( addr2 ); }
OP(BA) { AD2_I16; m_X = rd16( addr2 ); }
OP(BB) { AD2_I16; m_Y = rd16( addr2 ); }
OP(BC) { AD1_I16; wr16( addr1, m_BA ); }
OP(BD) { AD1_I16; wr16( addr1, m_HL ); }
OP(BE) { AD1_I16; wr16( addr1, m_X ); }
OP(BF) { AD1_I16; wr16( addr1, m_Y ); }
OP(C0) { minx->BA = ADD16( minx, minx->BA, rdop16(minx) ); }
OP(C1) { minx->HL = ADD16( minx, minx->HL, rdop16(minx) ); }
OP(C2) { minx->X = ADD16( minx, minx->X, rdop16(minx) ); }
OP(C3) { minx->Y = ADD16( minx, minx->Y, rdop16(minx) ); }
OP(C4) { minx->BA = rdop16(minx); }
OP(C5) { minx->HL = rdop16(minx); }
OP(C6) { minx->X = rdop16(minx); }
OP(C7) { minx->Y = rdop16(minx); }
OP(C8) { UINT16 t = minx->BA; minx->BA = minx->HL; minx->HL = t; }
OP(C9) { UINT16 t = minx->BA; minx->BA = minx->X; minx->X = t; }
OP(CA) { UINT16 t = minx->BA; minx->BA = minx->Y; minx->Y = t; }
OP(CB) { UINT16 t = minx->BA; minx->BA = minx->SP; minx->SP = t; }
OP(CC) { minx->BA = ( minx->BA >> 8 ) | ( ( minx->BA & 0x00FF ) << 8 ); }
OP(CD) { UINT8 t; AD2_IHL; t = RD( addr2 ); WR( addr2, ( minx->BA & 0x00FF ) ); minx->BA = ( minx->BA & 0xFF00 ) | t; }
OP(CE) { UINT8 op = rdop(minx); insnminx_CE[op](minx); minx->icount -= insnminx_cycles_CE[op]; }
OP(CF) { UINT8 op = rdop(minx); insnminx_CF[op](minx); minx->icount -= insnminx_cycles_CF[op]; }
OP(C0) { m_BA = ADD16( m_BA, rdop16() ); }
OP(C1) { m_HL = ADD16( m_HL, rdop16() ); }
OP(C2) { m_X = ADD16( m_X, rdop16() ); }
OP(C3) { m_Y = ADD16( m_Y, rdop16() ); }
OP(C4) { m_BA = rdop16(); }
OP(C5) { m_HL = rdop16(); }
OP(C6) { m_X = rdop16(); }
OP(C7) { m_Y = rdop16(); }
OP(C8) { UINT16 t = m_BA; m_BA = m_HL; m_HL = t; }
OP(C9) { UINT16 t = m_BA; m_BA = m_X; m_X = t; }
OP(CA) { UINT16 t = m_BA; m_BA = m_Y; m_Y = t; }
OP(CB) { UINT16 t = m_BA; m_BA = m_SP; m_SP = t; }
OP(CC) { m_BA = ( m_BA >> 8 ) | ( ( m_BA & 0x00FF ) << 8 ); }
OP(CD) { UINT8 t; AD2_IHL; t = RD( addr2 ); WR( addr2, ( m_BA & 0x00FF ) ); m_BA = ( m_BA & 0xFF00 ) | t; }
OP(CE) { UINT8 op = rdop(); (this->*insnminx_CE[op])(); m_icount -= insnminx_cycles_CE[op]; }
OP(CF) { UINT8 op = rdop(); (this->*insnminx_CF[op])(); m_icount -= insnminx_cycles_CF[op]; }
OP(D0) { minx->BA = SUB16( minx, minx->BA, rdop16(minx) ); }
OP(D1) { minx->HL = SUB16( minx, minx->HL, rdop16(minx) ); }
OP(D2) { minx->X = SUB16( minx, minx->X, rdop16(minx) ); }
OP(D3) { minx->Y = SUB16( minx, minx->Y, rdop16(minx) ); }
OP(D4) { SUB16( minx, minx->BA, rdop16(minx) ); }
OP(D5) { SUB16( minx, minx->HL, rdop16(minx) ); }
OP(D6) { SUB16( minx, minx->X, rdop16(minx) ); }
OP(D7) { SUB16( minx, minx->Y, rdop16(minx) ); }
OP(D8) { AD1_IN8; WR( addr1, AND8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(D9) { AD1_IN8; WR( addr1, OR8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(DA) { AD1_IN8; WR( addr1, XOR8( minx, RD( addr1 ), rdop(minx) ) ); }
OP(DB) { AD1_IN8; SUB8( minx, RD( addr1 ), rdop(minx) ); }
OP(DC) { AD1_IN8; minx->F = ( AND8( minx, RD( addr1 ), rdop(minx) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z; }
OP(DD) { AD1_IN8; WR( addr1, rdop(minx) ); }
OP(DE) { minx->BA = ( minx->BA & 0xFF00 ) | ( ( minx->BA & 0x000F ) | ( ( minx->BA & 0x0F00 ) >> 4 ) ); }
OP(DF) { minx->BA = ( ( minx->BA & 0x0080 ) ? 0xFF00 : 0x0000 ) | ( minx->BA & 0x000F ); }
OP(D0) { m_BA = SUB16( m_BA, rdop16() ); }
OP(D1) { m_HL = SUB16( m_HL, rdop16() ); }
OP(D2) { m_X = SUB16( m_X, rdop16() ); }
OP(D3) { m_Y = SUB16( m_Y, rdop16() ); }
OP(D4) { SUB16( m_BA, rdop16() ); }
OP(D5) { SUB16( m_HL, rdop16() ); }
OP(D6) { SUB16( m_X, rdop16() ); }
OP(D7) { SUB16( m_Y, rdop16() ); }
OP(D8) { AD1_IN8; WR( addr1, AND8( RD( addr1 ), rdop() ) ); }
OP(D9) { AD1_IN8; WR( addr1, OR8( RD( addr1 ), rdop() ) ); }
OP(DA) { AD1_IN8; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); }
OP(DB) { AD1_IN8; SUB8( RD( addr1 ), rdop() ); }
OP(DC) { AD1_IN8; m_F = ( AND8( RD( addr1 ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
OP(DD) { AD1_IN8; WR( addr1, rdop() ); }
OP(DE) { m_BA = ( m_BA & 0xFF00 ) | ( ( m_BA & 0x000F ) | ( ( m_BA & 0x0F00 ) >> 4 ) ); }
OP(DF) { m_BA = ( ( m_BA & 0x0080 ) ? 0xFF00 : 0x0000 ) | ( m_BA & 0x000F ); }
OP(E0) { INT8 d8 = rdop(minx); if ( minx->F & FLAG_C ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(E1) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_C ) ) { CALL( minx, minx->PC + d8- 1 ); minx->icount -= 12; } }
OP(E2) { INT8 d8 = rdop(minx); if ( minx->F & FLAG_Z ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(E3) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_Z ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } }
OP(E4) { INT8 d8 = rdop(minx); if ( minx->F & FLAG_C ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E5) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_C ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E6) { INT8 d8 = rdop(minx); if ( minx->F & FLAG_Z ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E7) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_Z ) ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(E8) { UINT16 d16 = rdop16(minx); if ( minx->F & FLAG_C ) { CALL( minx, minx->PC + d16 - 1 ); minx->icount -= 12; } }
OP(E9) { UINT16 d16 = rdop16(minx); if ( ! ( minx->F & FLAG_C ) ) { CALL( minx, minx->PC + d16 - 1 ); minx->icount -= 12; } }
OP(EA) { UINT16 d16 = rdop16(minx); if ( minx->F & FLAG_Z ) { CALL( minx, minx->PC + d16 - 1 ); minx->icount -= 12; } }
OP(EB) { UINT16 d16 = rdop16(minx); if ( ! ( minx->F & FLAG_Z ) ) { CALL( minx, minx->PC + d16 - 1 ); minx->icount -= 12; } }
OP(EC) { UINT16 d16 = rdop16(minx); if ( minx->F & FLAG_C ) { JMP( minx, minx->PC + d16 - 1 ); } }
OP(ED) { UINT16 d16 = rdop16(minx); if ( ! ( minx->F & FLAG_C ) ) { JMP( minx, minx->PC + d16 - 1 ); } }
OP(EE) { UINT16 d16 = rdop16(minx); if ( minx->F & FLAG_Z ) { JMP( minx, minx->PC + d16 - 1 ); } }
OP(EF) { UINT16 d16 = rdop16(minx); if ( ! ( minx->F & FLAG_Z ) ) { JMP( minx, minx->PC + d16 - 1 ); } }
OP(E0) { INT8 d8 = rdop(); if ( m_F & FLAG_C ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(E1) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_C ) ) { CALL( m_PC + d8- 1 ); m_icount -= 12; } }
OP(E2) { INT8 d8 = rdop(); if ( m_F & FLAG_Z ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(E3) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_Z ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
OP(E4) { INT8 d8 = rdop(); if ( m_F & FLAG_C ) { JMP( m_PC + d8 - 1 ); } }
OP(E5) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_C ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E6) { INT8 d8 = rdop(); if ( m_F & FLAG_Z ) { JMP( m_PC + d8 - 1 ); } }
OP(E7) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_Z ) ) { JMP( m_PC + d8 - 1 ); } }
OP(E8) { UINT16 d16 = rdop16(); if ( m_F & FLAG_C ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
OP(E9) { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_C ) ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
OP(EA) { UINT16 d16 = rdop16(); if ( m_F & FLAG_Z ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
OP(EB) { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_Z ) ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
OP(EC) { UINT16 d16 = rdop16(); if ( m_F & FLAG_C ) { JMP( m_PC + d16 - 1 ); } }
OP(ED) { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_C ) ) { JMP( m_PC + d16 - 1 ); } }
OP(EE) { UINT16 d16 = rdop16(); if ( m_F & FLAG_Z ) { JMP( m_PC + d16 - 1 ); } }
OP(EF) { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_Z ) ) { JMP( m_PC + d16 - 1 ); } }
OP(F0) { INT8 d8 = rdop(minx); CALL( minx, minx->PC + d8 - 1 ); }
OP(F1) { INT8 d8 = rdop(minx); JMP( minx, minx->PC + d8 - 1 ); }
OP(F2) { UINT16 d16 = rdop16(minx); CALL( minx, minx->PC + d16 - 1 ); }
OP(F3) { UINT16 d16 = rdop16(minx); JMP( minx, minx->PC + d16 - 1 ); }
OP(F4) { JMP( minx, minx->HL ); }
OP(F5) { INT8 d8 = rdop(minx); minx->BA = minx->BA - 0x0100; if ( minx->BA & 0xFF00 ) { JMP( minx, minx->PC + d8 - 1 ); } }
OP(F6) { minx->BA = ( minx->BA & 0xFF00 ) | ( ( minx->BA & 0x00F0 ) >> 4 ) | ( ( minx->BA & 0x000F ) << 4 ); }
OP(F0) { INT8 d8 = rdop(); CALL( m_PC + d8 - 1 ); }
OP(F1) { INT8 d8 = rdop(); JMP( m_PC + d8 - 1 ); }
OP(F2) { UINT16 d16 = rdop16(); CALL( m_PC + d16 - 1 ); }
OP(F3) { UINT16 d16 = rdop16(); JMP( m_PC + d16 - 1 ); }
OP(F4) { JMP( m_HL ); }
OP(F5) { INT8 d8 = rdop(); m_BA = m_BA - 0x0100; if ( m_BA & 0xFF00 ) { JMP( m_PC + d8 - 1 ); } }
OP(F6) { m_BA = ( m_BA & 0xFF00 ) | ( ( m_BA & 0x00F0 ) >> 4 ) | ( ( m_BA & 0x000F ) << 4 ); }
OP(F7) { UINT8 d; AD1_IHL; d = RD( addr1 ); WR( addr1, ( ( d & 0xF0 ) >> 4 ) | ( ( d & 0x0F ) << 4 ) ); }
OP(F8) { minx->PC = POP16(minx); minx->V = POP8(minx); minx->U = minx->V; }
OP(F9) { minx->F = POP8(minx); minx->PC = POP16(minx); minx->V = POP8(minx); minx->U = minx->V; }
OP(FA) { minx->PC = POP16(minx) + 2; minx->V = POP8(minx); minx->U = minx->V; }
OP(FB) { AD1_I16; CALL( minx, rd16( minx, addr1 ) ); }
OP(FC) { UINT8 i = rdop(minx) & 0xFE; CALL( minx, rd16( minx, i ) ); PUSH8( minx, minx->F ); }
OP(FD) { UINT8 i = rdop(minx) & 0xFE; JMP( minx, rd16( minx, i ) ); /* PUSH8( minx, minx->F );?? */ }
OP(F8) { m_PC = POP16(); m_V = POP8(); m_U = m_V; }
OP(F9) { m_F = POP8(); m_PC = POP16(); m_V = POP8(); m_U = m_V; }
OP(FA) { m_PC = POP16() + 2; m_V = POP8(); m_U = m_V; }
OP(FB) { AD1_I16; CALL( rd16( addr1 ) ); }
OP(FC) { UINT8 i = rdop() & 0xFE; CALL( rd16( i ) ); PUSH8( m_F ); }
OP(FD) { UINT8 i = rdop() & 0xFE; JMP( rd16( i ) ); /* PUSH8( m_F );?? */ }
OP(FE) { /* illegal operation? */ }
OP(FF) { }
static void (*const insnminx[256])(minx_state *minx) = {
minx_00, minx_01, minx_02, minx_03, minx_04, minx_05, minx_06, minx_07,
minx_08, minx_09, minx_0A, minx_0B, minx_0C, minx_0D, minx_0E, minx_0F,
minx_10, minx_11, minx_12, minx_13, minx_14, minx_15, minx_16, minx_17,
minx_18, minx_19, minx_1A, minx_1B, minx_1C, minx_1D, minx_1E, minx_1F,
minx_20, minx_21, minx_22, minx_23, minx_24, minx_25, minx_26, minx_27,
minx_28, minx_29, minx_2A, minx_2B, minx_2C, minx_2D, minx_2E, minx_2F,
minx_30, minx_31, minx_32, minx_33, minx_34, minx_35, minx_36, minx_37,
minx_38, minx_39, minx_3A, minx_3B, minx_3C, minx_3D, minx_3E, minx_3F,
minx_40, minx_41, minx_42, minx_43, minx_44, minx_45, minx_46, minx_47,
minx_48, minx_49, minx_4A, minx_4B, minx_4C, minx_4D, minx_4E, minx_4F,
minx_50, minx_51, minx_52, minx_53, minx_54, minx_55, minx_56, minx_57,
minx_58, minx_59, minx_5A, minx_5B, minx_5C, minx_5D, minx_5E, minx_5F,
minx_60, minx_61, minx_62, minx_63, minx_64, minx_65, minx_66, minx_67,
minx_68, minx_69, minx_6A, minx_6B, minx_6C, minx_6D, minx_6E, minx_6F,
minx_70, minx_71, minx_72, minx_73, minx_74, minx_75, minx_76, minx_77,
minx_78, minx_79, minx_7A, minx_7B, minx_7C, minx_7D, minx_7E, minx_7F,
minx_80, minx_81, minx_82, minx_83, minx_84, minx_85, minx_86, minx_87,
minx_88, minx_89, minx_8A, minx_8B, minx_8C, minx_8D, minx_8E, minx_8F,
minx_90, minx_91, minx_92, minx_93, minx_94, minx_95, minx_96, minx_97,
minx_98, minx_99, minx_9A, minx_9B, minx_9C, minx_9D, minx_9E, minx_9F,
minx_A0, minx_A1, minx_A2, minx_A3, minx_A4, minx_A5, minx_A6, minx_A7,
minx_A8, minx_A9, minx_AA, minx_AB, minx_AC, minx_AD, minx_AE, minx_AF,
minx_B0, minx_B1, minx_B2, minx_B3, minx_B4, minx_B5, minx_B6, minx_B7,
minx_B8, minx_B9, minx_BA, minx_BB, minx_BC, minx_BD, minx_BE, minx_BF,
minx_C0, minx_C1, minx_C2, minx_C3, minx_C4, minx_C5, minx_C6, minx_C7,
minx_C8, minx_C9, minx_CA, minx_CB, minx_CC, minx_CD, minx_CE, minx_CF,
minx_D0, minx_D1, minx_D2, minx_D3, minx_D4, minx_D5, minx_D6, minx_D7,
minx_D8, minx_D9, minx_DA, minx_DB, minx_DC, minx_DD, minx_DE, minx_DF,
minx_E0, minx_E1, minx_E2, minx_E3, minx_E4, minx_E5, minx_E6, minx_E7,
minx_E8, minx_E9, minx_EA, minx_EB, minx_EC, minx_ED, minx_EE, minx_EF,
minx_F0, minx_F1, minx_F2, minx_F3, minx_F4, minx_F5, minx_F6, minx_F7,
minx_F8, minx_F9, minx_FA, minx_FB, minx_FC, minx_FD, minx_FE, minx_FF
const minx_cpu_device::op_func minx_cpu_device::insnminx[256] = {
&minx_cpu_device::minx_00, &minx_cpu_device::minx_01, &minx_cpu_device::minx_02, &minx_cpu_device::minx_03, &minx_cpu_device::minx_04, &minx_cpu_device::minx_05, &minx_cpu_device::minx_06, &minx_cpu_device::minx_07,
&minx_cpu_device::minx_08, &minx_cpu_device::minx_09, &minx_cpu_device::minx_0A, &minx_cpu_device::minx_0B, &minx_cpu_device::minx_0C, &minx_cpu_device::minx_0D, &minx_cpu_device::minx_0E, &minx_cpu_device::minx_0F,
&minx_cpu_device::minx_10, &minx_cpu_device::minx_11, &minx_cpu_device::minx_12, &minx_cpu_device::minx_13, &minx_cpu_device::minx_14, &minx_cpu_device::minx_15, &minx_cpu_device::minx_16, &minx_cpu_device::minx_17,
&minx_cpu_device::minx_18, &minx_cpu_device::minx_19, &minx_cpu_device::minx_1A, &minx_cpu_device::minx_1B, &minx_cpu_device::minx_1C, &minx_cpu_device::minx_1D, &minx_cpu_device::minx_1E, &minx_cpu_device::minx_1F,
&minx_cpu_device::minx_20, &minx_cpu_device::minx_21, &minx_cpu_device::minx_22, &minx_cpu_device::minx_23, &minx_cpu_device::minx_24, &minx_cpu_device::minx_25, &minx_cpu_device::minx_26, &minx_cpu_device::minx_27,
&minx_cpu_device::minx_28, &minx_cpu_device::minx_29, &minx_cpu_device::minx_2A, &minx_cpu_device::minx_2B, &minx_cpu_device::minx_2C, &minx_cpu_device::minx_2D, &minx_cpu_device::minx_2E, &minx_cpu_device::minx_2F,
&minx_cpu_device::minx_30, &minx_cpu_device::minx_31, &minx_cpu_device::minx_32, &minx_cpu_device::minx_33, &minx_cpu_device::minx_34, &minx_cpu_device::minx_35, &minx_cpu_device::minx_36, &minx_cpu_device::minx_37,
&minx_cpu_device::minx_38, &minx_cpu_device::minx_39, &minx_cpu_device::minx_3A, &minx_cpu_device::minx_3B, &minx_cpu_device::minx_3C, &minx_cpu_device::minx_3D, &minx_cpu_device::minx_3E, &minx_cpu_device::minx_3F,
&minx_cpu_device::minx_40, &minx_cpu_device::minx_41, &minx_cpu_device::minx_42, &minx_cpu_device::minx_43, &minx_cpu_device::minx_44, &minx_cpu_device::minx_45, &minx_cpu_device::minx_46, &minx_cpu_device::minx_47,
&minx_cpu_device::minx_48, &minx_cpu_device::minx_49, &minx_cpu_device::minx_4A, &minx_cpu_device::minx_4B, &minx_cpu_device::minx_4C, &minx_cpu_device::minx_4D, &minx_cpu_device::minx_4E, &minx_cpu_device::minx_4F,
&minx_cpu_device::minx_50, &minx_cpu_device::minx_51, &minx_cpu_device::minx_52, &minx_cpu_device::minx_53, &minx_cpu_device::minx_54, &minx_cpu_device::minx_55, &minx_cpu_device::minx_56, &minx_cpu_device::minx_57,
&minx_cpu_device::minx_58, &minx_cpu_device::minx_59, &minx_cpu_device::minx_5A, &minx_cpu_device::minx_5B, &minx_cpu_device::minx_5C, &minx_cpu_device::minx_5D, &minx_cpu_device::minx_5E, &minx_cpu_device::minx_5F,
&minx_cpu_device::minx_60, &minx_cpu_device::minx_61, &minx_cpu_device::minx_62, &minx_cpu_device::minx_63, &minx_cpu_device::minx_64, &minx_cpu_device::minx_65, &minx_cpu_device::minx_66, &minx_cpu_device::minx_67,
&minx_cpu_device::minx_68, &minx_cpu_device::minx_69, &minx_cpu_device::minx_6A, &minx_cpu_device::minx_6B, &minx_cpu_device::minx_6C, &minx_cpu_device::minx_6D, &minx_cpu_device::minx_6E, &minx_cpu_device::minx_6F,
&minx_cpu_device::minx_70, &minx_cpu_device::minx_71, &minx_cpu_device::minx_72, &minx_cpu_device::minx_73, &minx_cpu_device::minx_74, &minx_cpu_device::minx_75, &minx_cpu_device::minx_76, &minx_cpu_device::minx_77,
&minx_cpu_device::minx_78, &minx_cpu_device::minx_79, &minx_cpu_device::minx_7A, &minx_cpu_device::minx_7B, &minx_cpu_device::minx_7C, &minx_cpu_device::minx_7D, &minx_cpu_device::minx_7E, &minx_cpu_device::minx_7F,
&minx_cpu_device::minx_80, &minx_cpu_device::minx_81, &minx_cpu_device::minx_82, &minx_cpu_device::minx_83, &minx_cpu_device::minx_84, &minx_cpu_device::minx_85, &minx_cpu_device::minx_86, &minx_cpu_device::minx_87,
&minx_cpu_device::minx_88, &minx_cpu_device::minx_89, &minx_cpu_device::minx_8A, &minx_cpu_device::minx_8B, &minx_cpu_device::minx_8C, &minx_cpu_device::minx_8D, &minx_cpu_device::minx_8E, &minx_cpu_device::minx_8F,
&minx_cpu_device::minx_90, &minx_cpu_device::minx_91, &minx_cpu_device::minx_92, &minx_cpu_device::minx_93, &minx_cpu_device::minx_94, &minx_cpu_device::minx_95, &minx_cpu_device::minx_96, &minx_cpu_device::minx_97,
&minx_cpu_device::minx_98, &minx_cpu_device::minx_99, &minx_cpu_device::minx_9A, &minx_cpu_device::minx_9B, &minx_cpu_device::minx_9C, &minx_cpu_device::minx_9D, &minx_cpu_device::minx_9E, &minx_cpu_device::minx_9F,
&minx_cpu_device::minx_A0, &minx_cpu_device::minx_A1, &minx_cpu_device::minx_A2, &minx_cpu_device::minx_A3, &minx_cpu_device::minx_A4, &minx_cpu_device::minx_A5, &minx_cpu_device::minx_A6, &minx_cpu_device::minx_A7,
&minx_cpu_device::minx_A8, &minx_cpu_device::minx_A9, &minx_cpu_device::minx_AA, &minx_cpu_device::minx_AB, &minx_cpu_device::minx_AC, &minx_cpu_device::minx_AD, &minx_cpu_device::minx_AE, &minx_cpu_device::minx_AF,
&minx_cpu_device::minx_B0, &minx_cpu_device::minx_B1, &minx_cpu_device::minx_B2, &minx_cpu_device::minx_B3, &minx_cpu_device::minx_B4, &minx_cpu_device::minx_B5, &minx_cpu_device::minx_B6, &minx_cpu_device::minx_B7,
&minx_cpu_device::minx_B8, &minx_cpu_device::minx_B9, &minx_cpu_device::minx_BA, &minx_cpu_device::minx_BB, &minx_cpu_device::minx_BC, &minx_cpu_device::minx_BD, &minx_cpu_device::minx_BE, &minx_cpu_device::minx_BF,
&minx_cpu_device::minx_C0, &minx_cpu_device::minx_C1, &minx_cpu_device::minx_C2, &minx_cpu_device::minx_C3, &minx_cpu_device::minx_C4, &minx_cpu_device::minx_C5, &minx_cpu_device::minx_C6, &minx_cpu_device::minx_C7,
&minx_cpu_device::minx_C8, &minx_cpu_device::minx_C9, &minx_cpu_device::minx_CA, &minx_cpu_device::minx_CB, &minx_cpu_device::minx_CC, &minx_cpu_device::minx_CD, &minx_cpu_device::minx_CE, &minx_cpu_device::minx_CF,
&minx_cpu_device::minx_D0, &minx_cpu_device::minx_D1, &minx_cpu_device::minx_D2, &minx_cpu_device::minx_D3, &minx_cpu_device::minx_D4, &minx_cpu_device::minx_D5, &minx_cpu_device::minx_D6, &minx_cpu_device::minx_D7,
&minx_cpu_device::minx_D8, &minx_cpu_device::minx_D9, &minx_cpu_device::minx_DA, &minx_cpu_device::minx_DB, &minx_cpu_device::minx_DC, &minx_cpu_device::minx_DD, &minx_cpu_device::minx_DE, &minx_cpu_device::minx_DF,
&minx_cpu_device::minx_E0, &minx_cpu_device::minx_E1, &minx_cpu_device::minx_E2, &minx_cpu_device::minx_E3, &minx_cpu_device::minx_E4, &minx_cpu_device::minx_E5, &minx_cpu_device::minx_E6, &minx_cpu_device::minx_E7,
&minx_cpu_device::minx_E8, &minx_cpu_device::minx_E9, &minx_cpu_device::minx_EA, &minx_cpu_device::minx_EB, &minx_cpu_device::minx_EC, &minx_cpu_device::minx_ED, &minx_cpu_device::minx_EE, &minx_cpu_device::minx_EF,
&minx_cpu_device::minx_F0, &minx_cpu_device::minx_F1, &minx_cpu_device::minx_F2, &minx_cpu_device::minx_F3, &minx_cpu_device::minx_F4, &minx_cpu_device::minx_F5, &minx_cpu_device::minx_F6, &minx_cpu_device::minx_F7,
&minx_cpu_device::minx_F8, &minx_cpu_device::minx_F9, &minx_cpu_device::minx_FA, &minx_cpu_device::minx_FB, &minx_cpu_device::minx_FC, &minx_cpu_device::minx_FD, &minx_cpu_device::minx_FE, &minx_cpu_device::minx_FF
};
static const int insnminx_cycles[256] = {
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
const int minx_cpu_device::insnminx_cycles[256] = {
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
4, 4, 4, 4, 12, 8, 8, 8, 4, 4, 4, 4, 12, 8, 8, 8,
4, 4, 4, 4, 12, 8, 8, 8, 4, 4, 4, 4, 12, 8, 8, 8,
8, 8, 8, 8, 16, 12, 12, 12, 8, 8, 8, 8, 16, 12, 12, 12,
8, 8, 8, 8, 16, 12, 12, 12, 12, 12, 12, 12, 1, 16, 16, 16,
4, 4, 4, 4, 12, 8, 8, 8, 4, 4, 4, 4, 12, 8, 8, 8,
4, 4, 4, 4, 12, 8, 8, 8, 4, 4, 4, 4, 12, 8, 8, 8,
8, 8, 8, 8, 16, 12, 12, 12, 8, 8, 8, 8, 16, 12, 12, 12,
8, 8, 8, 8, 16, 12, 12, 12, 12, 12, 12, 12, 1, 16, 16, 16,
8, 8, 8, 8, 8, 16, 12, 8, 8, 8, 8, 8, 8, 16, 12, 8,
8, 8, 8, 8, 8, 12, 8, 8, 8, 8, 8, 8, 12, 12, 12, 12,
8, 8, 8, 8, 8, 16, 12, 8, 8, 8, 8, 8, 8, 16, 12, 8,
8, 8, 8, 8, 8, 12, 8, 8, 8, 8, 8, 8, 12, 12, 12, 12,
16, 16, 16, 16, 12, 12, 16, 12, 12, 12, 12, 12, 8, 8, 12, 8,
8, 8, 8, 8, 8, 12, 12, 12, 20, 20, 20, 20, 1, 1, 1, 1,
8, 8, 8, 8, 8, 12, 12, 12, 20, 20, 20, 20, 1, 1, 1, 1,
12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 8, 12, 0, 0,
12, 12, 12, 12, 12, 12, 12, 12, 20, 20, 20, 16, 16, 16, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 12, 12, 12, 12, 12, 12, 12, 12,
8, 8, 8, 8, 8, 8, 8, 8, 12, 12, 12, 12, 12, 12, 12, 12,
20, 8, 24, 12, 8, 1, 8, 12, 8, 8, 8, 20, 20, 1, 1, 8
};