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romp: various improvements (nw)

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* corrected scr register names
* some basic instruction cycle counts
* some exceptions/interrupts
* most flags
This commit is contained in:
Patrick Mackinlay 2020-02-25 20:38:00 +07:00
parent 6038ff41f7
commit 364c17fa3d
3 changed files with 582 additions and 231 deletions
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700
src/devices/cpu/romp/romp.cpp
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File diff suppressed because it is too large Load Diff

109
src/devices/cpu/romp/romp.h
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@ -11,6 +11,8 @@ class romp_device : public cpu_device
public:
romp_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
auto out_tm() { return m_out_tm.bind(); }
protected:
enum registers : unsigned
{
@ -20,28 +22,74 @@ protected:
enum scr : unsigned
{
COS = 6, // counter source
COU = 7, // counter
TS = 8, // timer status
MQ = 10, // multiplier quotient
MCS = 11, // machine check status
PCS = 11, // program check status
IRB = 12, // interrupt request buffer
IAR = 13, // instruction address register
ICS = 14, // interrupt control status
CS = 15, // condition status
COUS = 6, // counter source
COU = 7, // counter
TS = 8, // timer status
MQ = 10, // multiplier quotient
MPCS = 11, // machine/program check status
IRB = 12, // interrupt request buffer
IAR = 13, // instruction address register
ICS = 14, // interrupt control status
CS = 15, // condition status
};
enum cs : unsigned
enum mpcs_mask : u32
{
TB = 0, // test bit
OV = 1, // overflow
// reserved
C0 = 3, // carry zero
GT = 4, // greater than
EQ = 5, // equal
LT = 6, // less than
PZ = 7, // permanent zero
// reserved
PCS_DAE = 0x0000'0002, // data address exception
PCS_IAE = 0x0000'0004, // instruction address exception
PCS_IOC = 0x0000'0008, // illegal operation code
PCS_PIE = 0x0000'0010, // privileged instruction exception
PCS_PT = 0x0000'0020, // program trap
PCS_PCU = 0x0000'0040, // program check with unknown origin
PCS_PCK = 0x0000'0080, // program check with known origin
// reserved
MCS_IOT = 0x0000'0200, // i/o trap
MCS_PCT = 0x0000'0400, // processor channel timeout
MCS_DT = 0x0000'0800, // data timeout
MCS_IT = 0x0000'1000, // instruction timeout
MCS_PC = 0x0000'2000, // parity check
// reserved
MCS_PCC = 0x0000'8000, // processor channel check
MCS_ALL = 0x0000'ff00,
PCS_ALL = 0x0000'00ff,
};
enum irb_mask : u16
{
// reserved
IRB_L6 = 0x0200, // interrupt request level 6
IRB_L5 = 0x0400, // interrupt request level 5
IRB_L4 = 0x0800, // interrupt request level 4
IRB_L3 = 0x1000, // interrupt request level 3
IRB_L2 = 0x2000, // interrupt request level 2
IRB_L1 = 0x4000, // interrupt request level 1
IRB_L0 = 0x8000, // interrupt request level 0
IRB_ALL = 0xfe00,
};
enum ics_mask : u32
{
ICS_PP = 0x0000'0007, // processor priority
// reserved
ICS_RS = 0x0000'0070, // register set number
ICS_CS = 0x0000'0080, // check stop mask
ICS_IM = 0x0000'0100, // interrupt mask
ICS_TM = 0x0000'0200, // translate mode
ICS_US = 0x0000'0400, // unprivileged state
ICS_MP = 0x0000'0800, // memory protect
ICS_PE = 0x0000'1000, // parity error retry interrupt enable
};
enum cs_mask : u32
{
CS_T = 0x0000'0001, // test bit
CS_O = 0x0000'0002, // overflow
CS_C = 0x0000'0008, // carry
CS_G = 0x0000'0010, // greater than
CS_E = 0x0000'0020, // equal
CS_L = 0x0000'0040, // less than
CS_Z = 0x0000'0080, // permanent zero
};
// device_t overrides
@ -59,6 +107,9 @@ protected:
virtual space_config_vector memory_space_config() const override;
virtual bool memory_translate(int spacenum, int intention, offs_t &address) override;
// device_state_interface overrides
virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
// device_disasm_interface overrides
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
@ -69,10 +120,23 @@ private:
u32 ba(u16 hi, u16 lo) const { return ((u32(hi) << 16) | lo) & 0x00ff'fffeU; }
s32 bi(u16 hi, u16 lo) const { return s32((u32(hi) << 16 | lo) << 12) >> 11; }
void flags(u32 const op1);
void flags_add(u32 const op1, u32 const op2);
void flags_sub(u32 const op1, u32 const op2);
void set_scr(unsigned scr, u32 data);
void interrupt_check();
void machine_check(u32 mcs);
void program_check(u32 pcs);
void interrupt_enter(unsigned vector, u16 svc = 0);
// address spaces
address_space_config const m_mem_config;
address_space_config const m_io_config;
devcb_write_line m_out_tm;
// mame state
int m_icount;
@ -83,9 +147,10 @@ private:
// internal state
enum branch_state : unsigned
{
NONE = 0,
SUBJECT = 1, // branch subject instruction active
BRANCH = 2, // branch instruction active
DEFAULT = 0,
BRANCH = 1, // branch subject instruction active
DELAY = 2, // delayed branch instruction active
EXCEPTION = 3,
}
m_branch_state;
u32 m_branch_target;

4
src/devices/cpu/romp/rompdasm.cpp
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@ -196,8 +196,8 @@ offs_t romp_disassembler::disassemble(std::ostream &stream, offs_t pc, data_buff
case 0xeb: util::stream_format(stream, "lhs %s,0(%s)", gpr[R2], gpr[R3]); break; // load half short
case 0xec: util::stream_format(stream, "balr %s,%s", gpr[R2], gpr[R3]); flags |= STEP_OVER; break; // branch and link
case 0xed: util::stream_format(stream, "balrx %s,%s", gpr[R2], gpr[R3]); flags |= STEP_OVER | step_over_extra(1); break; // branch and link with execute
case 0xee: util::stream_format(stream, "b%-5s %s,%s", util::string_format("%sr", cc[N]), gpr[R3]); break; // branch on condition bit
case 0xef: util::stream_format(stream, "b%-5s %s,%s", util::string_format("%srx", cc[N]), gpr[R3]); break; // branch on condition bit with execute
case 0xee: util::stream_format(stream, "b%-5s %s", util::string_format("%sr", cc[N]), gpr[R3]); break; // branch on condition bit
case 0xef: util::stream_format(stream, "b%-5s %s", util::string_format("%srx", cc[N]), gpr[R3]); break; // branch on condition bit with execute
case 0xf0: util::stream_format(stream, "wait"); break; // wait
case 0xf1: util::stream_format(stream, "ae %s,%s", gpr[R2], gpr[R3]); break; // add extended