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https://github.com/holub/mame
synced 2025-04-19 23:12:11 +03:00
romp: various improvements (nw)
* corrected scr register names * some basic instruction cycle counts * some exceptions/interrupts * most flags
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@ -11,6 +11,8 @@ class romp_device : public cpu_device
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public:
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romp_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
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auto out_tm() { return m_out_tm.bind(); }
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protected:
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enum registers : unsigned
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{
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@ -20,28 +22,74 @@ protected:
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enum scr : unsigned
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{
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COS = 6, // counter source
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COU = 7, // counter
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TS = 8, // timer status
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MQ = 10, // multiplier quotient
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MCS = 11, // machine check status
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PCS = 11, // program check status
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IRB = 12, // interrupt request buffer
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IAR = 13, // instruction address register
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ICS = 14, // interrupt control status
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CS = 15, // condition status
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COUS = 6, // counter source
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COU = 7, // counter
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TS = 8, // timer status
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MQ = 10, // multiplier quotient
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MPCS = 11, // machine/program check status
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IRB = 12, // interrupt request buffer
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IAR = 13, // instruction address register
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ICS = 14, // interrupt control status
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CS = 15, // condition status
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};
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enum cs : unsigned
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enum mpcs_mask : u32
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{
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TB = 0, // test bit
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OV = 1, // overflow
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// reserved
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C0 = 3, // carry zero
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GT = 4, // greater than
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EQ = 5, // equal
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LT = 6, // less than
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PZ = 7, // permanent zero
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// reserved
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PCS_DAE = 0x0000'0002, // data address exception
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PCS_IAE = 0x0000'0004, // instruction address exception
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PCS_IOC = 0x0000'0008, // illegal operation code
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PCS_PIE = 0x0000'0010, // privileged instruction exception
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PCS_PT = 0x0000'0020, // program trap
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PCS_PCU = 0x0000'0040, // program check with unknown origin
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PCS_PCK = 0x0000'0080, // program check with known origin
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// reserved
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MCS_IOT = 0x0000'0200, // i/o trap
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MCS_PCT = 0x0000'0400, // processor channel timeout
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MCS_DT = 0x0000'0800, // data timeout
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MCS_IT = 0x0000'1000, // instruction timeout
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MCS_PC = 0x0000'2000, // parity check
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// reserved
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MCS_PCC = 0x0000'8000, // processor channel check
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MCS_ALL = 0x0000'ff00,
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PCS_ALL = 0x0000'00ff,
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};
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enum irb_mask : u16
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{
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// reserved
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IRB_L6 = 0x0200, // interrupt request level 6
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IRB_L5 = 0x0400, // interrupt request level 5
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IRB_L4 = 0x0800, // interrupt request level 4
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IRB_L3 = 0x1000, // interrupt request level 3
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IRB_L2 = 0x2000, // interrupt request level 2
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IRB_L1 = 0x4000, // interrupt request level 1
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IRB_L0 = 0x8000, // interrupt request level 0
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IRB_ALL = 0xfe00,
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};
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enum ics_mask : u32
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{
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ICS_PP = 0x0000'0007, // processor priority
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// reserved
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ICS_RS = 0x0000'0070, // register set number
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ICS_CS = 0x0000'0080, // check stop mask
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ICS_IM = 0x0000'0100, // interrupt mask
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ICS_TM = 0x0000'0200, // translate mode
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ICS_US = 0x0000'0400, // unprivileged state
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ICS_MP = 0x0000'0800, // memory protect
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ICS_PE = 0x0000'1000, // parity error retry interrupt enable
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};
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enum cs_mask : u32
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{
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CS_T = 0x0000'0001, // test bit
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CS_O = 0x0000'0002, // overflow
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CS_C = 0x0000'0008, // carry
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CS_G = 0x0000'0010, // greater than
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CS_E = 0x0000'0020, // equal
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CS_L = 0x0000'0040, // less than
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CS_Z = 0x0000'0080, // permanent zero
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};
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// device_t overrides
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@ -59,6 +107,9 @@ protected:
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virtual space_config_vector memory_space_config() const override;
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virtual bool memory_translate(int spacenum, int intention, offs_t &address) override;
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// device_state_interface overrides
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virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
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// device_disasm_interface overrides
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virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
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@ -69,10 +120,23 @@ private:
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u32 ba(u16 hi, u16 lo) const { return ((u32(hi) << 16) | lo) & 0x00ff'fffeU; }
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s32 bi(u16 hi, u16 lo) const { return s32((u32(hi) << 16 | lo) << 12) >> 11; }
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void flags(u32 const op1);
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void flags_add(u32 const op1, u32 const op2);
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void flags_sub(u32 const op1, u32 const op2);
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void set_scr(unsigned scr, u32 data);
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void interrupt_check();
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void machine_check(u32 mcs);
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void program_check(u32 pcs);
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void interrupt_enter(unsigned vector, u16 svc = 0);
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// address spaces
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address_space_config const m_mem_config;
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address_space_config const m_io_config;
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devcb_write_line m_out_tm;
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// mame state
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int m_icount;
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@ -83,9 +147,10 @@ private:
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// internal state
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enum branch_state : unsigned
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{
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NONE = 0,
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SUBJECT = 1, // branch subject instruction active
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BRANCH = 2, // branch instruction active
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DEFAULT = 0,
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BRANCH = 1, // branch subject instruction active
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DELAY = 2, // delayed branch instruction active
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EXCEPTION = 3,
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}
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m_branch_state;
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u32 m_branch_target;
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@ -196,8 +196,8 @@ offs_t romp_disassembler::disassemble(std::ostream &stream, offs_t pc, data_buff
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case 0xeb: util::stream_format(stream, "lhs %s,0(%s)", gpr[R2], gpr[R3]); break; // load half short
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case 0xec: util::stream_format(stream, "balr %s,%s", gpr[R2], gpr[R3]); flags |= STEP_OVER; break; // branch and link
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case 0xed: util::stream_format(stream, "balrx %s,%s", gpr[R2], gpr[R3]); flags |= STEP_OVER | step_over_extra(1); break; // branch and link with execute
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case 0xee: util::stream_format(stream, "b%-5s %s,%s", util::string_format("%sr", cc[N]), gpr[R3]); break; // branch on condition bit
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case 0xef: util::stream_format(stream, "b%-5s %s,%s", util::string_format("%srx", cc[N]), gpr[R3]); break; // branch on condition bit with execute
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case 0xee: util::stream_format(stream, "b%-5s %s", util::string_format("%sr", cc[N]), gpr[R3]); break; // branch on condition bit
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case 0xef: util::stream_format(stream, "b%-5s %s", util::string_format("%srx", cc[N]), gpr[R3]); break; // branch on condition bit with execute
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case 0xf0: util::stream_format(stream, "wait"); break; // wait
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case 0xf1: util::stream_format(stream, "ae %s,%s", gpr[R2], gpr[R3]); break; // add extended
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