From 36822d3e2c71365a2772976b456f687d88a90cfc Mon Sep 17 00:00:00 2001
From: smf- <smf-@users.noreply.github.com>
Date: Sun, 17 Mar 2013 14:35:15 +0000
Subject: [PATCH] MESS: Added some notes to clcd mmu registers, the only
 available documentation http://www.c128.com/pdf/LCD%20Specification.pdf
 doesn't match the hardware that we have the software for.

---
 src/mess/drivers/clcd.c | 80 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 75 insertions(+), 5 deletions(-)

diff --git a/src/mess/drivers/clcd.c b/src/mess/drivers/clcd.c
index 0e7af199fc1..62b4ac01011 100644
--- a/src/mess/drivers/clcd.c
+++ b/src/mess/drivers/clcd.c
@@ -59,17 +59,77 @@ public:
 		return 0;
 	}
 
-	DECLARE_WRITE8_MEMBER(rambank_w)
+	DECLARE_WRITE8_MEMBER(ramwrite_w)
 	{
-//      printf( "ram bank:%02x %02x\n", offset, data );
+		// this area might be shared between rom & ram or it might be ram only
+//		printf( "ram write:%04x %02x\n", offset, data );
+	}
+
+	// these seem to control what appears in the memory space at various addresses.
+	// whether they just affect data access or instruction fetching as well is unknown.
+
+	DECLARE_WRITE8_MEMBER(fa00_w)
+	{
+//		printf( "fa00\n" );
+	}
+
+	DECLARE_WRITE8_MEMBER(fa80_w)
+	{
+//		printf( "fa80\n" );
+	}
+
+	DECLARE_WRITE8_MEMBER(fb00_w)
+	{
+//		printf( "fb00\n" );
+	}
+
+	DECLARE_WRITE8_MEMBER(fb80_w)
+	{
+//		printf( "fb80\n" );
+	}
+
+	DECLARE_WRITE8_MEMBER(fc00_w)
+	{
+//		printf( "fc00\n" );
+	}
+
+	DECLARE_WRITE8_MEMBER(fc80_w)
+	{
+//		printf( "fc80\n" );
+	}
+
+	DECLARE_WRITE8_MEMBER(fd00_w)
+	{
+//		printf( "fd00\n" );
+	}
+
+	DECLARE_WRITE8_MEMBER(fd80_w)
+	{
+//		printf( "fd80\n" );
+	}
+
+	DECLARE_WRITE8_MEMBER(fe00_w)
+	{
+//		printf( "fe00\n" );
+	}
+
+	DECLARE_WRITE8_MEMBER(fe80_w)
+	{
+//		printf( "fe80\n" );
 	}
 
 	DECLARE_WRITE8_MEMBER(rombank_w)
 	{
-//      printf( "rom bank %02x\n", data);
+//		printf( "rom bank %02x\n", data);
+		// this might be for ram banking
 		membank("bankedroms")->set_entry(0);
 	}
 
+	DECLARE_WRITE8_MEMBER(ff80_w)
+	{
+//		printf( "ff80:%02x %02x\n", offset, data );
+	}
+
 	WRITE8_MEMBER( via0_pa_w )
 	{
 		keyColumnSelect = data;
@@ -179,10 +239,20 @@ static ADDRESS_MAP_START( clcd_mem, AS_PROGRAM, 8, clcd_state )
 	AM_RANGE(0xf800, 0xf80f) AM_DEVREADWRITE("via0", via6522_device, read, write)
 	AM_RANGE(0xf880, 0xf88f) AM_DEVREADWRITE("via1", via6522_device, read, write)
 	AM_RANGE(0xf980, 0xf981) AM_DEVREADWRITE("acia", mos6551_device, read, write)
+	AM_RANGE(0xfa00, 0xfa00) AM_WRITE(fa00_w)
+	AM_RANGE(0xfa80, 0xfa80) AM_WRITE(fa80_w)
+	AM_RANGE(0xfb00, 0xfb00) AM_WRITE(fb00_w)
+	AM_RANGE(0xfb80, 0xfb80) AM_WRITE(fb80_w)
+	AM_RANGE(0xfc00, 0xfc00) AM_WRITE(fc00_w)
+	AM_RANGE(0xfc80, 0xfc80) AM_WRITE(fc80_w)
+	AM_RANGE(0xfd00, 0xfd00) AM_WRITE(fd00_w)
+	AM_RANGE(0xfd80, 0xfd80) AM_WRITE(fd80_w)
+	AM_RANGE(0xfe00, 0xfe00) AM_WRITE(fe00_w)
+	AM_RANGE(0xfe80, 0xfe80) AM_WRITE(fe80_w)
 	AM_RANGE(0xff00, 0xff00) AM_WRITE(rombank_w)
-	AM_RANGE(0xff80, 0xff83) AM_WRITE(rambank_w)
+	AM_RANGE(0xff80, 0xff83) AM_WRITE(ff80_w)
 	AM_RANGE(0x0000, 0x3fff) AM_RAM AM_SHARE("ram")
-	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bankedroms")
+	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bankedroms") AM_WRITE(ramwrite_w)
 	AM_RANGE(0x8000, 0xffff) AM_ROM AM_REGION("maincpu", 0)
 ADDRESS_MAP_END