diff --git a/src/mame/drivers/dblcrown.c b/src/mame/drivers/dblcrown.c index 0b7e9fe1e7c..5863684fa63 100644 --- a/src/mame/drivers/dblcrown.c +++ b/src/mame/drivers/dblcrown.c @@ -1,23 +1,28 @@ /*************************************************************************** -Double Crown -(C) 1994, or maybe 1995 -cards gambling game -dfinal.c ish, but newer? + Double Crown (c) 1997 Cadence Technology / Dyna + driver by Angelo Salese -Excellent System -boardlabel: ES-9411B + TODO: + - RAM-based tiles color offset (perhaps there isn't a real palette bank, + it's just sloppy code?) + - Bogus "Hole" in main screen display + - Is the background pen really black? -28.6363 xtal -ES-9409 QFP is 208 pins.. for graphics only? -Z0840006PSC Zilog z80, is rated 6.17 MHz -OKI M82C55A-2 -65764H-5 .. 64kbit ram CMOS -2 * N341256P-25 - CMOS SRAM 256K-BIT(32KX8) -4 * dipsw 8pos -YMZ284-D (ay8910, but without i/o ports) -MAXIM MAX693ACPE is a "Microprocessor Supervisory Circuit", for watchdog? and for keeping nvram stable? +============================================================================ + Excellent System + boardlabel: ES-9411B + + 28.6363 xtal + ES-9409 QFP is 208 pins.. for graphics only? + Z0840006PSC Zilog z80, is rated 6.17 MHz + OKI M82C55A-2 + 65764H-5 .. 64kbit ram CMOS + 2 * N341256P-25 - CMOS SRAM 256K-BIT(32KX8) + 4 * dipsw 8pos + YMZ284-D (ay8910, but without i/o ports) + MAXIM MAX693ACPE is a "Microprocessor Supervisory Circuit", for watchdog? and for keeping nvram stable? ***************************************************************************/ @@ -50,6 +55,7 @@ public: UINT8 *m_pal_ram; UINT8 *m_vram; UINT8 m_vram_bank[2]; + UINT8 m_mux_data; DECLARE_READ8_MEMBER(bank_r); DECLARE_WRITE8_MEMBER(bank_w); @@ -61,6 +67,10 @@ public: DECLARE_WRITE8_MEMBER(vram_w); DECLARE_READ8_MEMBER(vram_bank_r); DECLARE_WRITE8_MEMBER(vram_bank_w); + DECLARE_READ8_MEMBER(mux_r); + DECLARE_WRITE8_MEMBER(mux_w); + DECLARE_READ8_MEMBER(in_mux_r); + DECLARE_READ8_MEMBER(in_mux_type_r); TIMER_DEVICE_CALLBACK_MEMBER(dblcrown_irq_scanline); @@ -83,6 +93,42 @@ void dblcrown_state::video_start() UINT32 dblcrown_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect ) { + gfx_element *gfx = machine().gfx[0]; + gfx_element *gfx_2 = machine().gfx[1]; + int x,y; + int count; + + count = 0xa000; + + for (y=0;y<16;y++) + { + for (x=0;x<32;x++) + { + UINT16 tile = ((m_vram[count])|(m_vram[count+1]<<8)) & 0xfff; + UINT8 col = (m_vram[count+1] >> 4) + 0x10; + + drawgfx_opaque(bitmap,cliprect,gfx_2,tile,col,0,0,x*16,y*16); + + count+=2; + } + } + + count = 0xb000; + + for (y=0;y<32;y++) + { + for (x=0;x<64;x++) + { + UINT16 tile = m_vram[count]; + UINT8 col = 0x10; // TODO + + drawgfx_transpen(bitmap,cliprect,gfx,tile,col,0,0,x*8,y*8,0); + + count+=2; + } + } + + return 0; } @@ -129,6 +175,7 @@ WRITE8_MEMBER( dblcrown_state::palette_w) r = ((datax)&0x000f)>>0; g = ((datax)&0x00f0)>>4; b = ((datax)&0x0f00)>>8; + /* TODO: remaining bits */ palette_set_color_rgb(machine(), offset, pal4bit(r), pal4bit(g), pal4bit(b)); } @@ -137,7 +184,7 @@ WRITE8_MEMBER( dblcrown_state::palette_w) READ8_MEMBER( dblcrown_state::vram_r) { UINT32 hi_offs; - hi_offs = m_vram_bank[offset & 0x1000 >> 12] << 12; + hi_offs = m_vram_bank[(offset & 0x1000) >> 12] << 12; return m_vram[(offset & 0xfff) | hi_offs]; } @@ -172,54 +219,111 @@ WRITE8_MEMBER( dblcrown_state::vram_bank_w) printf("vram bank = %02x\n",data); } +READ8_MEMBER( dblcrown_state::mux_r) +{ + return m_mux_data; +} + +WRITE8_MEMBER( dblcrown_state::mux_w) +{ + m_mux_data = data; +} + +READ8_MEMBER( dblcrown_state::in_mux_r ) +{ + const char *const muxnames[] = { "IN0", "IN1", "IN2", "IN3" }; + int i; + UINT8 res; + + res = 0; + + for(i=0;i<4;i++) + { + if(m_mux_data & 1 << i) + res |= ioport(muxnames[i])->read(); + } + + return res; +} + +READ8_MEMBER( dblcrown_state::in_mux_type_r ) +{ + const char *const muxnames[] = { "IN0", "IN1", "IN2", "IN3" }; + int i; + UINT8 res; + + res = 0xff; + + for(i=0;i<4;i++) + { + if(ioport(muxnames[i])->read() != 0xff) + res &= ~(1 << i); + } + + return res; +} + static ADDRESS_MAP_START( dblcrown_map, AS_PROGRAM, 8, dblcrown_state ) + ADDRESS_MAP_UNMAP_HIGH AM_RANGE(0x0000, 0x7fff) AM_ROM AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("rom_bank") AM_RANGE(0xa000, 0xb7ff) AM_RAM // work ram AM_RANGE(0xb800, 0xbfff) AM_RAM AM_SHARE("nvram") AM_RANGE(0xc000, 0xdfff) AM_READWRITE(vram_r, vram_w) - AM_RANGE(0xf000, 0xf1ff) AM_READWRITE(palette_r, palette_w) //AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_byte_le_w) AM_SHARE("paletteram") // TODO: correct bit order - AM_RANGE(0xfe00, 0xfeff) AM_RAM // ??? + AM_RANGE(0xf000, 0xf1ff) AM_READWRITE(palette_r, palette_w) +// AM_RANGE(0xfe00, 0xfeff) AM_RAM // ??? AM_RANGE(0xff00, 0xff01) AM_READWRITE(vram_bank_r, vram_bank_w) AM_RANGE(0xff04, 0xff04) AM_READWRITE(irq_source_r,irq_source_w) - AM_RANGE(0xff00, 0xffff) AM_RAM // ???, intentional fall-through +// AM_RANGE(0xff00, 0xffff) AM_RAM // ???, intentional fall-through ADDRESS_MAP_END static ADDRESS_MAP_START( dblcrown_io, AS_IO, 8, dblcrown_state ) - ADDRESS_MAP_GLOBAL_MASK(0xff) - AM_RANGE(0x11, 0x11) AM_READWRITE(bank_r,bank_w) + ADDRESS_MAP_GLOBAL_MASK(0xff) + ADDRESS_MAP_UNMAP_HIGH + AM_RANGE(0x00, 0x00) AM_READ_PORT("DSWA") + AM_RANGE(0x01, 0x01) AM_READ_PORT("DSWB") + AM_RANGE(0x02, 0x02) AM_READ_PORT("DSWC") + AM_RANGE(0x03, 0x03) AM_READ_PORT("DSWD") + AM_RANGE(0x04, 0x04) AM_READ(in_mux_r) + AM_RANGE(0x05, 0x05) AM_READ(in_mux_type_r) + AM_RANGE(0x11, 0x11) AM_READWRITE(bank_r,bank_w) + AM_RANGE(0x12, 0x12) AM_READWRITE(mux_r,mux_w) +// AM_RANGE(0x20, 0x20) AM_DEVREAD_LEGACY("aysnd", ay8910_r) + AM_RANGE(0x20, 0x21) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w) ADDRESS_MAP_END static INPUT_PORTS_START( dblcrown ) - /* dummy active high structure */ - PORT_START("SYSA") - PORT_DIPNAME( 0x01, 0x00, "SYSA" ) - PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x01, DEF_STR( On ) ) - PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x02, DEF_STR( On ) ) - PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x04, DEF_STR( On ) ) - PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x08, DEF_STR( On ) ) - PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x10, DEF_STR( On ) ) - PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x20, DEF_STR( On ) ) - PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x40, DEF_STR( On ) ) - PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x80, DEF_STR( On ) ) + PORT_START("IN0") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Memory Reset") + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Credit Reset") + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_KEYIN ) PORT_NAME("Note") + PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED ) + + PORT_START("IN1") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_HIGH ) PORT_NAME("Big") + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_LOW ) PORT_NAME("Small") + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_NAME("Payout") + PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED ) + + PORT_START("IN2") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_HOLD1 ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_HOLD2 ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_HOLD3 ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_POKER_HOLD4 ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD5 ) + PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED ) + + PORT_START("IN3") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_CANCEL ) PORT_NAME("Cancel / Repeat Bet") + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL ) PORT_NAME("Deal / Draw") + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_BET ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_D_UP ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) PORT_NAME("Analyzer") + PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED ) - /* dummy active low structure */ PORT_START("DSWA") PORT_DIPNAME( 0x01, 0x01, "DSWA" ) PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) @@ -239,6 +343,84 @@ static INPUT_PORTS_START( dblcrown ) PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x40, 0x40, "Input Test" ) + PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + + PORT_START("DSWB") + PORT_DIPNAME( 0x01, 0x01, "DSWB" ) + PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + + PORT_START("DSWC") + PORT_DIPNAME( 0x01, 0x01, "DSWC" ) + PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + + PORT_START("DSWD") + PORT_DIPNAME( 0x01, 0x01, "DSWD" ) + PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) @@ -298,15 +480,39 @@ TIMER_DEVICE_CALLBACK_MEMBER(dblcrown_state::dblcrown_irq_scanline) { int scanline = param; - if (scanline == 240) + if (scanline == 256) { m_maincpu->set_input_line(0, HOLD_LINE); m_irq_src = 2; } - - /* TODO: unknown source */ - if (scanline == 128) + else if ((scanline % 4) == 0) /* TODO: proper timing of this ... */ { +/* +This is the main loop of this irq source. They hooked a timer irq then polled inputs via this wacky routine. +It needs at least 64 instances because 0xa05b will be eventually nuked by the vblank irq sub-routine. + +043B: pop af +043C: push af +043D: ld a,($A05B) +0440: cp $00 +0442: jr z,$0463 +0444: cp $10 +0446: jr z,$046D +0448: cp $20 +044A: jr z,$047F +044C: cp $30 +044E: jr z,$0491 +0450: cp $40 +0452: jr z,$04AB +0454: ld a,($A05B) +0457: inc a +0458: ld ($A05B),a +045B: xor a +045C: ld ($FF04),a +045F: pop af +0460: ei +0461: reti +*/ m_maincpu->set_input_line(0, HOLD_LINE); m_irq_src = 4; } @@ -326,8 +532,8 @@ static MACHINE_CONFIG_START( dblcrown, dblcrown_state ) MCFG_SCREEN_REFRESH_RATE(60) MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) MCFG_SCREEN_UPDATE_DRIVER(dblcrown_state, screen_update) - MCFG_SCREEN_SIZE(32*8, 32*8) - MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 0*8, 32*8-1) + MCFG_SCREEN_SIZE(64*8, 64*8) + MCFG_SCREEN_VISIBLE_AREA(0*8, 40*8-1, 2*8, 30*8-1) MCFG_GFXDECODE(dblcrown) @@ -338,7 +544,7 @@ static MACHINE_CONFIG_START( dblcrown, dblcrown_state ) /* sound hardware */ MCFG_SPEAKER_STANDARD_MONO("mono") MCFG_SOUND_ADD("aysnd", AY8910, MAIN_CLOCK/12) - MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30) + MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75) MACHINE_CONFIG_END @@ -363,4 +569,4 @@ ROM_START( dblcrown ) ROM_LOAD("palce16v8h.u39", 0x0000, 0x0bf1, CRC(997b0ba9) SHA1(1c121ab74f33d5162b619740b08cc7bc694c257d) ) ROM_END -GAME( 199?, dblcrown, 0, dblcrown, dblcrown, driver_device, 0, ROT0, "Excellent System", "Double Crown", GAME_IS_SKELETON ) // 1997 DYNA copyright in tile GFX +GAME( 1997, dblcrown, 0, dblcrown, dblcrown, driver_device, 0, ROT0, "Cadence Technology", "Double Crown (v1.0.3)", GAME_NOT_WORKING | GAME_IMPERFECT_GRAPHICS ) // 1997 DYNA copyright in tile GFX