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4enlinea: Added player 1 & 2 inputs, connected to

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both AY-3-8910 ports (traced on real hardware).
Added info about the PCB connectors.
This commit is contained in:
Roberto Fresca 2014-04-02 03:18:46 +00:00
parent f6dc3b14b1
commit 373f4d57e8
1 changed files with 39 additions and 57 deletions
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96
src/mame/drivers/4enlinea.c
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@ -13,7 +13,7 @@
1x AY-3-8910 A 1x AY-3-8910 A
1x UMC UM487F (HCGA Controller) 1x UMC UM487F (HCGA Controller)
2x NEC D41464C (64K x 4-bit Dynamic NMOS RAM). 2x NEC D41464C (64K x 4-bit Dynamic NMOS RAM) for VRAM.
1x UMC UM6264A (8K x 8-bit CMOS SRAM). 1x UMC UM6264A (8K x 8-bit CMOS SRAM).
2x 27512 EPROMS. 2x 27512 EPROMS.
@ -29,6 +29,18 @@
1x 8.000 MHz crystal. ; Divided by 2 for audio CPU Z84C00AB6. 1x 8.000 MHz crystal. ; Divided by 2 for audio CPU Z84C00AB6.
1x 14.31818 MHz crystal ; For HCGA controller. 1x 14.31818 MHz crystal ; For HCGA controller.
CN1: 1 x 8 connector.
CN2: 1 x 8 connector.
CN3: 2 x 5 connector.
CN4: 2 x 5 connector.
CN5: 2 x 5 connector.
CN6: 2 x 28 Jamma connector.
CN7: 1 x 20 connector.
CN8: 1 x 4 connector.
CN9: 1 x 4 connector.
CN10: DB9 video out connector.
CN11 1 x 2 bridge connector.
************************************************************************** **************************************************************************
UM487F HCGA Controller notes... UM487F HCGA Controller notes...
@ -321,10 +333,7 @@ READ8_MEMBER(_4enlinea_state::crtc_status_r)
1: Vertical sync period. 1: Vertical sync period.
*/ */
//logerror("CRTC status read\n"); return (m_screen->vpos() >= 200) ? 0x80 : 0x00; // bit 7 is suppossed to be unused in CGA mode
return (m_screen->vpos() >= 200) ? 0x80 : 0x00;
// return (machine().rand() & 0x80); /* bit 7 ??? (it's suppossed to be unused in CGA mode) */
} }
READ8_MEMBER(_4enlinea_state::unk_e000_r) READ8_MEMBER(_4enlinea_state::unk_e000_r)
@ -390,57 +399,30 @@ ADDRESS_MAP_END
***********************************/ ***********************************/
static INPUT_PORTS_START( 4enlinea ) static INPUT_PORTS_START( 4enlinea )
PORT_START("DSW1")
PORT_DIPNAME( 0x01, 0x00, "0-0")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x00, "0-1")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x02, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x00, "0-2")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x04, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x00, "0-3")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x08, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x00, "0-4")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x00, "0-5")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x20, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x00, "0-6")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x40, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x00, "0-7")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
PORT_START("DSW2") /* Player 1 & 2 ports are tied to both AY-3-8910 ports.
PORT_DIPNAME( 0x01, 0x00, "0-0") Coin 1 & 2 are tied to the big ES2 9046 CPLD/FPGA,
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) so... It's a mystery to figure out.
PORT_DIPSETTING( 0x01, DEF_STR( On ) ) */
PORT_DIPNAME( 0x02, 0x00, "0-1") PORT_START("IN-P1")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
PORT_DIPSETTING( 0x02, DEF_STR( On ) ) PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
PORT_DIPNAME( 0x04, 0x00, "0-2") PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
PORT_DIPSETTING( 0x04, DEF_STR( On ) ) PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
PORT_DIPNAME( 0x08, 0x00, "0-3") PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
PORT_DIPSETTING( 0x08, DEF_STR( On ) ) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_DIPNAME( 0x10, 0x00, "0-4")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_START("IN-P2")
PORT_DIPSETTING( 0x10, DEF_STR( On ) ) PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
PORT_DIPNAME( 0x20, 0x00, "0-5") PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
PORT_DIPSETTING( 0x20, DEF_STR( On ) ) PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
PORT_DIPNAME( 0x40, 0x00, "0-6") PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
PORT_DIPSETTING( 0x40, DEF_STR( On ) ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
PORT_DIPNAME( 0x80, 0x00, "0-7") PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
INPUT_PORTS_END INPUT_PORTS_END
@ -516,8 +498,8 @@ static const ay8910_interface ay8910_intf =
{ {
AY8910_LEGACY_OUTPUT, AY8910_LEGACY_OUTPUT,
AY8910_DEFAULT_LOADS, AY8910_DEFAULT_LOADS,
DEVCB_NULL, DEVCB_INPUT_PORT("IN-P2"),
DEVCB_NULL, DEVCB_INPUT_PORT("IN-P1"),
DEVCB_NULL, DEVCB_NULL,
DEVCB_NULL DEVCB_NULL
}; };