mirror of
https://github.com/holub/mame
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z8.c: Modernized cpu core. [Wilbert Pol]
This commit is contained in:
Wilbert Pol
parent
3faea5bc66
commit
37866bccb3
File diff suppressed because it is too large
Load Diff
@ -23,15 +23,305 @@ enum
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Z8_GENSP = STATE_GENSP
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};
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class z8_device : public cpu_device
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{
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public:
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// construction/destruction
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z8_device(const machine_config &mconfig, device_type type, const char *name, const char *_tag, device_t *_owner, UINT32 _clock, const char *shortname, const char *source, int size);
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const { return 6; }
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virtual UINT32 execute_max_cycles() const { return 20; }
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virtual UINT32 execute_input_lines() const { return 4; }
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virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 2 - 1) / 2; }
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virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 2); }
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virtual void execute_run();
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virtual void execute_set_input(int inputnum, int state);
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
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{
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switch ( spacenum )
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{
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case AS_PROGRAM: return &m_program_config;
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case AS_DATA: return &m_data_config;
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case AS_IO: return &m_io_config;
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default: return NULL;
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}
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return NULL;
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}
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// device_state_interface overrides
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virtual void state_import(const device_state_entry &entry);
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virtual void state_export(const device_state_entry &entry);
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void state_string_export(const device_state_entry &entry, astring &string);
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 3; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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private:
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address_space_config m_program_config;
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address_space_config m_data_config;
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address_space_config m_io_config;
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address_space *m_program;
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direct_read_data *m_direct;
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address_space *m_data;
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address_space *m_io;
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/* registers */
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UINT16 m_pc; /* program counter */
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UINT8 m_r[256]; /* register file */
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UINT8 m_input[4]; /* port input latches */
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UINT8 m_output[4]; /* port output latches */
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UINT8 m_t0; /* timer 0 current count */
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UINT8 m_t1; /* timer 1 current count */
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/* fake registers */
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UINT16 m_fake_sp; /* fake stack pointer */
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UINT8 m_fake_r[16]; /* fake working registers */
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/* interrupts */
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int m_irq[6]; /* interrupts */
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/* execution logic */
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int m_icount; /* instruction counter */
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/* timers */
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emu_timer *m_t0_timer;
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emu_timer *m_t1_timer;
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TIMER_CALLBACK_MEMBER( t0_tick );
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TIMER_CALLBACK_MEMBER( t1_tick );
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inline UINT8 fetch();
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inline UINT8 register_read(UINT8 offset);
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inline UINT16 register_pair_read(UINT8 offset);
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inline void register_write(UINT8 offset, UINT8 data);
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inline void register_pair_write(UINT8 offset, UINT16 data);
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inline UINT8 get_working_register(int offset);
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inline UINT8 get_register(UINT8 offset);
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inline UINT8 get_intermediate_register(int offset);
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inline void stack_push_byte(UINT8 src);
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inline void stack_push_word(UINT16 src);
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inline UINT8 stack_pop_byte();
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inline UINT16 stack_pop_word();
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inline void set_flag(UINT8 flag, int state);
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inline void clear(UINT8 dst);
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inline void load(UINT8 dst, UINT8 src);
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inline void load_from_memory(address_space *space);
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inline void load_to_memory(address_space *space);
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inline void load_from_memory_autoinc(address_space *space);
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inline void load_to_memory_autoinc(address_space *space);
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inline void pop(UINT8 dst);
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inline void push(UINT8 src);
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inline void add_carry(UINT8 dst, INT8 src);
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inline void add(UINT8 dst, INT8 src);
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inline void compare(UINT8 dst, UINT8 src);
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inline void decimal_adjust(UINT8 dst);
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inline void decrement(UINT8 dst);
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inline void decrement_word(UINT8 dst);
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inline void increment(UINT8 dst);
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inline void increment_word(UINT8 dst);
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inline void subtract_carry(UINT8 dst, UINT8 src);
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inline void subtract(UINT8 dst, UINT8 src);
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inline void _and(UINT8 dst, UINT8 src);
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inline void complement(UINT8 dst);
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inline void _or(UINT8 dst, UINT8 src);
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inline void _xor(UINT8 dst, UINT8 src);
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inline void call(UINT16 dst);
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inline void jump(UINT16 dst);
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inline int check_condition_code(int cc);
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inline void test_complement_under_mask(UINT8 dst, UINT8 src);
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inline void test_under_mask(UINT8 dst, UINT8 src);
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inline void rotate_left(UINT8 dst);
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inline void rotate_left_carry(UINT8 dst);
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inline void rotate_right(UINT8 dst);
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inline void rotate_right_carry(UINT8 dst);
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inline void shift_right_arithmetic(UINT8 dst);
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inline void swap(UINT8 dst);
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#define INSTRUCTION(inst) void inst(UINT8 opcode, int *cycles);
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INSTRUCTION( illegal );
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INSTRUCTION( clr_R1 );
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INSTRUCTION( clr_IR1 );
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INSTRUCTION( ld_r1_IM );
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INSTRUCTION( ld_r1_R2 );
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INSTRUCTION( ld_r2_R1 );
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INSTRUCTION( ld_Ir1_r2 );
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INSTRUCTION( ld_R2_IR1 );
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INSTRUCTION( ld_r1_x_R2 );
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INSTRUCTION( ld_r2_x_R1 );
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INSTRUCTION( ld_r1_r2 );
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INSTRUCTION( ld_r1_Ir2 );
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INSTRUCTION( ld_R2_R1 );
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INSTRUCTION( ld_IR2_R1 );
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INSTRUCTION( ld_R1_IM );
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INSTRUCTION( ld_IR1_IM );
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INSTRUCTION( ldc_r1_Irr2 );
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INSTRUCTION( ldc_r2_Irr1 );
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INSTRUCTION( ldci_Ir1_Irr2 );
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INSTRUCTION( ldci_Ir2_Irr1 );
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INSTRUCTION( lde_r1_Irr2 );
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INSTRUCTION( lde_r2_Irr1 );
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INSTRUCTION( ldei_Ir1_Irr2 );
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INSTRUCTION( ldei_Ir2_Irr1 );
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INSTRUCTION( pop_R1 );
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INSTRUCTION( pop_IR1 );
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INSTRUCTION( push_R2 );
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INSTRUCTION( push_IR2 );
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INSTRUCTION( adc_r1_r2 );
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INSTRUCTION( adc_r1_Ir2 );
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INSTRUCTION( adc_R2_R1 );
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INSTRUCTION( adc_IR2_R1 );
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INSTRUCTION( adc_R1_IM );
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INSTRUCTION( adc_IR1_IM );
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INSTRUCTION( add_r1_r2 );
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INSTRUCTION( add_r1_Ir2 );
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INSTRUCTION( add_R2_R1 );
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INSTRUCTION( add_IR2_R1 );
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INSTRUCTION( add_R1_IM );
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INSTRUCTION( add_IR1_IM );
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INSTRUCTION( cp_r1_r2 );
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INSTRUCTION( cp_r1_Ir2 );
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INSTRUCTION( cp_R2_R1 );
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INSTRUCTION( cp_IR2_R1 );
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INSTRUCTION( cp_R1_IM );
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INSTRUCTION( cp_IR1_IM );
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INSTRUCTION( da_R1 );
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INSTRUCTION( da_IR1 );
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INSTRUCTION( dec_R1 );
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INSTRUCTION( dec_IR1 );
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INSTRUCTION( decw_RR1 );
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INSTRUCTION( decw_IR1 );
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INSTRUCTION( inc_r1 );
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INSTRUCTION( inc_R1 );
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INSTRUCTION( inc_IR1 );
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INSTRUCTION( incw_RR1 );
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INSTRUCTION( incw_IR1 );
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INSTRUCTION( sbc_r1_r2 );
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INSTRUCTION( sbc_r1_Ir2 );
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INSTRUCTION( sbc_R2_R1 );
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INSTRUCTION( sbc_IR2_R1 );
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INSTRUCTION( sbc_R1_IM );
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INSTRUCTION( sbc_IR1_IM );
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INSTRUCTION( sub_r1_r2 );
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INSTRUCTION( sub_r1_Ir2 );
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INSTRUCTION( sub_R2_R1 );
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INSTRUCTION( sub_IR2_R1 );
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INSTRUCTION( sub_R1_IM );
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INSTRUCTION( sub_IR1_IM );
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INSTRUCTION( and_r1_r2 );
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INSTRUCTION( and_r1_Ir2 );
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INSTRUCTION( and_R2_R1 );
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INSTRUCTION( and_IR2_R1 );
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INSTRUCTION( and_R1_IM );
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INSTRUCTION( and_IR1_IM );
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INSTRUCTION( com_R1 );
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INSTRUCTION( com_IR1 );
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INSTRUCTION( or_r1_r2 );
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INSTRUCTION( or_r1_Ir2 );
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INSTRUCTION( or_R2_R1 );
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INSTRUCTION( or_IR2_R1 );
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INSTRUCTION( or_R1_IM );
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INSTRUCTION( or_IR1_IM );
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INSTRUCTION( xor_r1_r2 );
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INSTRUCTION( xor_r1_Ir2 );
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INSTRUCTION( xor_R2_R1 );
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INSTRUCTION( xor_IR2_R1 );
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INSTRUCTION( xor_R1_IM );
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INSTRUCTION( xor_IR1_IM );
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INSTRUCTION( call_IRR1 );
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INSTRUCTION( call_DA );
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INSTRUCTION( djnz_r1_RA );
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INSTRUCTION( iret );
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INSTRUCTION( ret );
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INSTRUCTION( jp_IRR1 );
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INSTRUCTION( jp_cc_DA )
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INSTRUCTION( jr_cc_RA )
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INSTRUCTION( tcm_r1_r2 );
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INSTRUCTION( tcm_r1_Ir2 );
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INSTRUCTION( tcm_R2_R1 );
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INSTRUCTION( tcm_IR2_R1 );
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INSTRUCTION( tcm_R1_IM );
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INSTRUCTION( tcm_IR1_IM );
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INSTRUCTION( tm_r1_r2 );
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INSTRUCTION( tm_r1_Ir2 );
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INSTRUCTION( tm_R2_R1 );
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INSTRUCTION( tm_IR2_R1 );
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INSTRUCTION( tm_R1_IM );
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INSTRUCTION( tm_IR1_IM );
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INSTRUCTION( rl_R1 );
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INSTRUCTION( rl_IR1 );
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INSTRUCTION( rlc_R1 );
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INSTRUCTION( rlc_IR1 );
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INSTRUCTION( rr_R1 );
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INSTRUCTION( rr_IR1 );
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INSTRUCTION( rrc_R1 );
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INSTRUCTION( rrc_IR1 );
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INSTRUCTION( sra_R1 );
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INSTRUCTION( sra_IR1 );
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INSTRUCTION( swap_R1 );
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INSTRUCTION( swap_IR1 );
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INSTRUCTION( ccf );
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INSTRUCTION( di );
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INSTRUCTION( ei );
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INSTRUCTION( nop );
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INSTRUCTION( rcf );
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INSTRUCTION( scf );
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INSTRUCTION( srp_IM );
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#undef INSTRUCTION
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typedef void (z8_device::*z8_opcode_func) (UINT8 opcode, int *cycles);
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struct z8_opcode_map
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{
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z8_opcode_func function;
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int execution_cycles;
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int pipeline_cycles;
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};
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static const z8_opcode_map Z8601_OPCODE_MAP[256];
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};
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class z8601_device : public z8_device
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{
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public:
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z8601_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
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};
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class ub8830d_device : public z8_device
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{
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public:
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ub8830d_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
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};
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class z8611_device : public z8_device
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{
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public:
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z8611_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
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};
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/* Zilog Z8601 */
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DECLARE_LEGACY_CPU_DEVICE(Z8601, z8601);
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extern const device_type Z8601;
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/* VEB Mikroelektronik Erfurt UB8830D MME */
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DECLARE_LEGACY_CPU_DEVICE(UB8830D, ub8830d);
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extern const device_type UB8830D;
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/* Zilog Z8611 */
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DECLARE_LEGACY_CPU_DEVICE(Z8611, z8611);
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extern const device_type Z8611;
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CPU_DISASSEMBLE( z8 );
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#endif
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@ -11,118 +11,118 @@
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MACROS
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***************************************************************************/
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#define read(_reg) register_read(cpustate, _reg)
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#define r(_data) get_working_register(cpustate, _data)
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#define Ir(_data) get_intermediate_register(cpustate, get_working_register(cpustate, _data))
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#define R get_register(cpustate, fetch(cpustate))
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#define IR get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate)))
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#define RR get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate)))
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#define IM fetch(cpustate)
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#define flag(_flag) ((cpustate->r[Z8_REGISTER_FLAGS] & Z8_FLAGS##_##_flag) ? 1 : 0)
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#define read(_reg) register_read(_reg)
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#define r(_data) get_working_register(_data)
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#define Ir(_data) get_intermediate_register(get_working_register(_data))
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#define R get_register(fetch())
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#define IR get_intermediate_register(get_register(fetch()))
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#define RR get_intermediate_register(get_register(fetch()))
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#define IM fetch()
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#define flag(_flag) ((m_r[Z8_REGISTER_FLAGS] & Z8_FLAGS##_##_flag) ? 1 : 0)
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#define mode_r1_r2(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst_src = fetch();\
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UINT8 dst = r(dst_src >> 4);\
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UINT8 src = read(r(dst_src & 0x0f));\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_r1_Ir2(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst_src = fetch();\
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UINT8 dst = r(dst_src >> 4);\
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UINT8 src = read(Ir(dst_src & 0x0f));\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_R2_R1(_func) \
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UINT8 src = read(R);\
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UINT8 dst = R;\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_IR2_R1(_func) \
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UINT8 src = read(R);\
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UINT8 dst = IR;\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_R1_IM(_func) \
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UINT8 dst = R;\
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UINT8 src = IM;\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_IR1_IM(_func) \
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UINT8 dst = IR;\
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UINT8 src = IM;\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_r1(_func) \
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UINT8 dst = r(opcode >> 4);\
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_func(cpustate, dst);
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_func(dst);
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#define mode_R1(_func) \
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UINT8 dst = R;\
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_func(cpustate, dst);
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_func(dst);
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#define mode_RR1(_func) \
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UINT8 dst = R;\
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_func(cpustate, dst);
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_func(dst);
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#define mode_IR1(_func) \
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UINT8 dst = IR;\
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_func(cpustate, dst);
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_func(dst);
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#define mode_r1_IM(_func) \
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UINT8 dst = r(opcode >> 4);\
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UINT8 src = IM;\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_r1_R2(_func) \
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UINT8 dst = r(opcode >> 4);\
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UINT8 src = read(R);\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_r2_R1(_func) \
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UINT8 src = read(r(opcode >> 4));\
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UINT8 dst = R;\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_Ir1_r2(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst_src = fetch();\
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UINT8 dst = Ir(dst_src >> 4);\
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UINT8 src = read(r(dst_src & 0x0f));\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_R2_IR1(_func) \
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UINT8 src = read(R);\
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UINT8 dst = IR;\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_r1_x_R2(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst_src = fetch();\
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UINT8 dst = r(dst_src >> 4);\
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UINT8 src = read(read(r(dst_src & 0x0f)) + R);\
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_func(cpustate, dst, src);
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_func(dst, src);
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#define mode_r2_x_R1(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst_src = fetch();\
|
||||
UINT8 dst = R + read(r(dst_src & 0x0f));\
|
||||
UINT8 src = read(r(dst_src >> 4));\
|
||||
_func(cpustate, dst, src);
|
||||
_func(dst, src);
|
||||
|
||||
/***************************************************************************
|
||||
LOAD INSTRUCTIONS
|
||||
***************************************************************************/
|
||||
|
||||
static void clear(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::clear(UINT8 dst)
|
||||
{
|
||||
/* dst <- 0 */
|
||||
register_write(cpustate, dst, 0);
|
||||
register_write(dst, 0);
|
||||
}
|
||||
|
||||
INSTRUCTION( clr_R1 ) { mode_R1(clear) }
|
||||
INSTRUCTION( clr_IR1 ) { mode_IR1(clear) }
|
||||
|
||||
static void load(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
void z8_device::load(UINT8 dst, UINT8 src)
|
||||
{
|
||||
/* dst <- src */
|
||||
register_write(cpustate, dst, src);
|
||||
register_write(dst, src);
|
||||
}
|
||||
|
||||
INSTRUCTION( ld_r1_IM ) { mode_r1_IM(load) }
|
||||
@ -140,86 +140,86 @@ INSTRUCTION( ld_IR2_R1 ) { mode_IR2_R1(load) }
|
||||
INSTRUCTION( ld_R1_IM ) { mode_R1_IM(load) }
|
||||
INSTRUCTION( ld_IR1_IM ) { mode_IR1_IM(load) }
|
||||
|
||||
static void load_from_memory(z8_state *cpustate, address_space *space)
|
||||
void z8_device::load_from_memory(address_space *space)
|
||||
{
|
||||
UINT8 operands = fetch(cpustate);
|
||||
UINT8 dst = get_working_register(cpustate, operands >> 4);
|
||||
UINT8 src = get_working_register(cpustate, operands & 0x0f);
|
||||
UINT8 operands = fetch();
|
||||
UINT8 dst = get_working_register(operands >> 4);
|
||||
UINT8 src = get_working_register(operands & 0x0f);
|
||||
|
||||
UINT16 address = register_pair_read(cpustate, src);
|
||||
UINT8 data = cpustate->direct->read_decrypted_byte(address);
|
||||
UINT16 address = register_pair_read(src);
|
||||
UINT8 data = m_direct->read_decrypted_byte(address);
|
||||
|
||||
register_write(cpustate, dst, data);
|
||||
register_write(dst, data);
|
||||
}
|
||||
|
||||
static void load_to_memory(z8_state *cpustate, address_space *space)
|
||||
void z8_device::load_to_memory(address_space *space)
|
||||
{
|
||||
UINT8 operands = fetch(cpustate);
|
||||
UINT8 src = get_working_register(cpustate, operands >> 4);
|
||||
UINT8 dst = get_working_register(cpustate, operands & 0x0f);
|
||||
UINT8 operands = fetch();
|
||||
UINT8 src = get_working_register(operands >> 4);
|
||||
UINT8 dst = get_working_register(operands & 0x0f);
|
||||
|
||||
UINT16 address = register_pair_read(cpustate, dst);
|
||||
UINT8 data = register_read(cpustate, src);
|
||||
UINT16 address = register_pair_read(dst);
|
||||
UINT8 data = register_read(src);
|
||||
|
||||
cpustate->program->write_byte(address, data);
|
||||
m_program->write_byte(address, data);
|
||||
}
|
||||
|
||||
static void load_from_memory_autoinc(z8_state *cpustate, address_space *space)
|
||||
void z8_device::load_from_memory_autoinc(address_space *space)
|
||||
{
|
||||
UINT8 operands = fetch(cpustate);
|
||||
UINT8 dst = get_working_register(cpustate, operands >> 4);
|
||||
UINT8 real_dst = get_intermediate_register(cpustate, dst);
|
||||
UINT8 src = get_working_register(cpustate, operands & 0x0f);
|
||||
UINT8 operands = fetch();
|
||||
UINT8 dst = get_working_register(operands >> 4);
|
||||
UINT8 real_dst = get_intermediate_register(dst);
|
||||
UINT8 src = get_working_register(operands & 0x0f);
|
||||
|
||||
UINT16 address = register_pair_read(cpustate, src);
|
||||
UINT8 data = cpustate->direct->read_decrypted_byte(address);
|
||||
UINT16 address = register_pair_read(src);
|
||||
UINT8 data = m_direct->read_decrypted_byte(address);
|
||||
|
||||
register_write(cpustate, real_dst, data);
|
||||
register_write(real_dst, data);
|
||||
|
||||
register_write(cpustate, dst, real_dst + 1);
|
||||
register_pair_write(cpustate, src, address + 1);
|
||||
register_write(dst, real_dst + 1);
|
||||
register_pair_write(src, address + 1);
|
||||
}
|
||||
|
||||
static void load_to_memory_autoinc(z8_state *cpustate, address_space *space)
|
||||
void z8_device::load_to_memory_autoinc(address_space *space)
|
||||
{
|
||||
UINT8 operands = fetch(cpustate);
|
||||
UINT8 src = get_working_register(cpustate, operands >> 4);
|
||||
UINT8 dst = get_working_register(cpustate, operands & 0x0f);
|
||||
UINT8 real_src = get_intermediate_register(cpustate, src);
|
||||
UINT8 operands = fetch();
|
||||
UINT8 src = get_working_register(operands >> 4);
|
||||
UINT8 dst = get_working_register(operands & 0x0f);
|
||||
UINT8 real_src = get_intermediate_register(src);
|
||||
|
||||
UINT16 address = register_pair_read(cpustate, dst);
|
||||
UINT8 data = register_read(cpustate, real_src);
|
||||
UINT16 address = register_pair_read(dst);
|
||||
UINT8 data = register_read(real_src);
|
||||
|
||||
cpustate->program->write_byte(address, data);
|
||||
m_program->write_byte(address, data);
|
||||
|
||||
register_pair_write(cpustate, dst, address + 1);
|
||||
register_write(cpustate, src, real_src + 1);
|
||||
register_pair_write(dst, address + 1);
|
||||
register_write(src, real_src + 1);
|
||||
}
|
||||
|
||||
INSTRUCTION( ldc_r1_Irr2 ) { load_from_memory(cpustate, cpustate->program); }
|
||||
INSTRUCTION( ldc_r2_Irr1 ) { load_to_memory(cpustate, cpustate->program); }
|
||||
INSTRUCTION( ldci_Ir1_Irr2 ) { load_from_memory_autoinc(cpustate, cpustate->program); }
|
||||
INSTRUCTION( ldci_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->program); }
|
||||
INSTRUCTION( lde_r1_Irr2 ) { load_from_memory(cpustate, cpustate->data); }
|
||||
INSTRUCTION( lde_r2_Irr1 ) { load_to_memory(cpustate, cpustate->data); }
|
||||
INSTRUCTION( ldei_Ir1_Irr2 ) { load_from_memory_autoinc(cpustate, cpustate->data); }
|
||||
INSTRUCTION( ldei_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->data); }
|
||||
INSTRUCTION( ldc_r1_Irr2 ) { load_from_memory(m_program); }
|
||||
INSTRUCTION( ldc_r2_Irr1 ) { load_to_memory(m_program); }
|
||||
INSTRUCTION( ldci_Ir1_Irr2 ) { load_from_memory_autoinc(m_program); }
|
||||
INSTRUCTION( ldci_Ir2_Irr1 ) { load_to_memory_autoinc(m_program); }
|
||||
INSTRUCTION( lde_r1_Irr2 ) { load_from_memory(m_data); }
|
||||
INSTRUCTION( lde_r2_Irr1 ) { load_to_memory(m_data); }
|
||||
INSTRUCTION( ldei_Ir1_Irr2 ) { load_from_memory_autoinc(m_data); }
|
||||
INSTRUCTION( ldei_Ir2_Irr1 ) { load_to_memory_autoinc(m_data); }
|
||||
|
||||
static void pop(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::pop(UINT8 dst)
|
||||
{
|
||||
/* dst <- @SP
|
||||
SP <- SP + 1 */
|
||||
register_write(cpustate, dst, stack_pop_byte(cpustate));
|
||||
register_write(dst, stack_pop_byte());
|
||||
}
|
||||
|
||||
INSTRUCTION( pop_R1 ) { mode_R1(pop) }
|
||||
INSTRUCTION( pop_IR1 ) { mode_IR1(pop) }
|
||||
|
||||
static void push(z8_state *cpustate, UINT8 src)
|
||||
void z8_device::push(UINT8 src)
|
||||
{
|
||||
/* SP <- SP - 1
|
||||
@SP <- src */
|
||||
stack_push_byte(cpustate, read(src));
|
||||
stack_push_byte(read(src));
|
||||
}
|
||||
|
||||
INSTRUCTION( push_R2 ) { mode_R1(push) }
|
||||
@ -229,10 +229,10 @@ INSTRUCTION( push_IR2 ) { mode_IR1(push) }
|
||||
ARITHMETIC INSTRUCTIONS
|
||||
***************************************************************************/
|
||||
|
||||
static void add_carry(z8_state *cpustate, UINT8 dst, INT8 src)
|
||||
void z8_device::add_carry(UINT8 dst, INT8 src)
|
||||
{
|
||||
/* dst <- dst + src + C */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT16 new_data = data + src + flag(C);
|
||||
|
||||
set_flag_c(new_data & 0x100);
|
||||
@ -242,7 +242,7 @@ static void add_carry(z8_state *cpustate, UINT8 dst, INT8 src)
|
||||
set_flag_d(0);
|
||||
set_flag_h(((data & 0x1f) == 0x0f) && ((new_data & 0x1f) == 0x10));
|
||||
|
||||
register_write(cpustate, dst, new_data & 0xff);
|
||||
register_write(dst, new_data & 0xff);
|
||||
}
|
||||
|
||||
INSTRUCTION( adc_r1_r2 ) { mode_r1_r2(add_carry) }
|
||||
@ -252,10 +252,10 @@ INSTRUCTION( adc_IR2_R1 ) { mode_IR2_R1(add_carry) }
|
||||
INSTRUCTION( adc_R1_IM ) { mode_R1_IM(add_carry) }
|
||||
INSTRUCTION( adc_IR1_IM ) { mode_IR1_IM(add_carry) }
|
||||
|
||||
static void add(z8_state *cpustate, UINT8 dst, INT8 src)
|
||||
void z8_device::add(UINT8 dst, INT8 src)
|
||||
{
|
||||
/* dst <- dst + src */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT16 new_data = data + src;
|
||||
|
||||
set_flag_c(new_data & 0x100);
|
||||
@ -265,7 +265,7 @@ static void add(z8_state *cpustate, UINT8 dst, INT8 src)
|
||||
set_flag_d(0);
|
||||
set_flag_h(((data & 0x1f) == 0x0f) && ((new_data & 0x1f) == 0x10));
|
||||
|
||||
register_write(cpustate, dst, new_data & 0xff);
|
||||
register_write(dst, new_data & 0xff);
|
||||
}
|
||||
|
||||
INSTRUCTION( add_r1_r2 ) { mode_r1_r2(add) }
|
||||
@ -275,10 +275,10 @@ INSTRUCTION( add_IR2_R1 ) { mode_IR2_R1(add) }
|
||||
INSTRUCTION( add_R1_IM ) { mode_R1_IM(add) }
|
||||
INSTRUCTION( add_IR1_IM ) { mode_IR1_IM(add) }
|
||||
|
||||
static void compare(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
void z8_device::compare(UINT8 dst, UINT8 src)
|
||||
{
|
||||
/* dst - src */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT16 new_data = data - src;
|
||||
|
||||
set_flag_c(!(new_data & 0x100));
|
||||
@ -294,78 +294,78 @@ INSTRUCTION( cp_IR2_R1 ) { mode_IR2_R1(compare) }
|
||||
INSTRUCTION( cp_R1_IM ) { mode_R1_IM(compare) }
|
||||
INSTRUCTION( cp_IR1_IM ) { mode_IR1_IM(compare) }
|
||||
|
||||
static void decimal_adjust(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::decimal_adjust(UINT8 dst)
|
||||
{
|
||||
}
|
||||
|
||||
INSTRUCTION( da_R1 ) { mode_R1(decimal_adjust) }
|
||||
INSTRUCTION( da_IR1 ) { mode_IR1(decimal_adjust) }
|
||||
|
||||
static void decrement(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::decrement(UINT8 dst)
|
||||
{
|
||||
/* dst <- dst - 1 */
|
||||
UINT8 data = register_read(cpustate, dst) - 1;
|
||||
UINT8 data = register_read(dst) - 1;
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x80);
|
||||
set_flag_v(data == 0x7f);
|
||||
|
||||
register_write(cpustate, dst, data);
|
||||
register_write(dst, data);
|
||||
}
|
||||
|
||||
INSTRUCTION( dec_R1 ) { mode_R1(decrement) }
|
||||
INSTRUCTION( dec_IR1 ) { mode_IR1(decrement) }
|
||||
|
||||
static void decrement_word(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::decrement_word(UINT8 dst)
|
||||
{
|
||||
/* dst <- dst - 1 */
|
||||
UINT16 data = register_pair_read(cpustate, dst) - 1;
|
||||
UINT16 data = register_pair_read(dst) - 1;
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x8000);
|
||||
set_flag_v(data == 0x7fff);
|
||||
|
||||
register_pair_write(cpustate, dst, data);
|
||||
register_pair_write(dst, data);
|
||||
}
|
||||
|
||||
INSTRUCTION( decw_RR1 ) { mode_RR1(decrement_word) }
|
||||
INSTRUCTION( decw_IR1 ) { mode_IR1(decrement_word) }
|
||||
|
||||
static void increment(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::increment(UINT8 dst)
|
||||
{
|
||||
/* dst <- dst + 1 */
|
||||
UINT8 data = register_read(cpustate, dst) + 1;
|
||||
UINT8 data = register_read(dst) + 1;
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x80);
|
||||
set_flag_v(data == 0x80);
|
||||
|
||||
register_write(cpustate, dst, data);
|
||||
register_write(dst, data);
|
||||
}
|
||||
|
||||
INSTRUCTION( inc_r1 ) { mode_r1(increment) }
|
||||
INSTRUCTION( inc_R1 ) { mode_R1(increment) }
|
||||
INSTRUCTION( inc_IR1 ) { mode_IR1(increment) }
|
||||
|
||||
static void increment_word(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::increment_word(UINT8 dst)
|
||||
{
|
||||
/* dst <- dst + 1 */
|
||||
UINT16 data = register_pair_read(cpustate, dst) + 1;
|
||||
UINT16 data = register_pair_read(dst) + 1;
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x8000);
|
||||
set_flag_v(data == 0x8000);
|
||||
|
||||
register_pair_write(cpustate, dst, data);
|
||||
register_pair_write(dst, data);
|
||||
}
|
||||
|
||||
INSTRUCTION( incw_RR1 ) { mode_RR1(increment_word) }
|
||||
INSTRUCTION( incw_IR1 ) { mode_IR1(increment_word) }
|
||||
|
||||
static void subtract_carry(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
void z8_device::subtract_carry(UINT8 dst, UINT8 src)
|
||||
{
|
||||
/* dst <- dst - src - C */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT16 new_data = data - src;
|
||||
|
||||
set_flag_c(!(new_data & 0x100));
|
||||
@ -375,7 +375,7 @@ static void subtract_carry(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
set_flag_d(1);
|
||||
set_flag_h(!(((data & 0x1f) == 0x0f) && ((new_data & 0x1f) == 0x10)));
|
||||
|
||||
register_write(cpustate, dst, new_data & 0xff);
|
||||
register_write(dst, new_data & 0xff);
|
||||
}
|
||||
|
||||
INSTRUCTION( sbc_r1_r2 ) { mode_r1_r2(subtract_carry) }
|
||||
@ -385,10 +385,10 @@ INSTRUCTION( sbc_IR2_R1 ) { mode_IR2_R1(subtract_carry) }
|
||||
INSTRUCTION( sbc_R1_IM ) { mode_R1_IM(subtract_carry) }
|
||||
INSTRUCTION( sbc_IR1_IM ) { mode_IR1_IM(subtract_carry) }
|
||||
|
||||
static void subtract(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
void z8_device::subtract(UINT8 dst, UINT8 src)
|
||||
{
|
||||
/* dst <- dst - src */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT16 new_data = data - src;
|
||||
|
||||
set_flag_c(!(new_data & 0x100));
|
||||
@ -398,7 +398,7 @@ static void subtract(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
set_flag_d(1);
|
||||
set_flag_h(!(((data & 0x1f) == 0x0f) && ((new_data & 0x1f) == 0x10)));
|
||||
|
||||
register_write(cpustate, dst, new_data & 0xff);
|
||||
register_write(dst, new_data & 0xff);
|
||||
}
|
||||
|
||||
INSTRUCTION( sub_r1_r2 ) { mode_r1_r2(subtract) }
|
||||
@ -412,11 +412,11 @@ INSTRUCTION( sub_IR1_IM ) { mode_IR1_IM(subtract) }
|
||||
LOGICAL INSTRUCTIONS
|
||||
***************************************************************************/
|
||||
|
||||
static void _and(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
void z8_device::_and(UINT8 dst, UINT8 src)
|
||||
{
|
||||
/* dst <- dst AND src */
|
||||
UINT8 data = register_read(cpustate, dst) & src;
|
||||
register_write(cpustate, dst, data);
|
||||
UINT8 data = register_read(dst) & src;
|
||||
register_write(dst, data);
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x80);
|
||||
@ -430,11 +430,11 @@ INSTRUCTION( and_IR2_R1 ) { mode_IR2_R1(_and) }
|
||||
INSTRUCTION( and_R1_IM ) { mode_R1_IM(_and) }
|
||||
INSTRUCTION( and_IR1_IM ) { mode_IR1_IM(_and) }
|
||||
|
||||
static void complement(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::complement(UINT8 dst)
|
||||
{
|
||||
/* dst <- NOT dst */
|
||||
UINT8 data = register_read(cpustate, dst) ^ 0xff;
|
||||
register_write(cpustate, dst, data);
|
||||
UINT8 data = register_read(dst) ^ 0xff;
|
||||
register_write(dst, data);
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x80);
|
||||
@ -444,11 +444,11 @@ static void complement(z8_state *cpustate, UINT8 dst)
|
||||
INSTRUCTION( com_R1 ) { mode_R1(complement) }
|
||||
INSTRUCTION( com_IR1 ) { mode_IR1(complement) }
|
||||
|
||||
static void _or(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
void z8_device::_or(UINT8 dst, UINT8 src)
|
||||
{
|
||||
/* dst <- dst OR src */
|
||||
UINT8 data = register_read(cpustate, dst) | src;
|
||||
register_write(cpustate, dst, data);
|
||||
UINT8 data = register_read(dst) | src;
|
||||
register_write(dst, data);
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x80);
|
||||
@ -462,11 +462,11 @@ INSTRUCTION( or_IR2_R1 ) { mode_IR2_R1(_or) }
|
||||
INSTRUCTION( or_R1_IM ) { mode_R1_IM(_or) }
|
||||
INSTRUCTION( or_IR1_IM ) { mode_IR1_IM(_or) }
|
||||
|
||||
static void _xor(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
void z8_device::_xor(UINT8 dst, UINT8 src)
|
||||
{
|
||||
/* dst <- dst XOR src */
|
||||
UINT8 data = register_read(cpustate, dst) ^ src;
|
||||
register_write(cpustate, dst, data);
|
||||
UINT8 data = register_read(dst) ^ src;
|
||||
register_write(dst, data);
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x80);
|
||||
@ -484,28 +484,28 @@ INSTRUCTION( xor_IR1_IM ) { mode_IR1_IM(_xor) }
|
||||
PROGRAM CONTROL INSTRUCTIONS
|
||||
***************************************************************************/
|
||||
|
||||
static void call(z8_state *cpustate, UINT16 dst)
|
||||
void z8_device::call(UINT16 dst)
|
||||
{
|
||||
stack_push_word(cpustate, cpustate->pc);
|
||||
cpustate->pc = dst;
|
||||
stack_push_word(m_pc);
|
||||
m_pc = dst;
|
||||
}
|
||||
|
||||
INSTRUCTION( call_IRR1 ) { UINT16 dst = register_pair_read(cpustate, get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate)))); call(cpustate, dst); }
|
||||
INSTRUCTION( call_DA ) { UINT16 dst = (fetch(cpustate) << 8) | fetch(cpustate); call(cpustate, dst); }
|
||||
INSTRUCTION( call_IRR1 ) { UINT16 dst = register_pair_read(get_intermediate_register(get_register(fetch()))); call(dst); }
|
||||
INSTRUCTION( call_DA ) { UINT16 dst = (fetch() << 8) | fetch(); call(dst); }
|
||||
|
||||
INSTRUCTION( djnz_r1_RA )
|
||||
{
|
||||
INT8 ra = (INT8)fetch(cpustate);
|
||||
INT8 ra = (INT8)fetch();
|
||||
|
||||
/* r <- r - 1 */
|
||||
int r = get_working_register(cpustate, opcode >> 4);
|
||||
UINT8 data = register_read(cpustate, r) - 1;
|
||||
register_write(cpustate, r, data);
|
||||
int r = get_working_register(opcode >> 4);
|
||||
UINT8 data = register_read(r) - 1;
|
||||
register_write(r, data);
|
||||
|
||||
/* if r<>0, PC <- PC + dst */
|
||||
if (data != 0)
|
||||
{
|
||||
cpustate->pc += ra;
|
||||
m_pc += ra;
|
||||
*cycles += 2;
|
||||
}
|
||||
}
|
||||
@ -514,32 +514,32 @@ INSTRUCTION( iret )
|
||||
{
|
||||
/* FLAGS <- @SP
|
||||
SP <- SP + 1 */
|
||||
register_write(cpustate, Z8_REGISTER_FLAGS, stack_pop_byte(cpustate));
|
||||
register_write(Z8_REGISTER_FLAGS, stack_pop_byte());
|
||||
|
||||
/* PC <- @SP
|
||||
SP <- SP + 2 */
|
||||
cpustate->pc = stack_pop_word(cpustate);
|
||||
m_pc = stack_pop_word();
|
||||
|
||||
/* IMR (7) <- 1 */
|
||||
cpustate->r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE;
|
||||
m_r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE;
|
||||
}
|
||||
|
||||
INSTRUCTION( ret )
|
||||
{
|
||||
/* PC <- @SP
|
||||
SP <- SP + 2 */
|
||||
cpustate->pc = stack_pop_word(cpustate);
|
||||
m_pc = stack_pop_word();
|
||||
}
|
||||
|
||||
static void jump(z8_state *cpustate, UINT16 dst)
|
||||
void z8_device::jump(UINT16 dst)
|
||||
{
|
||||
/* PC <- dst */
|
||||
cpustate->pc = dst;
|
||||
m_pc = dst;
|
||||
}
|
||||
|
||||
INSTRUCTION( jp_IRR1 ) { jump(cpustate, register_pair_read(cpustate, IR)); }
|
||||
INSTRUCTION( jp_IRR1 ) { jump(register_pair_read(IR)); }
|
||||
|
||||
static int check_condition_code(z8_state *cpustate, int cc)
|
||||
int z8_device::check_condition_code(int cc)
|
||||
{
|
||||
int truth = 0;
|
||||
|
||||
@ -568,25 +568,25 @@ static int check_condition_code(z8_state *cpustate, int cc)
|
||||
|
||||
INSTRUCTION( jp_cc_DA )
|
||||
{
|
||||
UINT16 dst = (fetch(cpustate) << 8) | fetch(cpustate);
|
||||
UINT16 dst = (fetch() << 8) | fetch();
|
||||
|
||||
/* if cc is true, then PC <- dst */
|
||||
if (check_condition_code(cpustate, opcode >> 4))
|
||||
if (check_condition_code(opcode >> 4))
|
||||
{
|
||||
jump(cpustate, dst);
|
||||
jump(dst);
|
||||
*cycles += 2;
|
||||
}
|
||||
}
|
||||
|
||||
INSTRUCTION( jr_cc_RA )
|
||||
{
|
||||
INT8 ra = (INT8)fetch(cpustate);
|
||||
UINT16 dst = cpustate->pc + ra;
|
||||
INT8 ra = (INT8)fetch();
|
||||
UINT16 dst = m_pc + ra;
|
||||
|
||||
/* if cc is true, then PC <- dst */
|
||||
if (check_condition_code(cpustate, opcode >> 4))
|
||||
if (check_condition_code(opcode >> 4))
|
||||
{
|
||||
jump(cpustate, dst);
|
||||
jump(dst);
|
||||
*cycles += 2;
|
||||
}
|
||||
}
|
||||
@ -595,10 +595,10 @@ INSTRUCTION( jr_cc_RA )
|
||||
BIT MANIPULATION INSTRUCTIONS
|
||||
***************************************************************************/
|
||||
|
||||
static void test_complement_under_mask(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
void z8_device::test_complement_under_mask(UINT8 dst, UINT8 src)
|
||||
{
|
||||
/* NOT(dst) AND src */
|
||||
UINT8 data = (register_read(cpustate, dst) ^ 0xff) & src;
|
||||
UINT8 data = (register_read(dst) ^ 0xff) & src;
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x80);
|
||||
@ -612,10 +612,10 @@ INSTRUCTION( tcm_IR2_R1 ) { mode_IR2_R1(test_complement_under_mask) }
|
||||
INSTRUCTION( tcm_R1_IM ) { mode_R1_IM(test_complement_under_mask) }
|
||||
INSTRUCTION( tcm_IR1_IM ) { mode_IR1_IM(test_complement_under_mask) }
|
||||
|
||||
static void test_under_mask(z8_state *cpustate, UINT8 dst, UINT8 src)
|
||||
void z8_device::test_under_mask(UINT8 dst, UINT8 src)
|
||||
{
|
||||
/* dst AND src */
|
||||
UINT8 data = register_read(cpustate, dst) & src;
|
||||
UINT8 data = register_read(dst) & src;
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x80);
|
||||
@ -633,10 +633,10 @@ INSTRUCTION( tm_IR1_IM ) { mode_IR1_IM(test_under_mask) }
|
||||
ROTATE AND SHIFT INSTRUCTIONS
|
||||
***************************************************************************/
|
||||
|
||||
static void rotate_left(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::rotate_left(UINT8 dst)
|
||||
{
|
||||
/* << */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT8 new_data = (data << 1) | BIT(data, 7);
|
||||
|
||||
set_flag_c(data & 0x80);
|
||||
@ -644,16 +644,16 @@ static void rotate_left(z8_state *cpustate, UINT8 dst)
|
||||
set_flag_s(new_data & 0x80);
|
||||
set_flag_v((data & 0x80) != (new_data & 0x80));
|
||||
|
||||
register_write(cpustate, dst, new_data);
|
||||
register_write(dst, new_data);
|
||||
}
|
||||
|
||||
INSTRUCTION( rl_R1 ) { mode_R1(rotate_left) }
|
||||
INSTRUCTION( rl_IR1 ) { mode_IR1(rotate_left) }
|
||||
|
||||
static void rotate_left_carry(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::rotate_left_carry(UINT8 dst)
|
||||
{
|
||||
/* << C */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT8 new_data = (data << 1) | flag(C);
|
||||
|
||||
set_flag_c(data & 0x80);
|
||||
@ -661,16 +661,16 @@ static void rotate_left_carry(z8_state *cpustate, UINT8 dst)
|
||||
set_flag_s(new_data & 0x80);
|
||||
set_flag_v((data & 0x80) != (new_data & 0x80));
|
||||
|
||||
register_write(cpustate, dst, new_data);
|
||||
register_write(dst, new_data);
|
||||
}
|
||||
|
||||
INSTRUCTION( rlc_R1 ) { mode_R1(rotate_left_carry) }
|
||||
INSTRUCTION( rlc_IR1 ) { mode_IR1(rotate_left_carry) }
|
||||
|
||||
static void rotate_right(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::rotate_right(UINT8 dst)
|
||||
{
|
||||
/* >> */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT8 new_data = ((data & 0x01) << 7) | (data >> 1);
|
||||
|
||||
set_flag_c(data & 0x01);
|
||||
@ -678,16 +678,16 @@ static void rotate_right(z8_state *cpustate, UINT8 dst)
|
||||
set_flag_s(new_data & 0x80);
|
||||
set_flag_v((data & 0x80) != (new_data & 0x80));
|
||||
|
||||
register_write(cpustate, dst, new_data);
|
||||
register_write(dst, new_data);
|
||||
}
|
||||
|
||||
INSTRUCTION( rr_R1 ) { mode_R1(rotate_right) }
|
||||
INSTRUCTION( rr_IR1 ) { mode_IR1(rotate_right) }
|
||||
|
||||
static void rotate_right_carry(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::rotate_right_carry(UINT8 dst)
|
||||
{
|
||||
/* >> C */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT8 new_data = (flag(C) << 7) | (data >> 1);
|
||||
|
||||
set_flag_c(data & 0x01);
|
||||
@ -695,16 +695,16 @@ static void rotate_right_carry(z8_state *cpustate, UINT8 dst)
|
||||
set_flag_s(new_data & 0x80);
|
||||
set_flag_v((data & 0x80) != (new_data & 0x80));
|
||||
|
||||
register_write(cpustate, dst, new_data);
|
||||
register_write(dst, new_data);
|
||||
}
|
||||
|
||||
INSTRUCTION( rrc_R1 ) { mode_R1(rotate_right_carry) }
|
||||
INSTRUCTION( rrc_IR1 ) { mode_IR1(rotate_right_carry) }
|
||||
|
||||
static void shift_right_arithmetic(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::shift_right_arithmetic(UINT8 dst)
|
||||
{
|
||||
/* */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
UINT8 new_data = (data & 0x80) | ((data >> 1) & 0x7f);
|
||||
|
||||
set_flag_c(data & 0x01);
|
||||
@ -712,18 +712,18 @@ static void shift_right_arithmetic(z8_state *cpustate, UINT8 dst)
|
||||
set_flag_s(new_data & 0x80);
|
||||
set_flag_v(0);
|
||||
|
||||
register_write(cpustate, dst, new_data);
|
||||
register_write(dst, new_data);
|
||||
}
|
||||
|
||||
INSTRUCTION( sra_R1 ) { mode_R1(shift_right_arithmetic) }
|
||||
INSTRUCTION( sra_IR1 ) { mode_IR1(shift_right_arithmetic) }
|
||||
|
||||
static void swap(z8_state *cpustate, UINT8 dst)
|
||||
void z8_device::swap(UINT8 dst)
|
||||
{
|
||||
/* dst(7-4) <-> dst(3-0) */
|
||||
UINT8 data = register_read(cpustate, dst);
|
||||
UINT8 data = register_read(dst);
|
||||
data = (data << 4) | (data >> 4);
|
||||
register_write(cpustate, dst, data);
|
||||
register_write(dst, data);
|
||||
|
||||
set_flag_z(data == 0);
|
||||
set_flag_s(data & 0x80);
|
||||
@ -737,10 +737,10 @@ INSTRUCTION( swap_IR1 ) { mode_IR1(swap) }
|
||||
CPU CONTROL INSTRUCTIONS
|
||||
***************************************************************************/
|
||||
|
||||
INSTRUCTION( ccf ) { cpustate->r[Z8_REGISTER_FLAGS] ^= Z8_FLAGS_C; }
|
||||
INSTRUCTION( di ) { cpustate->r[Z8_REGISTER_IMR] &= ~Z8_IMR_ENABLE; }
|
||||
INSTRUCTION( ei ) { cpustate->r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE; }
|
||||
INSTRUCTION( ccf ) { m_r[Z8_REGISTER_FLAGS] ^= Z8_FLAGS_C; }
|
||||
INSTRUCTION( di ) { m_r[Z8_REGISTER_IMR] &= ~Z8_IMR_ENABLE; }
|
||||
INSTRUCTION( ei ) { m_r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE; }
|
||||
INSTRUCTION( nop ) { /* no operation */ }
|
||||
INSTRUCTION( rcf ) { set_flag_c(0); }
|
||||
INSTRUCTION( scf ) { set_flag_c(1); }
|
||||
INSTRUCTION( srp_IM ) { cpustate->r[Z8_REGISTER_RP] = fetch(cpustate); }
|
||||
INSTRUCTION( srp_IM ) { m_r[Z8_REGISTER_RP] = fetch(); }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user