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First step in converting SH-2 to have separate internal devices. Fixed SH-1 num of address bits, removed extra read / write memory checks, added cache data array to main SH-2.

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(out-of-whatsnew) If anything regresses please let me know.
This commit is contained in:
angelosa 2015-07-07 20:52:24 +02:00
parent 9debe72975
commit 37950bd90f
5 changed files with 35 additions and 79 deletions
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86
src/emu/cpu/sh2/sh2.c
View File

@ -143,9 +143,13 @@ READ32_MEMBER(sh2_device::sh2_internal_a5)
static ADDRESS_MAP_START( sh2_internal_map, AS_PROGRAM, 32, sh2_device )
AM_RANGE(0x40000000, 0xbfffffff) AM_READ(sh2_internal_a5)
AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM // cache data array
AM_RANGE(0xe0000000, 0xffffffff) AM_READWRITE(sh2_internal_r, sh2_internal_w)
ADDRESS_MAP_END
static ADDRESS_MAP_START( sh7032_map, AS_PROGRAM, 32, sh2_device )
ADDRESS_MAP_END
sh2_device::sh2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, SH2, "SH-2", tag, owner, clock, "sh2", __FILE__)
@ -212,7 +216,9 @@ sh2_device::sh2_device(const machine_config &mconfig, device_type type, const ch
}
sh1_device::sh1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: sh2_device(mconfig, SH1, "SH-1", tag, owner, clock, "sh1", __FILE__, CPU_TYPE_SH1 )
: sh2_device(mconfig, SH1, "SH-1", tag, owner, clock, "sh1", __FILE__, CPU_TYPE_SH1 ),
m_program_config("program", ENDIANNESS_BIG, 32, 28, 0, ADDRESS_MAP_NAME(sh7032_map)),
m_decrypted_program_config("decrypted_opcodes", ENDIANNESS_BIG, 32, 28, 0)
{
}
@ -243,107 +249,33 @@ offs_t sh2_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *opro
UINT8 sh2_device::RB(offs_t A)
{
if (A >= 0xe0000000)
return sh2_internal_r(*m_internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);
if (A >= 0xc0000000)
return m_program->read_byte(A);
if (A >= 0x40000000)
return 0xa5;
return m_program->read_byte(A & AM);
}
UINT16 sh2_device::RW(offs_t A)
{
if (A >= 0xe0000000)
return sh2_internal_r(*m_internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);
if (A >= 0xc0000000)
return m_program->read_word(A);
if (A >= 0x40000000)
return 0xa5a5;
return m_program->read_word(A & AM);
}
UINT32 sh2_device::RL(offs_t A)
{
if (A >= 0xe0000000) /* I/O */
return sh2_internal_r(*m_internal, (A & 0x1fc)>>2, 0xffffffff);
if (A >= 0xc0000000) /* Cache Data Array */
return m_program->read_dword(A);
if (A >= 0x40000000) /* Cache Associative Purge Area */
return 0xa5a5a5a5;
{
/* 0x20000000 no Cache */
/* 0x00000000 read thru Cache if CE bit is 1 */
return m_program->read_dword(A & AM);
}
void sh2_device::WB(offs_t A, UINT8 V)
{
if (A >= 0xe0000000)
{
sh2_internal_w(*m_internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));
return;
}
if (A >= 0xc0000000)
{
m_program->write_byte(A,V);
return;
}
if (A >= 0x40000000)
return;
{
m_program->write_byte(A & AM,V);
}
void sh2_device::WW(offs_t A, UINT16 V)
{
if (A >= 0xe0000000)
{
sh2_internal_w(*m_internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));
return;
}
if (A >= 0xc0000000)
{
m_program->write_word(A,V);
return;
}
if (A >= 0x40000000)
return;
m_program->write_word(A & AM,V);
}
void sh2_device::WL(offs_t A, UINT32 V)
{
if (A >= 0xe0000000) /* I/O */
{
sh2_internal_w(*m_internal, (A & 0x1fc)>>2, V, 0xffffffff);
return;
}
if (A >= 0xc0000000) /* Cache Data Array */
{
m_program->write_dword(A,V);
return;
}
/* 0x60000000 Cache Address Data Array */
if (A >= 0x40000000) /* Cache Associative Purge Area */
return;
/* 0x20000000 no Cache */
/* 0x00000000 read thru Cache if CE bit is 1 */
m_program->write_dword(A & AM,V);

6
src/emu/cpu/sh2/sh2.h
View File

@ -500,6 +500,12 @@ class sh1_device : public sh2_device
public:
// construction/destruction
sh1_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
DECLARE_READ16_MEMBER(sh7032_r);
DECLARE_WRITE16_MEMBER(sh7032_w);
private:
UINT16 m_sh7032_regs[0x200];
address_space_config m_program_config, m_decrypted_program_config;
};

10
src/emu/cpu/sh2/sh2comn.c
View File

@ -888,3 +888,13 @@ void sh2_device::sh2_exception(const char *message, int irqline)
if(m_sh2_state->sleep_mode == 1) { m_sh2_state->sleep_mode = 2; }
}
READ16_MEMBER(sh1_device::sh7032_r)
{
return m_sh7032_regs[offset];
}
WRITE16_MEMBER(sh1_device::sh7032_w)
{
COMBINE_DATA(&m_sh7032_regs[offset]);
}

9
src/emu/dimemory.c
View File

@ -49,6 +49,15 @@ address_space_config::address_space_config()
{
}
/*!
@param name
@param endian CPU endianness
@param datawidth CPU parallelism bits
@param addrwidth address bits
@param addrshift
@param internal
@param defmap
*/
address_space_config::address_space_config(const char *name, endianness_t endian, UINT8 datawidth, UINT8 addrwidth, INT8 addrshift, address_map_constructor internal, address_map_constructor defmap)
: m_name(name),
m_endianness(endian),

3
src/mame/drivers/coolridr.c
View File

@ -3056,10 +3056,9 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( aquastge_submap, AS_PROGRAM, 32, coolridr_state )
AM_RANGE(0x05210000, 0x0521ffff) AM_RAM AM_SHARE("share3") /*Communication area RAM*/
//AM_RANGE(0x05200000, 0x0537ffff) AM_RAM
AM_RANGE(0x05200000, 0x0537ffff) AM_RAM
AM_RANGE(0x06000200, 0x06000207) AM_WRITENOP // program bug?
AM_RANGE(0x06100018, 0x0610001b) AM_READ_PORT("IN7")
AM_IMPORT_FROM(coolridr_submap)
ADDRESS_MAP_END