mirror of
https://github.com/holub/mame
synced 2025-06-02 10:59:52 +03:00
few bits of v53 stuff, start dynamic peripheral mapping, attempts to set up timers at least (nw)
This commit is contained in:
mamehaze
parent
075cb81413
commit
37bf50f2bc
@ -79,41 +79,220 @@ WRITE8_MEMBER(v53_base_device::WCY4_w)
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WRITE8_MEMBER(v53_base_device::SULA_w)
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{
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printf("v53: SULA_w %02x\n", data);
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m_SULA = data;
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install_peripheral_io();
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}
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WRITE8_MEMBER(v53_base_device::TULA_w)
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{
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printf("v53: TULA_w %02x\n", data);
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m_TULA = data;
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install_peripheral_io();
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}
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WRITE8_MEMBER(v53_base_device::IULA_w)
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{
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printf("v53: IULA_w %02x\n", data);
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m_IULA = data;
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install_peripheral_io();
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}
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WRITE8_MEMBER(v53_base_device::DULA_w)
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{
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printf("v53: DULA_w %02x\n", data);
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m_DULA = data;
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install_peripheral_io();
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}
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WRITE8_MEMBER(v53_base_device::OPHA_w)
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{
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printf("v53: OPHA_w %02x\n", data);
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m_OPHA = data;
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install_peripheral_io();
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}
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WRITE8_MEMBER(v53_base_device::OPSEL_w)
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{
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printf("v53: OPSEL_w %02x\n", data);
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m_OPSEL = data;
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install_peripheral_io();
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}
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WRITE8_MEMBER(v53_base_device::SCTL_w)
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{
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// bit 7: unused
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// bit 6: unused
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// bit 5: unused
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// bit 4: SCU input clock source
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// bit 3: uPD71037 DMA mode - Carry A20
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// bit 2: uPD71037 DMA mode - Carry A16
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// bit 1: uPD71037 DMA mode enable (otherwise in uPD71071 mode)
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// bit 0: Onboard pripheral I/O maps to 8-bit boundaries? (otherwise 16-bit)
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printf("v53: SCTL_w %02x\n", data);
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m_SCTL = data;
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install_peripheral_io();
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}
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/*
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m_WCY0 = 0x07;
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m_WCY1 = 0x77;
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m_WCY2 = 0x77;
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m_WCY3 = 0x77;
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m_WCY4 = 0x77;
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m_WMB0 = 0x77;
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m_WMB1 = 0x77;
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m_WAC = 0x00;
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m_TCKS = 0x00;
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m_RFC = 0x80;
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m_SBCR = 0x00;
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m_BRC = 0x00;
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// SCU
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m_SMD = 0x4b;
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m_SCM = 0x00;
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m_SIMK = 0x03;
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m_SST = 0x04;
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// DMA
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m_DCH = 0x01;
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m_DMD = 0x00;
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m_DCC = 0x0000;
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m_DST = 0x00;
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m_DMK = 0x0f;
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*/
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void v53_base_device::device_reset()
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{
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nec_common_device::device_reset();
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m_SCTL = 0x00;
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m_OPSEL= 0x00;
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// peripheral addresses
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m_SULA = 0x00;
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m_TULA = 0x00;
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m_IULA = 0x00;
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m_DULA = 0x00;
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m_OPHA = 0x00;
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}
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void v53_base_device::device_start()
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{
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nec_common_device::device_start();
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}
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void v53_base_device::install_peripheral_io()
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{
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// unmap everything in I/O space up to the fixed position registers (we avoid overwriting them, it isn't a valid config)
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space(AS_IO).unmap_readwrite(0x0000, 0xfeff);
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// IOAG determines if the handlers used 8-bit or 16-bit access
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// the hng64.c games first set everything up in 8-bit mode, then
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// do the procedure again in 16-bit mode before using them?!
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int IOAG = m_SCTL & 1;
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if (m_OPSEL & 0x01) // DMA Unit available
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{
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if (IOAG) // 8-bit
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{
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}
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else
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{
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}
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}
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if (m_OPSEL & 0x02) // Interupt Control Unit available
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{
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if (IOAG) // 8-bit
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{
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}
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else
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{
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}
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}
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if (m_OPSEL & 0x04) // Timer Control Unit available
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{
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UINT16 base = (m_OPHA << 8) | m_TULA;
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printf("installing TCU to %04x\n", base);
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if (IOAG) // 8-bit
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{
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}
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else
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{
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space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8_delegate(FUNC(v53_base_device::tmu_tst0_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct0_w), this), 0x00ff);
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space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8_delegate(FUNC(v53_base_device::tmu_tst1_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct1_w), this), 0x00ff);
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space(AS_IO).install_readwrite_handler(base+0x04, base+0x05, read8_delegate(FUNC(v53_base_device::tmu_tst2_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct2_w), this), 0x00ff);
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space(AS_IO).install_write_handler(base+0x06, base+0x07, write8_delegate(FUNC(v53_base_device::tmu_tmd_w), this), 0x00ff);
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}
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}
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if (m_OPSEL & 0x08) // Serial Control Unit available
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{
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if (IOAG) // 8-bit
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{
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}
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else
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{
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}
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}
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}
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/*** TCU ***/
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READ8_MEMBER(v53_base_device::tmu_tst0_r)
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{
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printf("v53: tmu_tst0_r\n");
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return 0;
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}
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WRITE8_MEMBER(v53_base_device::tmu_tct0_w)
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{
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printf("v53: tmu_tct0_w %02x\n", data);
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}
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READ8_MEMBER(v53_base_device::tmu_tst1_r)
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{
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printf("v53: tmu_tst1_r\n");
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return 0;
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}
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WRITE8_MEMBER(v53_base_device::tmu_tct1_w)
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{
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printf("v53: tmu_tct1_w %02x\n", data);
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}
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READ8_MEMBER(v53_base_device::tmu_tst2_r)
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{
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printf("v53: tmu_tst2_r\n");
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return 0;
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}
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WRITE8_MEMBER(v53_base_device::tmu_tct2_w)
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{
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printf("v53: tmu_tct2_w %02x\n", data);
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}
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WRITE8_MEMBER(v53_base_device::tmu_tmd_w)
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{
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printf("v53: tmu_tmd_w %02x\n", data);
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}
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/* General stuff */
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static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device )
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AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0
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AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1
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AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 // uPD71037 DMA mode bank selection register
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AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA)
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// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2
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// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3
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// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4
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@ -121,28 +300,28 @@ static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device )
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// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6
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// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7
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// AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8
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AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9
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AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea
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AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb
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AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec
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AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed
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AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 // baud rate counter (used for serial peripheral)
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AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea // waitstate control
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AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb // waitstate control
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AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec // waitstate control
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AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed // waitstate control
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// AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee
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// AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef
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AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0
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AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1
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AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2
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AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( WMB1_w, 0xff00) // 0xfff3
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AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4
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AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5
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AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6
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AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 // timer clocks
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AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 // internal clock divider, halt behavior etc.
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AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 // ram refresh control
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AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( WMB1_w, 0xff00) // 0xfff3 // waitstate control
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AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 // waitstate control
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AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 // waitstate control
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AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 // waitstate control
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// AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7
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AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8
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AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9
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AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa
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AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( DULA_w, 0xff00) // 0xfffb
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AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc
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AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd
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AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe
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AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 // peripheral mapping
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AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 // peripheral mapping
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AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa // peripheral mapping
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AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( DULA_w, 0xff00) // 0xfffb // peripheral mapping
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AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc // peripheral mapping (upper bits, common)
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AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd // peripheral enabling
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AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe // peripheral configuration (& byte / word mapping)
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// AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff
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ADDRESS_MAP_END
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@ -30,8 +30,28 @@ public:
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DECLARE_WRITE8_MEMBER(OPSEL_w);
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DECLARE_WRITE8_MEMBER(SCTL_w);
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const address_space_config m_io_space_config;
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UINT8 m_SCTL;
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UINT8 m_OPSEL;
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UINT8 m_SULA;
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UINT8 m_TULA;
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UINT8 m_IULA;
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UINT8 m_DULA;
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UINT8 m_OPHA;
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// TMU
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DECLARE_READ8_MEMBER(tmu_tst0_r);
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DECLARE_WRITE8_MEMBER(tmu_tct0_w);
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DECLARE_READ8_MEMBER(tmu_tst1_r);
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DECLARE_WRITE8_MEMBER(tmu_tct1_w);
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DECLARE_READ8_MEMBER(tmu_tst2_r);
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DECLARE_WRITE8_MEMBER(tmu_tct2_w);
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DECLARE_WRITE8_MEMBER(tmu_tmd_w);
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void install_peripheral_io();
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const address_space_config m_io_space_config;
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const address_space_config *memory_space_config(address_spacenum spacenum) const
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{
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switch (spacenum)
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@ -40,6 +60,11 @@ public:
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default: return nec_common_device::memory_space_config(spacenum);
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}
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}
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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};
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@ -12,7 +12,11 @@ sams64_2 (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.14. (#)Copyrig
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fatfurwa (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.14. (#)Copyright (C) SNK Corp. 1997,1998 All rights reserved
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buriki (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.15. (#)Copyright (C) SNK Corp. 1997,1998 All rights reserved
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the earlier revisions appear to have 2 banks of code (there are vectors at the end of the 0x1e0000 block and the 0x1f0000 block)
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The earlier revisions appear to have 2 banks of code (there are vectors at the end of the 0x1e0000 block and the 0x1f0000 block)
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Those first two revisions also spam the entire range of I/O ports with values several times on startup causing some unexpected
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writes to the V53 internal registers. The important ones are reinitialized after this however, I'm guessing this is harmless
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on real hardware, as the code flow seems to be correct.
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data structures look very similar between all of them
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