mirror of
https://github.com/holub/mame
synced 2025-04-22 08:22:15 +03:00
sun3 updates: [R. Belmont]
- Split sun3 and sun3x archiectures, they're different enough - Preliminary sun3 MMU implementation, passes POST but dies setting up initial mappings
This commit is contained in:
arbee
parent
8a3c3d174c
commit
37c1c94eb5
@ -2612,6 +2612,7 @@ files {
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MAME_DIR .. "src/mame/drivers/sun1.cpp",
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MAME_DIR .. "src/mame/drivers/sun2.cpp",
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MAME_DIR .. "src/mame/drivers/sun3.cpp",
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MAME_DIR .. "src/mame/drivers/sun3x.cpp",
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MAME_DIR .. "src/mame/drivers/sun4.cpp",
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}
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File diff suppressed because it is too large
Load Diff
684
src/mame/drivers/sun3x.cpp
Normal file
684
src/mame/drivers/sun3x.cpp
Normal file
@ -0,0 +1,684 @@
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// license:BSD-3-Clause
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// copyright-holders:Miodrag Milanovic, R. Belmont
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/***************************************************************************
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sun3.c: preliminary driver for Sun 3x models.
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status: 3/80 POSTs, 3/460 needs its unique RTC chip (also used by non-3x Sun 3s).
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TODO:
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- Z8530 SCC needs to actually speak serial so we can hook up the mouse and keyboard.
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- Improve interrupt controller emulation.
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- Figure out how the IOMMU works.
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- Intersil 7170 device for 3/460 and 3/480 (they use the same PROMs).
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- Sun custom MMU for original Sun 3 models.
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- AM7990 LANCE chip support for everyone.
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- Figure out how the parallel printer port maps to Centronics and make it so.
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- Much more...
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Sun-3x Models
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------------
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3/80
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Processor(s): 68030 @ 20MHz, 68882 @ 20MHz, 68030 on-chip
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MMU, 3 MIPS, 0.16 MFLOPS
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CPU: 501-1401/1650
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Chassis type: square pizza box
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Bus: P4 connector (not same as P4 on 3/60)
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Memory: 16M or 40M physical, 4G virtual, 100ns cycle
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Notes: Similar packaging to SparcStation 1. Parallel
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port, SCSI port, AUI Ethernet, 1.44M 3.5" floppy
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(720K on early units?). No onboard framebuffer.
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Code-named "Hydra". Type-4 keyboard and Sun-4
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mouse, plugged together and into the machine
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with a small DIN plug. 1M x 9 30-pin 100ns
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SIMMs. Boot ROM versions 3.0.2 and later allow
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using 4M SIMMs in some slots for up to 40M (see
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Misc Q&A #15).
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3/460
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Processor(s): 68030 @ 33 MHz, 68882, 68030 on-chip MMU,
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7 MIPS, 0.6 MFLOPS
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CPU: 501-1299/1550
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Bus: VME
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Memory: 128M physical with ECC, 4G/process virtual,
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64K cache, 80ns cycle
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Notes: A 3/260 upgraded with a 3/4xx CPU board. Uses
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original 3/2xx memory boards.
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3/470
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Processor(s): 68030 @ 33 MHz, 68882, 68030 on-chip MMU,
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7 MIPS, 0.6 MFLOPS
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CPU: 501-1299/1550
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Chassis type: deskside
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Bus: VME
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Memory: 128M physical with ECC, 4G/process virtual,
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64K cache, 80ns cycle
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Notes: Rare. Code-named "Pegasus". 8M standard, uses
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same memory boards as 3/2xx.
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3/480
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Processor(s): 68030 @ 33 MHz, 68882, 68030 on-chip MMU,
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7 MIPS, 0.6 MFLOPS
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CPU: 501-1299/1550
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Chassis type: rackmount
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Bus: VME
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Memory: 128M physical with ECC, 4G/process virtual,
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64K cache, 80ns cycle
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Notes: Rare. Code-named "Pegasus". 8M standard, uses
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same memory boards as 3/2xx.
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Sun3X notes from NetBSD and Linux:
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RAM_END 0x40000000
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P4DAC 0x50200000
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VIDEO_P4ID 0x50300000
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BW2_ADDR 0x50400000
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ENA_PLANE 0x50600000
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FPA_ADDR 0x5c000000
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IOMMU 0x60000000
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ENABLEREG 0x61000000
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BUSERRREG 0x61000400
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DIAGREG 0x61000800
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IDPROM1 0x61000c00 (3/470)
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MEMREG 0x61001000
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INTERREG 0x61001400
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SCC1 0x62000000 (keyboard/mouse)
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SCC2 0x62002000 (serial console)
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EEPROM 0x64000000
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IDPROM2 0x640007d8 (3/80)
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CLOCK2 0x640007f8 (3/80 Mostek 48T02)
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CLOCK1 0x64002000 (3/470 Intersil 7170)
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INTELETH 0x65000000
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LANCEETH 0x65002000
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EMULEXSCSI 0x66000000 (3/80 5394)
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EMULLEXDMA 0x66001000 (3/80)
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PCACHETAG 0x68000000
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ECCPARREG 0x6a1e0000
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IOCTAGS 0x6c000000
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IOCFLUSH 0x6d000000
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FDC 0x6e000000 (3/80 Intel 82077)
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FDC_CNTRL 0x6e000400
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FDC_VEC 0x6e000800
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PRINTER 0x6f00003c (3/80)
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The Sun3x System Enable Register controls the function of a few
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on-board devices and general system operation. It is cleared when
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the system is reset.
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15 0
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+---+---+---+---+---+---+---+---+---+---+---+---+---+---.---.---+
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|BT |FPP|DMA| 0 |VID|RES|FPA|DIA| 0 |CCH|IOC|LBK|DCH| UNUSED |
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+---+---+---+---+---+---+---+---+---+---+---+---+---+---.---.---+
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Where: DCH = debug mode for system cache
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LBK = VME loopback
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IOC = I/O cache enable
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CCH = system cache enable
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DIA = diagnostic switch
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FPA = enable floating-point accelerator
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RES = 0 for hi-res, 1 for low res
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VID = enable video display
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DMA = enable system DVMA
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FPP = enable 68881/2 FPU
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BT = 0 for boot state, 1 for normal state
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bad '030 MMU mapping: L fef82000 -> P 00000000
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****************************************************************************/
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#include "emu.h"
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#include "cpu/m68000/m68000.h"
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#include "machine/timekpr.h"
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#include "machine/z80scc.h"
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#include "bus/scsi/scsi.h"
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#include "bus/scsi/scsihd.h"
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#include "bus/scsi/scsicd.h"
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#include "machine/ncr539x.h"
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#include "machine/upd765.h"
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#include "formats/pc_dsk.h"
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#include "formats/mfi_dsk.h"
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#include "bus/rs232/rs232.h"
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#define TIMEKEEPER_TAG "timekpr"
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#define SCC1_TAG "scc1"
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#define SCC2_TAG "scc2"
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#define ESP_TAG "esp"
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#define FDC_TAG "fdc"
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#define RS232A_TAG "rs232a"
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#define RS232B_TAG "rs232b"
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class sun3x_state : public driver_device
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{
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public:
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sun3x_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_scc1(*this, SCC1_TAG),
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m_scc2(*this, SCC2_TAG),
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m_fdc(*this, FDC_TAG),
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m_p_ram(*this, "p_ram"),
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m_bw2_vram(*this, "bw2_vram")
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{ }
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required_device<cpu_device> m_maincpu;
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required_device<z80scc_device> m_scc1;
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required_device<z80scc_device> m_scc2;
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optional_device<n82077aa_device> m_fdc;
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virtual void machine_reset() override;
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required_shared_ptr<UINT32> m_p_ram;
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optional_shared_ptr<UINT32> m_bw2_vram;
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DECLARE_READ32_MEMBER(enable_r);
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DECLARE_WRITE32_MEMBER(enable_w);
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DECLARE_READ32_MEMBER(buserr_r);
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DECLARE_WRITE32_MEMBER(buserr_w);
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DECLARE_READ32_MEMBER(diag_r);
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DECLARE_WRITE32_MEMBER(diag_w);
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DECLARE_READ32_MEMBER(printer_r);
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DECLARE_WRITE32_MEMBER(printer_w);
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DECLARE_READ32_MEMBER(iommu_r);
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DECLARE_WRITE32_MEMBER(iommu_w);
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DECLARE_READ32_MEMBER(irqctrl_r);
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DECLARE_WRITE32_MEMBER(irqctrl_w);
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DECLARE_READ32_MEMBER(memreg_r);
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DECLARE_WRITE32_MEMBER(memreg_w);
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DECLARE_READ32_MEMBER(memrerraddr_r);
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DECLARE_WRITE32_MEMBER(memrerraddr_w);
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DECLARE_READ32_MEMBER(fdc_control_r);
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DECLARE_WRITE32_MEMBER(fdc_control_w);
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DECLARE_READ32_MEMBER(cause_buserr_r);
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DECLARE_WRITE32_MEMBER(cause_buserr_w);
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DECLARE_WRITE32_MEMBER(ramwrite_w);
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DECLARE_READ32_MEMBER(fpa_r);
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DECLARE_READ32_MEMBER(p4id_r);
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DECLARE_FLOPPY_FORMATS( floppy_formats );
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TIMER_DEVICE_CALLBACK_MEMBER(sun380_timer);
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UINT32 bw2_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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private:
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UINT32 m_enable, m_buserr, m_diag, m_printer, m_irqctrl, m_memreg, m_memerraddr;
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UINT32 m_iommu[0x800];
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bool m_bInBusErr;
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};
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static ADDRESS_MAP_START(sun3_80_mem, AS_PROGRAM, 32, sun3x_state)
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AM_RANGE(0x00000000, 0x03ffffff) AM_RAM AM_SHARE("p_ram") AM_WRITE(ramwrite_w)
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AM_RANGE(0x40000000, 0x40000003) AM_READWRITE(cause_buserr_r, cause_buserr_w)
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AM_RANGE(0x50300000, 0x50300003) AM_READ(p4id_r)
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AM_RANGE(0x50400000, 0x504fffff) AM_RAM AM_SHARE("bw2_vram")
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AM_RANGE(0x60000000, 0x60001fff) AM_READWRITE(iommu_r, iommu_w)
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AM_RANGE(0x61000000, 0x61000003) AM_READWRITE(enable_r, enable_w)
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AM_RANGE(0x61000400, 0x61000403) AM_READWRITE(buserr_r, buserr_w)
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AM_RANGE(0x61000800, 0x61000803) AM_READWRITE(diag_r, diag_w)
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AM_RANGE(0x61001000, 0x61001003) AM_READWRITE(memreg_r, memreg_w)
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AM_RANGE(0x61001004, 0x61001007) AM_READWRITE(memrerraddr_r, memrerraddr_w)
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AM_RANGE(0x61001400, 0x61001403) AM_READWRITE(irqctrl_r, irqctrl_w)
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AM_RANGE(0x62000000, 0x6200000f) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
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AM_RANGE(0x62002000, 0x6200200f) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
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AM_RANGE(0x63000000, 0x6301ffff) AM_ROM AM_REGION("user1",0)
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AM_RANGE(0x64000000, 0x640007ff) AM_DEVREADWRITE8(TIMEKEEPER_TAG, timekeeper_device, read, write, 0xffffffff)
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AM_RANGE(0x66000000, 0x6600003f) AM_DEVREADWRITE8(ESP_TAG, ncr539x_device, read, write, 0xff000000)
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AM_RANGE(0x6e000000, 0x6e000007) AM_DEVICE8(FDC_TAG, n82077aa_device, map, 0xffffffff)
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AM_RANGE(0x6e000400, 0x6e000403) AM_READWRITE(fdc_control_r, fdc_control_w)
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AM_RANGE(0x6f00003c, 0x6f00003f) AM_READWRITE(printer_r, printer_w)
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AM_RANGE(0xfefe0000, 0xfefeffff) AM_ROM AM_REGION("user1",0)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(sun3_460_mem, AS_PROGRAM, 32, sun3x_state)
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AM_RANGE(0x00000000, 0x03ffffff) AM_RAM AM_SHARE("p_ram") AM_WRITE(ramwrite_w)
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AM_RANGE(0x09000000, 0x09000003) AM_READWRITE(cause_buserr_r, cause_buserr_w)
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AM_RANGE(0x50300000, 0x50300003) AM_READ(p4id_r)
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AM_RANGE(0x50400000, 0x504fffff) AM_RAM AM_SHARE("bw2_vram")
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AM_RANGE(0x5c000f14, 0x5c000f17) AM_READ(fpa_r)
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AM_RANGE(0x60000000, 0x60001fff) AM_READWRITE(iommu_r, iommu_w)
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AM_RANGE(0x61000000, 0x61000003) AM_READWRITE(enable_r, enable_w)
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AM_RANGE(0x61000400, 0x61000403) AM_READWRITE(buserr_r, buserr_w)
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AM_RANGE(0x61000800, 0x61000803) AM_READWRITE(diag_r, diag_w)
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AM_RANGE(0x61001000, 0x61001003) AM_READWRITE(memreg_r, memreg_w)
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AM_RANGE(0x61001004, 0x61001007) AM_READWRITE(memrerraddr_r, memrerraddr_w)
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AM_RANGE(0x61001400, 0x61001403) AM_READWRITE(irqctrl_r, irqctrl_w)
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AM_RANGE(0x62000000, 0x6200000f) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
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AM_RANGE(0x62002000, 0x6200200f) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
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AM_RANGE(0x63000000, 0x6301ffff) AM_ROM AM_REGION("user1",0)
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AM_RANGE(0x6f00003c, 0x6f00003f) AM_READWRITE(printer_r, printer_w)
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AM_RANGE(0xfefe0000, 0xfefeffff) AM_ROM AM_REGION("user1",0)
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ADDRESS_MAP_END
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READ32_MEMBER( sun3x_state::p4id_r )
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{
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return (1<<24); // 0 = hires bw2 1600x1280, 1 = bw2 1152x900, 0x45 is "Ibis" color, blt 0x68 is "Lego" color
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}
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WRITE32_MEMBER( sun3x_state::fdc_control_w )
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{
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logerror("FDC write %02x (%08x)\n", data >> 24, space.device().safe_pc());
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}
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READ32_MEMBER( sun3x_state::fdc_control_r )
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{
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// Type of floppy present
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// 0 = no floppy in drive
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// 1 = ed
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// 2 = hd
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// 3 = dd
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if(m_fdc) {
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floppy_image_device *fdev = machine().device<floppy_connector>(":fdc:0")->get_device();
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if(fdev->exists()) {
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UINT32 variant = fdev->get_variant();
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switch(variant) {
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case floppy_image::SSSD:
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case floppy_image::SSDD:
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case floppy_image::DSDD:
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return 3 << 24;
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case floppy_image::DSHD:
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return 2 << 24;
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case floppy_image::DSED:
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return 1 << 24;
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}
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}
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}
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return 0 << 24;
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}
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WRITE32_MEMBER(sun3x_state::ramwrite_w)
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{
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UINT32 *pRAM = (UINT32 *)m_p_ram.target();
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if (((m_memreg & 0xf0000000) == 0x70000000) &&
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(m_irqctrl & 0x01000000) &&
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!(m_bInBusErr))
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{
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m_memerraddr = offset<<2;
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// low 4 bits of memreg are the byte lane(s) involved, negative logic
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m_memreg |= 0x0f;
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switch (mem_mask)
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{
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case 0xff000000:
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m_memreg &= ~0x08;
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break;
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case 0x00ff0000:
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m_memerraddr += 1;
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m_memreg &= ~0x04;
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break;
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case 0x0000ff00:
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m_memerraddr += 2;
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m_memreg &= ~0x02;
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break;
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case 0x000000ff:
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m_memerraddr += 3;
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m_memreg &= ~0x01;
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break;
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case 0x0000ffff:
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m_memerraddr += 2;
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m_memreg &= ~0x03;
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break;
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case 0xffff0000:
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m_memreg &= ~0x0c;
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break;
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case 0xffffffff: // no address adjust, show all 4 lanes as problematic
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break;
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}
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m_bInBusErr = true; // prevent recursion
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m_maincpu->set_input_line_and_vector(M68K_IRQ_7, ASSERT_LINE, 2);
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}
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COMBINE_DATA(&pRAM[offset]);
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}
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READ32_MEMBER(sun3x_state::enable_r)
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{
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return m_enable;
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}
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WRITE32_MEMBER(sun3x_state::enable_w)
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{
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// printf("sun3x: %08x to enable (mask %08x)\n", data, mem_mask);
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COMBINE_DATA(&m_enable);
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}
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READ32_MEMBER(sun3x_state::buserr_r)
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{
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UINT32 rv = m_buserr;
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m_buserr = 0;
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return rv;
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}
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WRITE32_MEMBER(sun3x_state::buserr_w)
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{
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// printf("sun3x: %08x to buserr (mask %08x)\n", data, mem_mask);
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COMBINE_DATA(&m_buserr);
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}
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READ32_MEMBER(sun3x_state::diag_r)
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{
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return m_diag;
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}
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WRITE32_MEMBER(sun3x_state::diag_w)
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{
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// printf("sun3x: %08x to diag (mask %08x)\n", data, mem_mask);
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COMBINE_DATA(&m_diag);
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}
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READ32_MEMBER(sun3x_state::printer_r)
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{
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return m_printer;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(sun3x_state::printer_w)
|
||||
{
|
||||
// printf("sun3x: %08x to printer (mask %08x)\n", data, mem_mask);
|
||||
COMBINE_DATA(&m_printer);
|
||||
}
|
||||
|
||||
READ32_MEMBER(sun3x_state::irqctrl_r)
|
||||
{
|
||||
return m_irqctrl;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(sun3x_state::irqctrl_w)
|
||||
{
|
||||
// printf("sun3x: %08x to interrupt control (mask %08x)\n", data, mem_mask);
|
||||
COMBINE_DATA(&m_irqctrl);
|
||||
|
||||
if (data & 0x01000000)
|
||||
{
|
||||
if (data & 0x02000000)
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_1, ASSERT_LINE);
|
||||
}
|
||||
if (data & 0x04000000)
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_2, ASSERT_LINE);
|
||||
}
|
||||
if (data & 0x08000000)
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_3, ASSERT_LINE);
|
||||
}
|
||||
if (!(data & 0x80000000))
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
else // master enable clear, clear all interrupts
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
|
||||
m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
|
||||
m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
|
||||
m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
|
||||
m_maincpu->set_input_line(M68K_IRQ_5, CLEAR_LINE);
|
||||
m_maincpu->set_input_line(M68K_IRQ_6, CLEAR_LINE);
|
||||
m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER(sun3x_state::memreg_r)
|
||||
{
|
||||
return m_memreg;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(sun3x_state::memreg_w)
|
||||
{
|
||||
// printf("sun3x: %08x to memory control (mask %08x)\n", data, mem_mask);
|
||||
COMBINE_DATA(&m_memreg);
|
||||
}
|
||||
|
||||
READ32_MEMBER(sun3x_state::memrerraddr_r)
|
||||
{
|
||||
m_bInBusErr = false;
|
||||
m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
|
||||
return m_memerraddr;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(sun3x_state::memrerraddr_w)
|
||||
{
|
||||
// printf("sun3x: %08x to memory error address (mask %08x)\n", data, mem_mask);
|
||||
COMBINE_DATA(&m_memerraddr);
|
||||
}
|
||||
|
||||
READ32_MEMBER(sun3x_state::iommu_r)
|
||||
{
|
||||
return m_iommu[offset];
|
||||
}
|
||||
|
||||
// IOMMU entry defs:
|
||||
// address mask: 0x03ffe000
|
||||
// cache inhibit: 0x00000040
|
||||
// full block: 0x00000020
|
||||
// modified: 0x00000010
|
||||
// used: 0x00000008
|
||||
// write prot: 0x00000004
|
||||
// bad: 0x00000002
|
||||
// valid: 0x00000001
|
||||
WRITE32_MEMBER(sun3x_state::iommu_w)
|
||||
{
|
||||
COMBINE_DATA(&m_iommu[offset]);
|
||||
}
|
||||
|
||||
READ32_MEMBER(sun3x_state::fpa_r)
|
||||
{
|
||||
m_buserr |= 0x04000000;
|
||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
|
||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
READ32_MEMBER(sun3x_state::cause_buserr_r)
|
||||
{
|
||||
m_buserr |= 0x20000000;
|
||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
|
||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(sun3x_state::cause_buserr_w)
|
||||
{
|
||||
m_buserr |= 0x20000000;
|
||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
|
||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
|
||||
}
|
||||
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(sun3x_state::sun380_timer)
|
||||
{
|
||||
if ((m_irqctrl & 0x81000000) == 0x81000000)
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
|
||||
m_maincpu->set_input_line(M68K_IRQ_7, ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
UINT32 sun3x_state::bw2_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
UINT32 *scanline;
|
||||
int x, y;
|
||||
UINT8 pixels;
|
||||
static const UINT32 palette[2] = { 0, 0xffffff };
|
||||
UINT8 *m_vram = (UINT8 *)m_bw2_vram.target();
|
||||
|
||||
for (y = 0; y < 900; y++)
|
||||
{
|
||||
scanline = &bitmap.pix32(y);
|
||||
for (x = 0; x < 1152/8; x++)
|
||||
{
|
||||
pixels = m_vram[(y * (1152/8)) + (BYTE4_XOR_BE(x))];
|
||||
|
||||
*scanline++ = palette[(pixels>>7)&1];
|
||||
*scanline++ = palette[(pixels>>6)&1];
|
||||
*scanline++ = palette[(pixels>>5)&1];
|
||||
*scanline++ = palette[(pixels>>4)&1];
|
||||
*scanline++ = palette[(pixels>>3)&1];
|
||||
*scanline++ = palette[(pixels>>2)&1];
|
||||
*scanline++ = palette[(pixels>>1)&1];
|
||||
*scanline++ = palette[(pixels&1)];
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Input ports */
|
||||
static INPUT_PORTS_START( sun3x )
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
void sun3x_state::machine_reset()
|
||||
{
|
||||
UINT8* user1 = memregion("user1")->base();
|
||||
|
||||
memcpy((UINT8*)m_p_ram.target(),user1,0x10000);
|
||||
|
||||
m_maincpu->reset();
|
||||
|
||||
memset(m_iommu, 0, sizeof(m_iommu));
|
||||
|
||||
m_enable = 0;
|
||||
m_buserr = 0;
|
||||
m_diag = 0;
|
||||
m_printer = 0;
|
||||
m_irqctrl = 0;
|
||||
m_memreg = 0;
|
||||
m_memerraddr = 0;
|
||||
m_bInBusErr = false;
|
||||
}
|
||||
|
||||
FLOPPY_FORMATS_MEMBER( sun3x_state::floppy_formats )
|
||||
FLOPPY_PC_FORMAT
|
||||
FLOPPY_FORMATS_END
|
||||
|
||||
static SLOT_INTERFACE_START( sun_floppies )
|
||||
SLOT_INTERFACE( "35hd", FLOPPY_35_HD )
|
||||
SLOT_INTERFACE_END
|
||||
|
||||
static MACHINE_CONFIG_START( sun3_80, sun3x_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M68030, 20000000)
|
||||
MCFG_CPU_PROGRAM_MAP(sun3_80_mem)
|
||||
|
||||
MCFG_M48T02_ADD(TIMEKEEPER_TAG)
|
||||
|
||||
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
|
||||
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
|
||||
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
|
||||
MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE(RS232B_TAG, rs232_port_device, write_txd))
|
||||
|
||||
MCFG_RS232_PORT_ADD(RS232A_TAG, default_rs232_devices, nullptr)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, rxa_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, dcda_w))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, ctsa_w))
|
||||
|
||||
MCFG_RS232_PORT_ADD(RS232B_TAG, default_rs232_devices, nullptr)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, rxb_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, dcdb_w))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, ctsb_w))
|
||||
|
||||
MCFG_DEVICE_ADD("scsi", SCSI_PORT, 0)
|
||||
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE1, "harddisk", SCSIHD, SCSI_ID_6)
|
||||
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE2, "harddisk", SCSIHD, SCSI_ID_5)
|
||||
|
||||
MCFG_DEVICE_ADD(ESP_TAG, NCR539X, 20000000/2)
|
||||
MCFG_LEGACY_SCSI_PORT("scsi")
|
||||
|
||||
MCFG_N82077AA_ADD("fdc", n82077aa_device::MODE_PS2)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:0", sun_floppies, "35hd", sun3x_state::floppy_formats)
|
||||
|
||||
// the timekeeper has no interrupt output, so 3/80 includes a dedicated timer circuit
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3x_state, sun380_timer, attotime::from_hz(100))
|
||||
|
||||
MCFG_SCREEN_ADD("bwtwo", RASTER)
|
||||
MCFG_SCREEN_UPDATE_DRIVER(sun3x_state, bw2_update)
|
||||
MCFG_SCREEN_SIZE(1152,900)
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
|
||||
MCFG_SCREEN_REFRESH_RATE(72)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_START( sun3_460, sun3x_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M68030, 33000000)
|
||||
MCFG_CPU_PROGRAM_MAP(sun3_460_mem)
|
||||
|
||||
MCFG_M48T02_ADD(TIMEKEEPER_TAG)
|
||||
|
||||
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
|
||||
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
|
||||
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
|
||||
MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE(RS232B_TAG, rs232_port_device, write_txd))
|
||||
|
||||
MCFG_RS232_PORT_ADD(RS232A_TAG, default_rs232_devices, nullptr)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, rxa_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, dcda_w))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, ctsa_w))
|
||||
|
||||
MCFG_RS232_PORT_ADD(RS232B_TAG, default_rs232_devices, nullptr)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, rxb_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, dcdb_w))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, ctsb_w))
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
/* ROM definition */
|
||||
|
||||
ROM_START( sun3_80 )
|
||||
ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF )
|
||||
/*
|
||||
Sun 3/80 V1.0 Bootprom
|
||||
Sun 3/80 V2.2 Bootprom
|
||||
Sun 3/80 V2.3 Bootprom
|
||||
Sun 3/80 V2.9.2 Bootprom
|
||||
Sun 3/80 V3.0 Bootprom
|
||||
Sun 3/80 V3.0.2 Bootprom
|
||||
Sun 3/80 V3.0.3 Bootprom
|
||||
*/
|
||||
ROM_SYSTEM_BIOS(0, "rev303", "Rev 3.0.3")
|
||||
ROMX_LOAD( "sun3_80_v3.0.3", 0x0000, 0x20000, CRC(8f983115) SHA1(e4be2dcbb29fc5c60ed9d838ab241c634fdd24e5), ROM_BIOS(1))
|
||||
ROM_SYSTEM_BIOS(1, "rev302", "Rev 3.0.2")
|
||||
ROMX_LOAD( "sun3_80_v3.0.2", 0x0000, 0x20000, CRC(c09a3592) SHA1(830187dfe58e65289533717a797d2c42da86ac4e), ROM_BIOS(2))
|
||||
ROM_SYSTEM_BIOS(2, "rev30", "Rev 3.0")
|
||||
ROMX_LOAD( "sun3_80_v3.0", 0x0000, 0x20000, CRC(47e3b012) SHA1(1e045b6f542aaf7808d6567c28a9e734a8c5d815), ROM_BIOS(3))
|
||||
ROM_SYSTEM_BIOS(3, "rev292", "Rev 2.9.2")
|
||||
ROMX_LOAD( "sun3_80_v2.9.2", 0x0000, 0x20000, CRC(32bcf711) SHA1(7ecd4a0d0988c1d1d53fd79ac16c8456ed73ace1), ROM_BIOS(4))
|
||||
|
||||
// default NVRAM: includes valid settings for console on framebuffer, boot from SCSI disk, Ethernet ID, more
|
||||
ROM_REGION( 0x800, TIMEKEEPER_TAG, 0 )
|
||||
ROM_LOAD( "timekpr_380.bin", 0x000000, 0x000800, CRC(e76f1aae) SHA1(8e7c36e3928887a94a8133e8416ee4126c31edd7) )
|
||||
ROM_END
|
||||
|
||||
ROM_START( sun3_460 )
|
||||
ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF )
|
||||
/*
|
||||
Sun 3/460/480 V1.2.3 Bootprom
|
||||
Sun 3/460/480 V2.9.1 Bootprom (2 Files, one for odd and one for even addresses)
|
||||
Sun 3/460/480 V2.9.2 Bootprom
|
||||
Sun 3/460/480 V2.9.3 Bootprom
|
||||
Sun 3/460/480 V3.0 Bootprom (2 Files, one for odd and one for even addresses)
|
||||
*/
|
||||
ROM_SYSTEM_BIOS(0, "rev30", "Rev 3.0")
|
||||
ROMX_LOAD( "3_400_l.300", 0x00000, 0x10000, CRC(1312a04b) SHA1(6c3b67ba3567991897a48fe20f589ebbfcf0a35d), ROM_BIOS(1))
|
||||
ROMX_LOAD( "3_400_h.300", 0x10000, 0x10000, CRC(8d688672) SHA1(a5593844ce6af6c4f7f39bb653dc8f964b73b095), ROM_BIOS(1))
|
||||
ROM_SYSTEM_BIOS(1, "rev291", "Rev 2.9.1")
|
||||
ROMX_LOAD( "sun3_460_v2.9.1_0", 0x00000, 0x10000, CRC(d62dbf09) SHA1(4a6b5fd7840b44fe93c9058a8973d8dd3c9f7d24), ROM_BIOS(2))
|
||||
ROMX_LOAD( "sun3_460_v2.9.1_1", 0x10000, 0x10000, CRC(3b5a5942) SHA1(ed6250e3c07d7cb62d4dd517a8637c8d37e16dc5), ROM_BIOS(2))
|
||||
ROM_END
|
||||
|
||||
/* Driver */
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
|
||||
COMP( 198?, sun3_80, 0, 0, sun3_80, sun3x, driver_device, 0, "Sun Microsystems", "Sun 3/80", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Hydra
|
||||
COMP( 198?, sun3_460, 0, 0, sun3_460, sun3x, driver_device, 0, "Sun Microsystems", "Sun 3/460/470/480", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Pegasus
|
||||
@ -33972,12 +33972,14 @@ sun2_50 //
|
||||
sun3_110 //
|
||||
sun3_150 //
|
||||
sun3_260 //
|
||||
sun3_460 //
|
||||
sun3_50 //
|
||||
sun3_60 //
|
||||
sun3_80 //
|
||||
sun3_e //
|
||||
|
||||
@source:sun3x.cpp
|
||||
sun3_80 //
|
||||
sun3_460 //
|
||||
|
||||
@source:sun4.cpp
|
||||
sun_s10 //
|
||||
sun_s20 //
|
||||
|
||||
@ -545,6 +545,7 @@ studio2.cpp
|
||||
sun1.cpp
|
||||
sun2.cpp
|
||||
sun3.cpp
|
||||
sun3x.cpp
|
||||
sun4.cpp
|
||||
super6.cpp
|
||||
super80.cpp
|
||||
|
||||
Loading…
Reference in New Issue
Block a user