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h8_dma: reorganize, upgrade

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This commit is contained in:
Olivier Galibert 2023-06-03 17:57:05 +02:00
parent c07474dfb3
commit 37dda0012c
22 changed files with 1117 additions and 622 deletions
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46
src/devices/cpu/h8/h8.cpp
View File

@ -115,6 +115,7 @@ void h8_device::device_start()
save_item(NAME(m_irq_level));
save_item(NAME(m_taken_irq_level));
save_item(NAME(m_irq_nmi));
save_item(NAME(m_current_dma));
set_icountptr(m_icount);
@ -133,6 +134,8 @@ void h8_device::device_start()
m_requested_state = -1;
m_dma_device = nullptr;
m_dtc_device = nullptr;
memset(m_dma_channel, 0, sizeof(m_dma_channel));
}
void h8_device::device_reset()
@ -147,25 +150,46 @@ void h8_device::device_reset()
m_irq_nmi = false;
m_taken_irq_vector = 0;
m_taken_irq_level = -1;
m_current_dma = nullptr;
m_current_dma = -1;
m_current_dtc = nullptr;
}
bool h8_device::trigger_dma(int vector)
{
return (m_dma_device && m_dma_device->trigger_dma(vector)) || (m_dtc_device && m_dtc_device->trigger_dtc(vector));
bool dma_triggered = false;
bool drop_interrupt = false;
for(int i=0; i != 8; i++)
if(m_dma_channel[i] && ((m_dma_channel[i]->m_flags & (h8_dma_state::ACTIVE|h8_dma_state::SUSPENDED)) == (h8_dma_state::ACTIVE|h8_dma_state::SUSPENDED)) && m_dma_channel[i]->m_trigger_vector == vector) {
m_dma_channel[i]->m_flags &= ~h8_dma_state::SUSPENDED;
dma_triggered = true;
if(m_dma_channel[i]->m_flags & h8_dma_state::EAT_INTERRUPT)
drop_interrupt = true;
}
// DMA can mask interrupt to the DTC
if(!drop_interrupt && m_dtc_device && m_dtc_device->trigger_dtc(vector))
drop_interrupt = true;
if(dma_triggered)
update_active_dma_channel();
return drop_interrupt;
}
void h8_device::set_current_dma(h8_dma_state *state)
void h8_device::set_dma_channel(h8_dma_state *state)
{
m_current_dma = state;
if(!state)
logerror("DMA done\n");
else {
logerror("New current dma s=%x d=%x is=%d id=%d count=%x m=%d autoreq=%d\n",
state->m_source, state->m_dest, state->m_incs, state->m_incd,
state->m_count, state->m_mode_16 ? 16 : 8, state->m_autoreq);
m_dma_channel[state->m_id] = state;
}
void h8_device::update_active_dma_channel()
{
for(int i=0; i != 8; i++) {
if(m_dma_channel[i] && ((m_dma_channel[i]->m_flags & (h8_dma_state::ACTIVE|h8_dma_state::SUSPENDED)) == h8_dma_state::ACTIVE)) {
m_current_dma = i;
return;
}
}
m_current_dma = -1;
}
void h8_device::set_current_dtc(h8_dtc_state *state)
@ -396,7 +420,7 @@ void h8_device::prefetch_done()
if(m_requested_state != -1) {
m_inst_state = m_requested_state;
m_requested_state = -1;
} else if(m_current_dma && !m_current_dma->m_suspended)
} else if(m_current_dma != -1)
m_inst_state = STATE_DMA;
else if(m_current_dtc)
m_inst_state = STATE_DTC;

10
src/devices/cpu/h8/h8.h
View File

@ -14,7 +14,7 @@
#pragma once
class h8_dma_device;
class h8gen_dma_device;
class h8_dtc_device;
struct h8_dma_state;
struct h8_dtc_state;
@ -66,7 +66,8 @@ public:
void internal_update();
void set_irq(int irq_vector, int irq_level, bool irq_nmi);
bool trigger_dma(int vector);
void set_current_dma(h8_dma_state *state);
void set_dma_channel(h8_dma_state *state);
void update_active_dma_channel();
void set_current_dtc(h8_dtc_state *state);
void request_state(int state);
bool access_is_dma() const { return m_inst_state == STATE_DMA || m_inst_state == STATE_DTC; }
@ -117,9 +118,10 @@ protected:
memory_access<32, 1, 0, ENDIANNESS_BIG>::cache m_cache;
memory_access<32, 1, 0, ENDIANNESS_BIG>::specific m_program;
memory_access<16, 1, -1, ENDIANNESS_BIG>::specific m_io;
h8_dma_device *m_dma_device;
h8gen_dma_device *m_dma_device;
h8_dtc_device *m_dtc_device;
h8_dma_state *m_current_dma;
h8_dma_state *m_dma_channel[8];
int m_current_dma;
h8_dtc_state *m_current_dtc;
uint32_t m_PPC; /* previous program counter */

34
src/devices/cpu/h8/h8.lst
View File

@ -200,25 +200,27 @@ macro jsr32 %opc %spreg
prefetch_noirq
10003 dma
if(m_current_dma->m_count == 1)
m_dma_device->count_last(m_current_dma->m_id);
if(m_current_dma->m_mode_16) {
m_TMP1 = read16(m_current_dma->m_source);
write16(m_current_dma->m_dest, m_TMP1);
m_TMP2 = m_current_dma;
if(m_dma_channel[m_TMP2]->m_flags & h8_dma_state::MODE_16) {
m_TMP1 = read16(m_dma_channel[m_TMP2]->m_source);
if(m_dma_channel[m_TMP2]->m_count == 1 && !(m_dma_channel[m_TMP2]->m_flags & (h8_dma_state::BLOCK|h8_dma_state::REPEAT)))
m_dma_device->count_last(m_dma_channel[m_TMP2]->m_id);
write16(m_dma_channel[m_TMP2]->m_dest, m_TMP1);
} else {
m_TMP1 = read8(m_current_dma->m_source);
write8(m_current_dma->m_dest, m_TMP1);
m_TMP1 = read8(m_dma_channel[m_TMP2]->m_source);
if(m_dma_channel[m_TMP2]->m_count == 1 && !(m_dma_channel[m_TMP2]->m_flags & (h8_dma_state::BLOCK|h8_dma_state::REPEAT)))
m_dma_device->count_last(m_dma_channel[m_TMP2]->m_id);
write8(m_dma_channel[m_TMP2]->m_dest, m_TMP1);
}
m_current_dma->m_source += m_current_dma->m_incs;
m_current_dma->m_dest += m_current_dma->m_incd;
m_current_dma->m_count--;
if(!m_current_dma->m_autoreq)
m_current_dma->m_suspended = true;
if(!m_current_dma->m_count) {
uint8_t id = m_current_dma->m_id;
m_current_dma = nullptr;
m_dma_device->count_done(id);
m_dma_channel[m_TMP2]->m_source += m_dma_channel[m_TMP2]->m_incs;
m_dma_channel[m_TMP2]->m_dest += m_dma_channel[m_TMP2]->m_incd;
m_dma_channel[m_TMP2]->m_count--;
if(m_dma_channel[m_TMP2]->m_flags & h8_dma_state::SUSPEND_AFTER_TRANSFER) {
m_dma_channel[m_TMP2]->m_flags |= h8_dma_state::SUSPENDED;
update_active_dma_channel();
}
if(!m_dma_channel[m_TMP2]->m_count)
m_dma_device->count_done(m_TMP2);
prefetch_done();
10004 dtc s20

47
src/devices/cpu/h8/h83002.cpp
View File

@ -39,26 +39,26 @@ void h83002_device::map(address_map &map)
map(base | 0xfd10, base | 0xff0f).ram();
map(base | 0xff20, base | 0xff21).rw(m_dma0, FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
map(base | 0xff22, base | 0xff23).rw(m_dma0, FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
map(base | 0xff24, base | 0xff25).rw(m_dma0, FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
map(base | 0xff26, base | 0xff26).rw(m_dma0, FUNC(h8_dma_channel_device::ioara8_r), FUNC(h8_dma_channel_device::ioara8_w));
map(base | 0xff27, base | 0xff27).rw(m_dma0, FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
map(base | 0xff28, base | 0xff29).rw(m_dma0, FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
map(base | 0xff2a, base | 0xff2b).rw(m_dma0, FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
map(base | 0xff2c, base | 0xff2d).rw(m_dma0, FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
map(base | 0xff2e, base | 0xff2e).rw(m_dma0, FUNC(h8_dma_channel_device::ioarb8_r), FUNC(h8_dma_channel_device::ioarb8_w));
map(base | 0xff2f, base | 0xff2f).rw(m_dma0, FUNC(h8_dma_channel_device::dtcrb_r), FUNC(h8_dma_channel_device::dtcrb_w));
map(base | 0xff30, base | 0xff31).rw(m_dma1, FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
map(base | 0xff32, base | 0xff33).rw(m_dma1, FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
map(base | 0xff34, base | 0xff35).rw(m_dma1, FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
map(base | 0xff36, base | 0xff36).rw(m_dma1, FUNC(h8_dma_channel_device::ioara8_r), FUNC(h8_dma_channel_device::ioara8_w));
map(base | 0xff37, base | 0xff37).rw(m_dma1, FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
map(base | 0xff38, base | 0xff39).rw(m_dma1, FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
map(base | 0xff3a, base | 0xff3b).rw(m_dma1, FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
map(base | 0xff3c, base | 0xff3d).rw(m_dma1, FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
map(base | 0xff3e, base | 0xff3e).rw(m_dma1, FUNC(h8_dma_channel_device::ioarb8_r), FUNC(h8_dma_channel_device::ioarb8_w));
map(base | 0xff3f, base | 0xff3f).rw(m_dma1, FUNC(h8_dma_channel_device::dtcrb_r), FUNC(h8_dma_channel_device::dtcrb_w));
map(base | 0xff20, base | 0xff21).rw(m_dma0, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff22, base | 0xff23).rw(m_dma0, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff24, base | 0xff25).rw(m_dma0, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff26, base | 0xff26).rw(m_dma0, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff27, base | 0xff27).rw(m_dma0, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff28, base | 0xff29).rw(m_dma0, FUNC(h8h_dma_channel_device::marbh_r), FUNC(h8h_dma_channel_device::marbh_w));
map(base | 0xff2a, base | 0xff2b).rw(m_dma0, FUNC(h8h_dma_channel_device::marbl_r), FUNC(h8h_dma_channel_device::marbl_w));
map(base | 0xff2c, base | 0xff2d).rw(m_dma0, FUNC(h8h_dma_channel_device::etcrb_r), FUNC(h8h_dma_channel_device::etcrb_w));
map(base | 0xff2e, base | 0xff2e).rw(m_dma0, FUNC(h8h_dma_channel_device::ioarb8_r), FUNC(h8h_dma_channel_device::ioarb8_w));
map(base | 0xff2f, base | 0xff2f).rw(m_dma0, FUNC(h8h_dma_channel_device::dtcrb_r), FUNC(h8h_dma_channel_device::dtcrb_w));
map(base | 0xff30, base | 0xff31).rw(m_dma1, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff32, base | 0xff33).rw(m_dma1, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff34, base | 0xff35).rw(m_dma1, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff36, base | 0xff36).rw(m_dma1, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff37, base | 0xff37).rw(m_dma1, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff38, base | 0xff39).rw(m_dma1, FUNC(h8h_dma_channel_device::marbh_r), FUNC(h8h_dma_channel_device::marbh_w));
map(base | 0xff3a, base | 0xff3b).rw(m_dma1, FUNC(h8h_dma_channel_device::marbl_r), FUNC(h8h_dma_channel_device::marbl_w));
map(base | 0xff3c, base | 0xff3d).rw(m_dma1, FUNC(h8h_dma_channel_device::etcrb_r), FUNC(h8h_dma_channel_device::etcrb_w));
map(base | 0xff3e, base | 0xff3e).rw(m_dma1, FUNC(h8h_dma_channel_device::ioarb8_r), FUNC(h8h_dma_channel_device::ioarb8_w));
map(base | 0xff3f, base | 0xff3f).rw(m_dma1, FUNC(h8h_dma_channel_device::dtcrb_r), FUNC(h8h_dma_channel_device::dtcrb_w));
map(base | 0xff60, base | 0xff60).rw(m_timer16, FUNC(h8_timer16_device::tstr_r), FUNC(h8_timer16_device::tstr_w));
map(base | 0xff61, base | 0xff61).rw(m_timer16, FUNC(h8_timer16_device::tsyr_r), FUNC(h8_timer16_device::tsyr_w));
@ -145,10 +145,9 @@ void h83002_device::device_add_mconfig(machine_config &config)
{
H8H_INTC(config, m_intc, *this);
H8_ADC_3337(config, m_adc, *this, m_intc, 60);
H8_DMA(config, m_dma, *this);
// (H8/2002.pdf) Table 8-11 DMAC Activation Sources
H8_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc, 44, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53);
H8_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc, 46, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53);
H8H_DMA(config, m_dma, *this);
H8H_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc, false, false);
H8H_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc, false, false);
H8_PORT(config, m_port4, *this, h8_device::PORT_4, 0x00, 0x00);
H8_PORT(config, m_port6, *this, h8_device::PORT_6, 0x80, 0x80);
H8_PORT(config, m_port7, *this, h8_device::PORT_7, 0x00, 0x00);

6
src/devices/cpu/h8/h83002.h
View File

@ -44,9 +44,9 @@ public:
protected:
required_device<h8h_intc_device> m_intc;
required_device<h8_adc_device> m_adc;
optional_device<h8_dma_device> m_dma;
optional_device<h8_dma_channel_device> m_dma0;
optional_device<h8_dma_channel_device> m_dma1;
required_device<h8h_dma_device> m_dma;
required_device<h8h_dma_channel_device> m_dma0;
required_device<h8h_dma_channel_device> m_dma1;
required_device<h8_port_device> m_port4;
required_device<h8_port_device> m_port6;
required_device<h8_port_device> m_port7;

81
src/devices/cpu/h8/h83003.cpp
View File

@ -43,41 +43,41 @@ void h83003_device::map(address_map &map)
map(base | 0xfd10, base | 0xff0f).ram();
map(base | 0xff20, base | 0xff21).rw(m_dma0, FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
map(base | 0xff22, base | 0xff23).rw(m_dma0, FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
map(base | 0xff24, base | 0xff25).rw(m_dma0, FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
map(base | 0xff26, base | 0xff26).rw(m_dma0, FUNC(h8_dma_channel_device::ioara8_r), FUNC(h8_dma_channel_device::ioara8_w));
map(base | 0xff27, base | 0xff27).rw(m_dma0, FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
map(base | 0xff28, base | 0xff29).rw(m_dma0, FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
map(base | 0xff2a, base | 0xff2b).rw(m_dma0, FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
map(base | 0xff2c, base | 0xff2d).rw(m_dma0, FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
map(base | 0xff2e, base | 0xff2e).rw(m_dma0, FUNC(h8_dma_channel_device::ioarb8_r), FUNC(h8_dma_channel_device::ioarb8_w));
map(base | 0xff2f, base | 0xff2f).rw(m_dma0, FUNC(h8_dma_channel_device::dtcrb_r), FUNC(h8_dma_channel_device::dtcrb_w));
map(base | 0xff30, base | 0xff31).rw(m_dma1, FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
map(base | 0xff32, base | 0xff33).rw(m_dma1, FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
map(base | 0xff34, base | 0xff35).rw(m_dma1, FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
map(base | 0xff36, base | 0xff36).rw(m_dma1, FUNC(h8_dma_channel_device::ioara8_r), FUNC(h8_dma_channel_device::ioara8_w));
map(base | 0xff37, base | 0xff37).rw(m_dma1, FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
map(base | 0xff38, base | 0xff39).rw(m_dma1, FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
map(base | 0xff3a, base | 0xff3b).rw(m_dma1, FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
map(base | 0xff3c, base | 0xff3d).rw(m_dma1, FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
map(base | 0xff3e, base | 0xff3e).rw(m_dma1, FUNC(h8_dma_channel_device::ioarb8_r), FUNC(h8_dma_channel_device::ioarb8_w));
map(base | 0xff3f, base | 0xff3f).rw(m_dma1, FUNC(h8_dma_channel_device::dtcrb_r), FUNC(h8_dma_channel_device::dtcrb_w));
map(base | 0xff40, base | 0xff41).rw(m_dma2, FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
map(base | 0xff42, base | 0xff43).rw(m_dma2, FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
map(base | 0xff44, base | 0xff45).rw(m_dma2, FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
map(base | 0xff46, base | 0xff46).rw(m_dma2, FUNC(h8_dma_channel_device::ioara8_r), FUNC(h8_dma_channel_device::ioara8_w));
map(base | 0xff47, base | 0xff47).rw(m_dma2, FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
map(base | 0xff48, base | 0xff49).rw(m_dma2, FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
map(base | 0xff4a, base | 0xff4b).rw(m_dma2, FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
map(base | 0xff4c, base | 0xff4d).rw(m_dma2, FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
map(base | 0xff4e, base | 0xff4e).rw(m_dma2, FUNC(h8_dma_channel_device::ioarb8_r), FUNC(h8_dma_channel_device::ioarb8_w));
map(base | 0xff4f, base | 0xff4f).rw(m_dma2, FUNC(h8_dma_channel_device::dtcrb_r), FUNC(h8_dma_channel_device::dtcrb_w));
map(base | 0xff50, base | 0xff51).rw(m_dma3, FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
map(base | 0xff52, base | 0xff53).rw(m_dma3, FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
map(base | 0xff54, base | 0xff55).rw(m_dma3, FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
map(base | 0xff56, base | 0xff56).rw(m_dma3, FUNC(h8_dma_channel_device::ioara8_r), FUNC(h8_dma_channel_device::ioara8_w));
map(base | 0xff57, base | 0xff57).rw(m_dma3, FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
map(base | 0xff20, base | 0xff21).rw(m_dma0, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff22, base | 0xff23).rw(m_dma0, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff24, base | 0xff25).rw(m_dma0, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff26, base | 0xff26).rw(m_dma0, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff27, base | 0xff27).rw(m_dma0, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff28, base | 0xff29).rw(m_dma0, FUNC(h8h_dma_channel_device::marbh_r), FUNC(h8h_dma_channel_device::marbh_w));
map(base | 0xff2a, base | 0xff2b).rw(m_dma0, FUNC(h8h_dma_channel_device::marbl_r), FUNC(h8h_dma_channel_device::marbl_w));
map(base | 0xff2c, base | 0xff2d).rw(m_dma0, FUNC(h8h_dma_channel_device::etcrb_r), FUNC(h8h_dma_channel_device::etcrb_w));
map(base | 0xff2e, base | 0xff2e).rw(m_dma0, FUNC(h8h_dma_channel_device::ioarb8_r), FUNC(h8h_dma_channel_device::ioarb8_w));
map(base | 0xff2f, base | 0xff2f).rw(m_dma0, FUNC(h8h_dma_channel_device::dtcrb_r), FUNC(h8h_dma_channel_device::dtcrb_w));
map(base | 0xff30, base | 0xff31).rw(m_dma1, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff32, base | 0xff33).rw(m_dma1, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff34, base | 0xff35).rw(m_dma1, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff36, base | 0xff36).rw(m_dma1, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff37, base | 0xff37).rw(m_dma1, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff38, base | 0xff39).rw(m_dma1, FUNC(h8h_dma_channel_device::marbh_r), FUNC(h8h_dma_channel_device::marbh_w));
map(base | 0xff3a, base | 0xff3b).rw(m_dma1, FUNC(h8h_dma_channel_device::marbl_r), FUNC(h8h_dma_channel_device::marbl_w));
map(base | 0xff3c, base | 0xff3d).rw(m_dma1, FUNC(h8h_dma_channel_device::etcrb_r), FUNC(h8h_dma_channel_device::etcrb_w));
map(base | 0xff3e, base | 0xff3e).rw(m_dma1, FUNC(h8h_dma_channel_device::ioarb8_r), FUNC(h8h_dma_channel_device::ioarb8_w));
map(base | 0xff3f, base | 0xff3f).rw(m_dma1, FUNC(h8h_dma_channel_device::dtcrb_r), FUNC(h8h_dma_channel_device::dtcrb_w));
map(base | 0xff40, base | 0xff41).rw(m_dma2, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff42, base | 0xff43).rw(m_dma2, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff44, base | 0xff45).rw(m_dma2, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff46, base | 0xff46).rw(m_dma2, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff47, base | 0xff47).rw(m_dma2, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff48, base | 0xff49).rw(m_dma2, FUNC(h8h_dma_channel_device::marbh_r), FUNC(h8h_dma_channel_device::marbh_w));
map(base | 0xff4a, base | 0xff4b).rw(m_dma2, FUNC(h8h_dma_channel_device::marbl_r), FUNC(h8h_dma_channel_device::marbl_w));
map(base | 0xff4c, base | 0xff4d).rw(m_dma2, FUNC(h8h_dma_channel_device::etcrb_r), FUNC(h8h_dma_channel_device::etcrb_w));
map(base | 0xff4e, base | 0xff4e).rw(m_dma2, FUNC(h8h_dma_channel_device::ioarb8_r), FUNC(h8h_dma_channel_device::ioarb8_w));
map(base | 0xff4f, base | 0xff4f).rw(m_dma2, FUNC(h8h_dma_channel_device::dtcrb_r), FUNC(h8h_dma_channel_device::dtcrb_w));
map(base | 0xff50, base | 0xff51).rw(m_dma3, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff52, base | 0xff53).rw(m_dma3, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff54, base | 0xff55).rw(m_dma3, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff56, base | 0xff56).rw(m_dma3, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff57, base | 0xff57).rw(m_dma3, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff60, base | 0xff60).rw(m_timer16, FUNC(h8_timer16_device::tstr_r), FUNC(h8_timer16_device::tstr_w));
map(base | 0xff61, base | 0xff61).rw(m_timer16, FUNC(h8_timer16_device::tsyr_r), FUNC(h8_timer16_device::tsyr_w));
@ -168,12 +168,11 @@ void h83003_device::device_add_mconfig(machine_config &config)
{
H8H_INTC(config, m_intc, *this);
H8_ADC_3337(config, m_adc, *this, m_intc, 60);
H8_DMA(config, m_dma, *this);
// (h8-3002.pdf) Table 8-11 DMAC Activation Sources
H8_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc, 44, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53);
H8_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc, 46, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53);
H8_DMA_CHANNEL(config, m_dma2, *this, m_dma, m_intc, 48, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53);
H8_DMA_CHANNEL(config, m_dma3, *this, m_dma, m_intc, 50, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53);
H8H_DMA(config, m_dma, *this);
H8H_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc, false, false);
H8H_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc, false, false);
H8H_DMA_CHANNEL(config, m_dma2, *this, m_dma, m_intc, false, true);
H8H_DMA_CHANNEL(config, m_dma3, *this, m_dma, m_intc, false, true);
H8_PORT(config, m_port4, *this, h8_device::PORT_4, 0x00, 0x00);
H8_PORT(config, m_port5, *this, h8_device::PORT_5, 0x0f, 0x00);
H8_PORT(config, m_port6, *this, h8_device::PORT_6, 0x80, 0x80);

10
src/devices/cpu/h8/h83003.h
View File

@ -46,11 +46,11 @@ public:
protected:
required_device<h8h_intc_device> m_intc;
required_device<h8_adc_device> m_adc;
required_device<h8_dma_device> m_dma;
required_device<h8_dma_channel_device> m_dma0;
required_device<h8_dma_channel_device> m_dma1;
required_device<h8_dma_channel_device> m_dma2;
required_device<h8_dma_channel_device> m_dma3;
required_device<h8h_dma_device> m_dma;
required_device<h8h_dma_channel_device> m_dma0;
required_device<h8h_dma_channel_device> m_dma1;
required_device<h8h_dma_channel_device> m_dma2;
required_device<h8h_dma_channel_device> m_dma3;
required_device<h8_port_device> m_port4;
required_device<h8_port_device> m_port5;
required_device<h8_port_device> m_port6;

26
src/devices/cpu/h8/h83042.cpp
View File

@ -11,6 +11,9 @@ h83042_device::h83042_device(const machine_config &mconfig, device_type type, co
h8h_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h83042_device::map), this)),
m_intc(*this, "intc"),
m_adc(*this, "adc"),
m_dma(*this, "dma"),
m_dma0(*this, "dma:0"),
m_dma1(*this, "dma:1"),
m_port1(*this, "port1"),
m_port2(*this, "port2"),
m_port3(*this, "port3"),
@ -58,6 +61,26 @@ void h83042_device::map(address_map &map)
map(base | 0xf710, base | 0xff0f).ram();
map(base | 0xff20, base | 0xff21).rw(m_dma0, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff22, base | 0xff23).rw(m_dma0, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff24, base | 0xff25).rw(m_dma0, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff26, base | 0xff26).rw(m_dma0, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff27, base | 0xff27).rw(m_dma0, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff28, base | 0xff29).rw(m_dma0, FUNC(h8h_dma_channel_device::marbh_r), FUNC(h8h_dma_channel_device::marbh_w));
map(base | 0xff2a, base | 0xff2b).rw(m_dma0, FUNC(h8h_dma_channel_device::marbl_r), FUNC(h8h_dma_channel_device::marbl_w));
map(base | 0xff2c, base | 0xff2d).rw(m_dma0, FUNC(h8h_dma_channel_device::etcrb_r), FUNC(h8h_dma_channel_device::etcrb_w));
map(base | 0xff2e, base | 0xff2e).rw(m_dma0, FUNC(h8h_dma_channel_device::ioarb8_r), FUNC(h8h_dma_channel_device::ioarb8_w));
map(base | 0xff2f, base | 0xff2f).rw(m_dma0, FUNC(h8h_dma_channel_device::dtcrb_r), FUNC(h8h_dma_channel_device::dtcrb_w));
map(base | 0xff30, base | 0xff31).rw(m_dma1, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff32, base | 0xff33).rw(m_dma1, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff34, base | 0xff35).rw(m_dma1, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff36, base | 0xff36).rw(m_dma1, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff37, base | 0xff37).rw(m_dma1, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff38, base | 0xff39).rw(m_dma1, FUNC(h8h_dma_channel_device::marbh_r), FUNC(h8h_dma_channel_device::marbh_w));
map(base | 0xff3a, base | 0xff3b).rw(m_dma1, FUNC(h8h_dma_channel_device::marbl_r), FUNC(h8h_dma_channel_device::marbl_w));
map(base | 0xff3c, base | 0xff3d).rw(m_dma1, FUNC(h8h_dma_channel_device::etcrb_r), FUNC(h8h_dma_channel_device::etcrb_w));
map(base | 0xff3e, base | 0xff3e).rw(m_dma1, FUNC(h8h_dma_channel_device::ioarb8_r), FUNC(h8h_dma_channel_device::ioarb8_w));
map(base | 0xff3f, base | 0xff3f).rw(m_dma1, FUNC(h8h_dma_channel_device::dtcrb_r), FUNC(h8h_dma_channel_device::dtcrb_w));
map(base | 0xff60, base | 0xff60).rw(m_timer16, FUNC(h8_timer16_device::tstr_r), FUNC(h8_timer16_device::tstr_w));
map(base | 0xff61, base | 0xff61).rw(m_timer16, FUNC(h8_timer16_device::tsyr_r), FUNC(h8_timer16_device::tsyr_w));
map(base | 0xff62, base | 0xff62).rw(m_timer16, FUNC(h8_timer16_device::tmdr_r), FUNC(h8_timer16_device::tmdr_w));
@ -153,6 +176,9 @@ void h83042_device::device_add_mconfig(machine_config &config)
{
H8H_INTC(config, m_intc, *this);
H8_ADC_3337(config, m_adc, *this, m_intc, 60);
H8H_DMA(config, m_dma, *this);
H8H_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc, false, false);
H8H_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc, false, false);
H8_PORT(config, m_port1, *this, h8_device::PORT_1, 0x00, 0x00);
H8_PORT(config, m_port2, *this, h8_device::PORT_2, 0x00, 0x00);
H8_PORT(config, m_port3, *this, h8_device::PORT_3, 0x00, 0x00);

4
src/devices/cpu/h8/h83042.h
View File

@ -24,6 +24,7 @@
#include "h8h.h"
#include "h8_adc.h"
#include "h8_dma.h"
#include "h8_port.h"
#include "h8_intc.h"
#include "h8_timer16.h"
@ -42,6 +43,9 @@ protected:
required_device<h8h_intc_device> m_intc;
required_device<h8_adc_device> m_adc;
required_device<h8h_dma_device> m_dma;
required_device<h8h_dma_channel_device> m_dma0;
required_device<h8h_dma_channel_device> m_dma1;
required_device<h8_port_device> m_port1;
required_device<h8_port_device> m_port2;
required_device<h8_port_device> m_port3;

26
src/devices/cpu/h8/h83048.cpp
View File

@ -12,6 +12,9 @@ h83048_device::h83048_device(const machine_config &mconfig, device_type type, co
h8h_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h83048_device::map), this)),
m_intc(*this, "intc"),
m_adc(*this, "adc"),
m_dma(*this, "dma"),
m_dma0(*this, "dma:0"),
m_dma1(*this, "dma:1"),
m_port1(*this, "port1"),
m_port2(*this, "port2"),
m_port3(*this, "port3"),
@ -63,6 +66,26 @@ void h83048_device::map(address_map &map)
map(base | m_ram_start, base | 0xff0f).ram();
map(base | 0xff20, base | 0xff21).rw(m_dma0, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff22, base | 0xff23).rw(m_dma0, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff24, base | 0xff25).rw(m_dma0, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff26, base | 0xff26).rw(m_dma0, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff27, base | 0xff27).rw(m_dma0, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff28, base | 0xff29).rw(m_dma0, FUNC(h8h_dma_channel_device::marbh_r), FUNC(h8h_dma_channel_device::marbh_w));
map(base | 0xff2a, base | 0xff2b).rw(m_dma0, FUNC(h8h_dma_channel_device::marbl_r), FUNC(h8h_dma_channel_device::marbl_w));
map(base | 0xff2c, base | 0xff2d).rw(m_dma0, FUNC(h8h_dma_channel_device::etcrb_r), FUNC(h8h_dma_channel_device::etcrb_w));
map(base | 0xff2e, base | 0xff2e).rw(m_dma0, FUNC(h8h_dma_channel_device::ioarb8_r), FUNC(h8h_dma_channel_device::ioarb8_w));
map(base | 0xff2f, base | 0xff2f).rw(m_dma0, FUNC(h8h_dma_channel_device::dtcrb_r), FUNC(h8h_dma_channel_device::dtcrb_w));
map(base | 0xff30, base | 0xff31).rw(m_dma1, FUNC(h8h_dma_channel_device::marah_r), FUNC(h8h_dma_channel_device::marah_w));
map(base | 0xff32, base | 0xff33).rw(m_dma1, FUNC(h8h_dma_channel_device::maral_r), FUNC(h8h_dma_channel_device::maral_w));
map(base | 0xff34, base | 0xff35).rw(m_dma1, FUNC(h8h_dma_channel_device::etcra_r), FUNC(h8h_dma_channel_device::etcra_w));
map(base | 0xff36, base | 0xff36).rw(m_dma1, FUNC(h8h_dma_channel_device::ioara8_r), FUNC(h8h_dma_channel_device::ioara8_w));
map(base | 0xff37, base | 0xff37).rw(m_dma1, FUNC(h8h_dma_channel_device::dtcra_r), FUNC(h8h_dma_channel_device::dtcra_w));
map(base | 0xff38, base | 0xff39).rw(m_dma1, FUNC(h8h_dma_channel_device::marbh_r), FUNC(h8h_dma_channel_device::marbh_w));
map(base | 0xff3a, base | 0xff3b).rw(m_dma1, FUNC(h8h_dma_channel_device::marbl_r), FUNC(h8h_dma_channel_device::marbl_w));
map(base | 0xff3c, base | 0xff3d).rw(m_dma1, FUNC(h8h_dma_channel_device::etcrb_r), FUNC(h8h_dma_channel_device::etcrb_w));
map(base | 0xff3e, base | 0xff3e).rw(m_dma1, FUNC(h8h_dma_channel_device::ioarb8_r), FUNC(h8h_dma_channel_device::ioarb8_w));
map(base | 0xff3f, base | 0xff3f).rw(m_dma1, FUNC(h8h_dma_channel_device::dtcrb_r), FUNC(h8h_dma_channel_device::dtcrb_w));
map(base | 0xff60, base | 0xff60).rw(m_timer16, FUNC(h8_timer16_device::tstr_r), FUNC(h8_timer16_device::tstr_w));
map(base | 0xff61, base | 0xff61).rw(m_timer16, FUNC(h8_timer16_device::tsyr_r), FUNC(h8_timer16_device::tsyr_w));
map(base | 0xff62, base | 0xff62).rw(m_timer16, FUNC(h8_timer16_device::tmdr_r), FUNC(h8_timer16_device::tmdr_w));
@ -158,6 +181,9 @@ void h83048_device::device_add_mconfig(machine_config &config)
{
H8H_INTC(config, m_intc, *this);
H8_ADC_3337(config, m_adc, *this, m_intc, 60);
H8H_DMA(config, m_dma, *this);
H8H_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc, false, false);
H8H_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc, false, false);
H8_PORT(config, m_port1, *this, h8_device::PORT_1, 0x00, 0x00);
H8_PORT(config, m_port2, *this, h8_device::PORT_2, 0x00, 0x00);
H8_PORT(config, m_port3, *this, h8_device::PORT_3, 0x00, 0x00);

4
src/devices/cpu/h8/h83048.h
View File

@ -24,6 +24,7 @@
#include "h8h.h"
#include "h8_adc.h"
#include "h8_dma.h"
#include "h8_port.h"
#include "h8_intc.h"
#include "h8_timer16.h"
@ -45,6 +46,9 @@ protected:
required_device<h8h_intc_device> m_intc;
required_device<h8_adc_device> m_adc;
required_device<h8h_dma_device> m_dma;
required_device<h8h_dma_channel_device> m_dma0;
required_device<h8h_dma_channel_device> m_dma1;
required_device<h8_port_device> m_port1;
required_device<h8_port_device> m_port2;
required_device<h8_port_device> m_port3;

960
src/devices/cpu/h8/h8_dma.cpp
View File

File diff suppressed because it is too large Load Diff

306
src/devices/cpu/h8/h8_dma.h
View File

@ -17,16 +17,32 @@
#include "h8_intc.h"
struct h8_dma_state {
uint32_t m_source, m_dest;
int32_t m_incs, m_incd;
uint32_t m_count;
int m_id;
bool m_autoreq; // activate by auto-request
bool m_suspended;
bool m_mode_16;
enum {
ACTIVE = 0x0001, // DMA is configured
SUSPENDED = 0x0002, // DMA currently suspended until trigger happens
SUSPEND_AFTER_TRANSFER = 0x0004, // Auto-suspend DMA after each transfer
BLOCK = 0x0008, // FAE block mode (cleared on last block)
REPEAT = 0x0010, // SAE repeat mode
MODE_16 = 0x0020, // Transfer 16-bits values
EAT_INTERRUPT = 0x0040, // Discard interrupt when used as trigger
TEND_INTERRUPT = 0x0080, // Interrupt on end of transfer
SOURCE_DECREMENT = 0x0100, // Decrement source instead of increment (folded into incs/incd)
DEST_DECREMENT = 0x0200, // Decrement source instead of increment (folded into incs/incd)
SOURCE_IDLE = 0x0400, // Don't increment/decrement source (folded into incs/incd)
DEST_IDLE = 0x0800, // Don't increment/decrement destination (folded into incs/incd)
MAR_IS_DEST = 0x1000, // MAR is destination in SAE (folded), destibation is the block in fae block
FAE = 0x2000, // FAE mode (for interrupt generation)
};
u32 m_source, m_dest;
s32 m_incs, m_incd;
u32 m_count, m_bcount;
u16 m_flags;
u8 m_id;
s8 m_trigger_vector;
};
class h8_dma_channel_device;
class h8gen_dma_channel_device;
enum {
// mind the order, all DREQ, TEND need to be sequential
@ -41,136 +57,220 @@ enum {
H8_INPUT_LINE_TEND3,
};
class h8_dma_device : public device_t {
class h8h_dma_device;
class h8s_dma_device;
DECLARE_DEVICE_TYPE(H8H_DMA, h8h_dma_device)
DECLARE_DEVICE_TYPE(H8S_DMA, h8s_dma_device)
class h8gen_dma_device : public device_t {
public:
h8_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
template<typename T> h8_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu) :
h8_dma_device(mconfig, tag, owner)
{
m_cpu.set_tag(std::forward<T>(cpu));
}
uint8_t dmawer_r();
void dmawer_w(uint8_t data);
uint8_t dmatcr_r();
void dmatcr_w(uint8_t data);
uint16_t dmabcr_r();
void dmabcr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
bool trigger_dma(int vector);
void count_last(int id);
void count_done(int id);
void clear_dte(int id);
void set_input(int inputnum, int state);
void start_stop_test();
protected:
required_device<h8_device> m_cpu;
required_device<h8_dma_channel_device> m_dmach0, m_dmach1;
optional_device_array<h8gen_dma_channel_device, 4> m_dmach;
virtual void device_start() override;
virtual void device_reset() override;
bool m_dreq[2];
virtual u8 active_channels() const = 0;
uint8_t m_dmawer, m_dmatcr;
uint16_t m_dmabcr;
h8gen_dma_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock = 0);
};
class h8_dma_channel_device : public device_t {
class h8h_dma_device : public h8gen_dma_device
{
public:
h8h_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0);
template<typename T> h8h_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu)
: h8h_dma_device(mconfig, tag, owner)
{
m_cpu.set_tag(std::forward<T>(cpu));
}
u8 active_channels() const override;
};
class h8s_dma_device : public h8gen_dma_device
{
public:
h8s_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0);
template<typename T> h8s_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu)
: h8s_dma_device(mconfig, tag, owner)
{
m_cpu.set_tag(std::forward<T>(cpu));
}
u8 dmawer_r();
void dmawer_w(u8 data);
u8 dmatcr_r();
void dmatcr_w(u8 data);
u16 dmabcr_r();
void dmabcr_w(offs_t offset, u16 data, u16 mem_mask = ~0);
void channel_done(int id);
int channel_mode(int id, bool block) const;
std::tuple<bool, bool, bool> get_fae_dtie_dta(int id) const;
protected:
u8 m_dmawer, m_dmatcr;
u16 m_dmabcr;
void device_start() override;
void device_reset() override;
u8 active_channels() const override;
};
class h8gen_dma_channel_device : public device_t {
public:
enum {
NONE = -1,
DREQ_LEVEL = -2,
DREQ_EDGE = -3
NONE = 0,
DREQ_LEVEL = -1,
DREQ_EDGE = -2,
AUTOREQ_CS = -3,
AUTOREQ_B = -4,
};
enum {
MODE8_MEM_MEM,
MODE8_DACK_MEM,
MODE8_MEM_DACK,
MODE16_MEM_MEM,
MODE16_DACK_MEM,
MODE16_MEM_DACK
FAE_NORMAL,
FAE_BLOCK,
SAE,
SAE_DACK,
};
h8_dma_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
template<typename T, typename U, typename V> h8_dma_channel_device(const machine_config &mconfig, const char *tag, device_t *owner,
T &&cpu, U &&dma, V &&intc, int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8,
int v9 = h8_dma_channel_device::NONE,
int va = h8_dma_channel_device::NONE,
int vb = h8_dma_channel_device::NONE,
int vc = h8_dma_channel_device::NONE,
int vd = h8_dma_channel_device::NONE,
int ve = h8_dma_channel_device::NONE,
int vf = h8_dma_channel_device::NONE)
: h8_dma_channel_device(mconfig, tag, owner, 0)
h8_dma_state m_state[2];
h8gen_dma_channel_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
u16 marah_r();
void marah_w(offs_t offset, u16 data, u16 mem_mask = ~0);
u16 maral_r();
void maral_w(offs_t offset, u16 data, u16 mem_mask = ~0);
u16 ioara_r();
u8 ioara8_r();
void ioara_w(offs_t offset, u16 data, u16 mem_mask = ~0);
void ioara8_w(u8 data);
u16 etcra_r();
void etcra_w(offs_t offset, u16 data, u16 mem_mask = ~0);
u16 marbh_r();
void marbh_w(offs_t offset, u16 data, u16 mem_mask = ~0);
u16 marbl_r();
void marbl_w(offs_t offset, u16 data, u16 mem_mask = ~0);
u16 ioarb_r();
u8 ioarb8_r();
void ioarb_w(offs_t offset, u16 data, u16 mem_mask = ~0);
void ioarb8_w(u8 data);
u16 etcrb_r();
void etcrb_w(offs_t offset, u16 data, u16 mem_mask = ~0);
void set_id(int id);
void count_done(int submodule);
void start_stop_test();
bool transfer_test_interrupt(int vector);
void set_dreq(int state);
void start(int submodule);
protected:
required_device<h8_device> m_cpu;
required_device<h8_intc_device> m_intc;
int m_irq_base;
u32 m_ioar_mask; // ff0000 for h8s, ffff00 for h8h
u32 m_mar[2];
u16 m_ioar[2], m_etcr[2];
bool m_dreq;
virtual void device_start() override;
virtual void device_reset() override;
virtual void dma_done(int subchannel);
virtual int channel_mode() const = 0;
virtual u16 channel_flags(int submodule) const = 0;
virtual s8 trigger_vector(int submodule) const = 0;
};
class h8h_dma_channel_device : public h8gen_dma_channel_device
{
public:
h8h_dma_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0);
template<typename T, typename U, typename V> h8h_dma_channel_device(const machine_config &mconfig, const char *tag, device_t *owner,
T &&cpu, U &&dma, V &&intc, bool has_adc, bool targets_sci1)
: h8h_dma_channel_device(mconfig, tag, owner)
{
m_cpu.set_tag(std::forward<T>(cpu));
m_dma.set_tag(std::forward<U>(dma));
m_intc.set_tag(std::forward<V>(intc));
set_info(irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf);
m_has_adc = has_adc;
m_targets_sci1 = targets_sci1;
}
void set_info(int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf);
uint16_t marah_r();
void marah_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t maral_r();
void maral_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t ioara_r();
uint8_t ioara8_r();
void ioara_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void ioara8_w(uint8_t data);
uint16_t etcra_r();
void etcra_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t marbh_r();
void marbh_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t marbl_r();
void marbl_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t ioarb_r();
uint8_t ioarb8_r();
void ioarb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void ioarb8_w(uint8_t data);
uint16_t etcrb_r();
void etcrb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t dmacr_r();
void dmacr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
u8 dtcra_r();
void dtcra_w(u8 data);
u8 dtcrb_r();
void dtcrb_w(u8 data);
// H8H DMA
uint8_t dtcra_r();
void dtcra_w(uint8_t data);
uint8_t dtcrb_r();
void dtcrb_w(uint8_t data);
u8 active_channels() const;
void set_id(int id);
void set_bcr(bool fae, bool sae, uint8_t dta, uint8_t dte, uint8_t dtie);
bool start_test(int vector);
void count_last(int submodule);
void count_done(int submodule);
protected:
required_device<h8_device> m_cpu;
required_device<h8_dma_device> m_dma;
required_device<h8_intc_device> m_intc;
h8_dma_state m_state[2];
int m_irq_base;
required_device<h8h_dma_device> m_dma;
u8 m_dtcr[2];
bool m_has_adc;
bool m_targets_sci1;
int m_activation_vectors[16];
void device_start() override;
void device_reset() override;
void dma_done(int subchannel) override;
uint32_t m_mar[2];
uint16_t m_ioar[2], m_etcr[2], m_dmacr;
uint8_t m_dtcr[2]; // H8H
uint8_t m_dta, m_dte, m_dtie;
bool m_fae; // Full-Address Mode
bool m_sae; // Short-Address Mode
virtual void device_start() override;
virtual void device_reset() override;
void h8h_sync(); // call set_bcr with contents from DTCR
void start(int submodule);
int channel_mode() const override;
u16 channel_flags(int submodule) const override;
s8 trigger_vector(int submodule) const override;
};
DECLARE_DEVICE_TYPE(H8_DMA, h8_dma_device)
DECLARE_DEVICE_TYPE(H8_DMA_CHANNEL, h8_dma_channel_device)
class h8s_dma_channel_device : public h8gen_dma_channel_device
{
public:
h8s_dma_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0);
template<typename T, typename U, typename V> h8s_dma_channel_device(const machine_config &mconfig, const char *tag, device_t *owner,
T &&cpu, U &&dma, V &&intc)
: h8s_dma_channel_device(mconfig, tag, owner)
{
m_cpu.set_tag(std::forward<T>(cpu));
m_dma.set_tag(std::forward<U>(dma));
m_intc.set_tag(std::forward<V>(intc));
}
u16 dmacr_r();
void dmacr_w(offs_t offset, u16 data, u16 mem_mask = ~0);
protected:
u16 m_dmacr;
required_device<h8s_dma_device> m_dma;
void device_start() override;
void device_reset() override;
void dma_done(int subchannel) override;
int channel_mode() const override;
u16 channel_flags(int submodule) const override;
s8 trigger_vector(int submodule) const override;
};
DECLARE_DEVICE_TYPE(H8H_DMA_CHANNEL, h8h_dma_channel_device)
DECLARE_DEVICE_TYPE(H8S_DMA_CHANNEL, h8s_dma_channel_device)
#endif // MAME_CPU_H8_H8_DMA_H

54
src/devices/cpu/h8/h8s2320.cpp
View File

@ -141,27 +141,29 @@ void h8s2320_device::map(address_map &map)
map(0xfffec4, 0xfffecd).rw(m_intc, FUNC(h8s_intc_device::ipr_r), FUNC(h8s_intc_device::ipr_w));
map(0xfffece, 0xfffece).rw(m_intc, FUNC(h8s_intc_device::iprk_r), FUNC(h8s_intc_device::iprk_w));
map(0xfffee0, 0xfffee1).rw(m_dma0, FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
map(0xfffee2, 0xfffee3).rw(m_dma0, FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
map(0xfffee4, 0xfffee5).rw(m_dma0, FUNC(h8_dma_channel_device::ioara_r), FUNC(h8_dma_channel_device::ioara_w));
map(0xfffee6, 0xfffee7).rw(m_dma0, FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
map(0xfffee8, 0xfffee9).rw(m_dma0, FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
map(0xfffeea, 0xfffeeb).rw(m_dma0, FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
map(0xfffeec, 0xfffeed).rw(m_dma0, FUNC(h8_dma_channel_device::ioarb_r), FUNC(h8_dma_channel_device::ioarb_w));
map(0xfffeee, 0xfffeef).rw(m_dma0, FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
map(0xfffef0, 0xfffef1).rw(m_dma1, FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
map(0xfffef2, 0xfffef3).rw(m_dma1, FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
map(0xfffef4, 0xfffef5).rw(m_dma1, FUNC(h8_dma_channel_device::ioara_r), FUNC(h8_dma_channel_device::ioara_w));
map(0xfffef6, 0xfffef7).rw(m_dma1, FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
map(0xfffef8, 0xfffef9).rw(m_dma1, FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
map(0xfffefa, 0xfffefb).rw(m_dma1, FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
map(0xfffefc, 0xfffefd).rw(m_dma1, FUNC(h8_dma_channel_device::ioarb_r), FUNC(h8_dma_channel_device::ioarb_w));
map(0xfffefe, 0xfffeff).rw(m_dma1, FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
map(0xffff00, 0xffff00).rw(m_dma, FUNC(h8_dma_device::dmawer_r), FUNC(h8_dma_device::dmawer_w));
map(0xffff01, 0xffff01).rw(m_dma, FUNC(h8_dma_device::dmatcr_r), FUNC(h8_dma_device::dmatcr_w));
map(0xffff02, 0xffff03).rw(m_dma0, FUNC(h8_dma_channel_device::dmacr_r), FUNC(h8_dma_channel_device::dmacr_w));
map(0xffff04, 0xffff05).rw(m_dma1, FUNC(h8_dma_channel_device::dmacr_r), FUNC(h8_dma_channel_device::dmacr_w));
map(0xffff06, 0xffff07).rw(m_dma, FUNC(h8_dma_device::dmabcr_r), FUNC(h8_dma_device::dmabcr_w));
if(type() != H8S2321) {
map(0xfffee0, 0xfffee1).rw(m_dma0, FUNC(h8s_dma_channel_device::marah_r), FUNC(h8s_dma_channel_device::marah_w));
map(0xfffee2, 0xfffee3).rw(m_dma0, FUNC(h8s_dma_channel_device::maral_r), FUNC(h8s_dma_channel_device::maral_w));
map(0xfffee4, 0xfffee5).rw(m_dma0, FUNC(h8s_dma_channel_device::ioara_r), FUNC(h8s_dma_channel_device::ioara_w));
map(0xfffee6, 0xfffee7).rw(m_dma0, FUNC(h8s_dma_channel_device::etcra_r), FUNC(h8s_dma_channel_device::etcra_w));
map(0xfffee8, 0xfffee9).rw(m_dma0, FUNC(h8s_dma_channel_device::marbh_r), FUNC(h8s_dma_channel_device::marbh_w));
map(0xfffeea, 0xfffeeb).rw(m_dma0, FUNC(h8s_dma_channel_device::marbl_r), FUNC(h8s_dma_channel_device::marbl_w));
map(0xfffeec, 0xfffeed).rw(m_dma0, FUNC(h8s_dma_channel_device::ioarb_r), FUNC(h8s_dma_channel_device::ioarb_w));
map(0xfffeee, 0xfffeef).rw(m_dma0, FUNC(h8s_dma_channel_device::etcrb_r), FUNC(h8s_dma_channel_device::etcrb_w));
map(0xfffef0, 0xfffef1).rw(m_dma1, FUNC(h8s_dma_channel_device::marah_r), FUNC(h8s_dma_channel_device::marah_w));
map(0xfffef2, 0xfffef3).rw(m_dma1, FUNC(h8s_dma_channel_device::maral_r), FUNC(h8s_dma_channel_device::maral_w));
map(0xfffef4, 0xfffef5).rw(m_dma1, FUNC(h8s_dma_channel_device::ioara_r), FUNC(h8s_dma_channel_device::ioara_w));
map(0xfffef6, 0xfffef7).rw(m_dma1, FUNC(h8s_dma_channel_device::etcra_r), FUNC(h8s_dma_channel_device::etcra_w));
map(0xfffef8, 0xfffef9).rw(m_dma1, FUNC(h8s_dma_channel_device::marbh_r), FUNC(h8s_dma_channel_device::marbh_w));
map(0xfffefa, 0xfffefb).rw(m_dma1, FUNC(h8s_dma_channel_device::marbl_r), FUNC(h8s_dma_channel_device::marbl_w));
map(0xfffefc, 0xfffefd).rw(m_dma1, FUNC(h8s_dma_channel_device::ioarb_r), FUNC(h8s_dma_channel_device::ioarb_w));
map(0xfffefe, 0xfffeff).rw(m_dma1, FUNC(h8s_dma_channel_device::etcrb_r), FUNC(h8s_dma_channel_device::etcrb_w));
map(0xffff00, 0xffff00).rw(m_dma, FUNC(h8s_dma_device::dmawer_r), FUNC(h8s_dma_device::dmawer_w));
map(0xffff01, 0xffff01).rw(m_dma, FUNC(h8s_dma_device::dmatcr_r), FUNC(h8s_dma_device::dmatcr_w));
map(0xffff02, 0xffff03).rw(m_dma0, FUNC(h8s_dma_channel_device::dmacr_r), FUNC(h8s_dma_channel_device::dmacr_w));
map(0xffff04, 0xffff05).rw(m_dma1, FUNC(h8s_dma_channel_device::dmacr_r), FUNC(h8s_dma_channel_device::dmacr_w));
map(0xffff06, 0xffff07).rw(m_dma, FUNC(h8s_dma_device::dmabcr_r), FUNC(h8s_dma_device::dmabcr_w));
}
map(0xffff2c, 0xffff2c).rw(m_intc, FUNC(h8s_intc_device::iscrh_r), FUNC(h8s_intc_device::iscrh_w));
map(0xffff2d, 0xffff2d).rw(m_intc, FUNC(h8s_intc_device::iscrl_r), FUNC(h8s_intc_device::iscrl_w));
map(0xffff2e, 0xffff2e).rw(m_intc, FUNC(h8s_intc_device::ier_r), FUNC(h8s_intc_device::ier_w));
@ -263,15 +265,15 @@ void h8s2320_device::map(address_map &map)
map(0xfffff8, 0xfffffb).rw(m_timer16_2, FUNC(h8_timer16_channel_device::tgr_r), FUNC(h8_timer16_channel_device::tgr_w));
}
// TODO: the 2321 doesn't have the dma subdevice
void h8s2320_device::device_add_mconfig(machine_config &config)
{
H8S_INTC(config, m_intc, *this);
H8_ADC_2320(config, m_adc, *this, m_intc, 28);
H8_DMA(config, m_dma, *this);
H8_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc, 72, h8_dma_channel_device::NONE, 28, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, 82, 81, 86, 85, 32, 40, 44, 48, 56, 60);
H8_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc, 74, h8_dma_channel_device::NONE, 28, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 82, 81, 86, 85, 32, 40, 44, 48, 56, 60);
if(type() != H8S2321) {
H8S_DMA(config, m_dma, *this);
H8S_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc);
H8S_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc);
}
H8_DTC(config, m_dtc, *this, m_intc, 24);
H8_PORT(config, m_port1, *this, h8_device::PORT_1, 0x00, 0x00);
H8_PORT(config, m_port2, *this, h8_device::PORT_2, 0x00, 0x00);

6
src/devices/cpu/h8/h8s2320.h
View File

@ -52,9 +52,9 @@ public:
protected:
required_device<h8s_intc_device> m_intc;
required_device<h8_adc_device> m_adc;
optional_device<h8_dma_device> m_dma;
optional_device<h8_dma_channel_device> m_dma0;
optional_device<h8_dma_channel_device> m_dma1;
optional_device<h8s_dma_device> m_dma;
optional_device<h8s_dma_channel_device> m_dma0;
optional_device<h8s_dma_channel_device> m_dma1;
required_device<h8_dtc_device> m_dtc;
required_device<h8_port_device> m_port1;
required_device<h8_port_device> m_port2;

27
src/devices/cpu/h8/h8s2357.cpp
View File

@ -14,6 +14,9 @@ h8s2357_device::h8s2357_device(const machine_config &mconfig, device_type type,
h8s2000_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h8s2357_device::map), this)),
m_intc(*this, "intc"),
m_adc(*this, "adc"),
m_dma(*this, "dma"),
m_dma0(*this, "dma:0"),
m_dma1(*this, "dma:1"),
m_port1(*this, "port1"),
m_port2(*this, "port2"),
m_port3(*this, "port3"),
@ -113,6 +116,27 @@ void h8s2357_device::map(address_map &map)
map(0xfffebf, 0xfffebf).w(m_portg, FUNC(h8_port_device::ddr_w));
map(0xfffec4, 0xfffecd).rw(m_intc, FUNC(h8s_intc_device::ipr_r), FUNC(h8s_intc_device::ipr_w));
map(0xfffece, 0xfffece).rw(m_intc, FUNC(h8s_intc_device::iprk_r), FUNC(h8s_intc_device::iprk_w));
map(0xfffee0, 0xfffee1).rw(m_dma0, FUNC(h8s_dma_channel_device::marah_r), FUNC(h8s_dma_channel_device::marah_w));
map(0xfffee2, 0xfffee3).rw(m_dma0, FUNC(h8s_dma_channel_device::maral_r), FUNC(h8s_dma_channel_device::maral_w));
map(0xfffee4, 0xfffee5).rw(m_dma0, FUNC(h8s_dma_channel_device::ioara_r), FUNC(h8s_dma_channel_device::ioara_w));
map(0xfffee6, 0xfffee7).rw(m_dma0, FUNC(h8s_dma_channel_device::etcra_r), FUNC(h8s_dma_channel_device::etcra_w));
map(0xfffee8, 0xfffee9).rw(m_dma0, FUNC(h8s_dma_channel_device::marbh_r), FUNC(h8s_dma_channel_device::marbh_w));
map(0xfffeea, 0xfffeeb).rw(m_dma0, FUNC(h8s_dma_channel_device::marbl_r), FUNC(h8s_dma_channel_device::marbl_w));
map(0xfffeec, 0xfffeed).rw(m_dma0, FUNC(h8s_dma_channel_device::ioarb_r), FUNC(h8s_dma_channel_device::ioarb_w));
map(0xfffeee, 0xfffeef).rw(m_dma0, FUNC(h8s_dma_channel_device::etcrb_r), FUNC(h8s_dma_channel_device::etcrb_w));
map(0xfffef0, 0xfffef1).rw(m_dma1, FUNC(h8s_dma_channel_device::marah_r), FUNC(h8s_dma_channel_device::marah_w));
map(0xfffef2, 0xfffef3).rw(m_dma1, FUNC(h8s_dma_channel_device::maral_r), FUNC(h8s_dma_channel_device::maral_w));
map(0xfffef4, 0xfffef5).rw(m_dma1, FUNC(h8s_dma_channel_device::ioara_r), FUNC(h8s_dma_channel_device::ioara_w));
map(0xfffef6, 0xfffef7).rw(m_dma1, FUNC(h8s_dma_channel_device::etcra_r), FUNC(h8s_dma_channel_device::etcra_w));
map(0xfffef8, 0xfffef9).rw(m_dma1, FUNC(h8s_dma_channel_device::marbh_r), FUNC(h8s_dma_channel_device::marbh_w));
map(0xfffefa, 0xfffefb).rw(m_dma1, FUNC(h8s_dma_channel_device::marbl_r), FUNC(h8s_dma_channel_device::marbl_w));
map(0xfffefc, 0xfffefd).rw(m_dma1, FUNC(h8s_dma_channel_device::ioarb_r), FUNC(h8s_dma_channel_device::ioarb_w));
map(0xfffefe, 0xfffeff).rw(m_dma1, FUNC(h8s_dma_channel_device::etcrb_r), FUNC(h8s_dma_channel_device::etcrb_w));
map(0xffff00, 0xffff00).rw(m_dma, FUNC(h8s_dma_device::dmawer_r), FUNC(h8s_dma_device::dmawer_w));
map(0xffff01, 0xffff01).rw(m_dma, FUNC(h8s_dma_device::dmatcr_r), FUNC(h8s_dma_device::dmatcr_w));
map(0xffff02, 0xffff03).rw(m_dma0, FUNC(h8s_dma_channel_device::dmacr_r), FUNC(h8s_dma_channel_device::dmacr_w));
map(0xffff04, 0xffff05).rw(m_dma1, FUNC(h8s_dma_channel_device::dmacr_r), FUNC(h8s_dma_channel_device::dmacr_w));
map(0xffff06, 0xffff07).rw(m_dma, FUNC(h8s_dma_device::dmabcr_r), FUNC(h8s_dma_device::dmabcr_w));
map(0xffff2c, 0xffff2c).rw(m_intc, FUNC(h8s_intc_device::iscrh_r), FUNC(h8s_intc_device::iscrh_w));
map(0xffff2d, 0xffff2d).rw(m_intc, FUNC(h8s_intc_device::iscrl_r), FUNC(h8s_intc_device::iscrl_w));
map(0xffff2e, 0xffff2e).rw(m_intc, FUNC(h8s_intc_device::ier_r), FUNC(h8s_intc_device::ier_w));
@ -213,6 +237,9 @@ void h8s2357_device::device_add_mconfig(machine_config &config)
{
H8S_INTC(config, m_intc, *this);
H8_ADC_2357(config, m_adc, *this, m_intc, 28);
H8S_DMA(config, m_dma, *this);
H8S_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc);
H8S_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc);
H8_PORT(config, m_port1, *this, h8_device::PORT_1, 0x00, 0x00);
H8_PORT(config, m_port2, *this, h8_device::PORT_2, 0x00, 0x00);
H8_PORT(config, m_port3, *this, h8_device::PORT_3, 0xc0, 0xc0);

4
src/devices/cpu/h8/h8s2357.h
View File

@ -28,6 +28,7 @@
#include "h8s2000.h"
#include "h8_intc.h"
#include "h8_adc.h"
#include "h8_dma.h"
#include "h8_port.h"
#include "h8_timer8.h"
#include "h8_timer16.h"
@ -44,6 +45,9 @@ public:
protected:
required_device<h8s_intc_device> m_intc;
required_device<h8_adc_device> m_adc;
required_device<h8s_dma_device> m_dma;
required_device<h8s_dma_channel_device> m_dma0;
required_device<h8s_dma_channel_device> m_dma1;
required_device<h8_port_device> m_port1;
required_device<h8_port_device> m_port2;
required_device<h8_port_device> m_port3;

28
src/devices/cpu/h8/h8s2655.cpp
View File

@ -10,6 +10,9 @@ h8s2655_device::h8s2655_device(const machine_config &mconfig, device_type type,
h8s2600_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h8s2655_device::map), this)),
m_intc(*this, "intc"),
m_adc(*this, "adc"),
m_dma(*this, "dma"),
m_dma0(*this, "dma:0"),
m_dma1(*this, "dma:1"),
m_port1(*this, "port1"),
m_port2(*this, "port2"),
m_port3(*this, "port3"),
@ -92,6 +95,28 @@ void h8s2655_device::map(address_map &map)
map(0xfffec2, 0xfffec2).rw(m_intc, FUNC(h8s_intc_device::icrc_r), FUNC(h8s_intc_device::icrc_w));
map(0xfffec4, 0xfffecd).rw(m_intc, FUNC(h8s_intc_device::ipr_r), FUNC(h8s_intc_device::ipr_w));
map(0xfffece, 0xfffece).rw(m_intc, FUNC(h8s_intc_device::iprk_r), FUNC(h8s_intc_device::iprk_w));
map(0xfffee0, 0xfffee1).rw(m_dma0, FUNC(h8s_dma_channel_device::marah_r), FUNC(h8s_dma_channel_device::marah_w));
map(0xfffee2, 0xfffee3).rw(m_dma0, FUNC(h8s_dma_channel_device::maral_r), FUNC(h8s_dma_channel_device::maral_w));
map(0xfffee4, 0xfffee5).rw(m_dma0, FUNC(h8s_dma_channel_device::ioara_r), FUNC(h8s_dma_channel_device::ioara_w));
map(0xfffee6, 0xfffee7).rw(m_dma0, FUNC(h8s_dma_channel_device::etcra_r), FUNC(h8s_dma_channel_device::etcra_w));
map(0xfffee8, 0xfffee9).rw(m_dma0, FUNC(h8s_dma_channel_device::marbh_r), FUNC(h8s_dma_channel_device::marbh_w));
map(0xfffeea, 0xfffeeb).rw(m_dma0, FUNC(h8s_dma_channel_device::marbl_r), FUNC(h8s_dma_channel_device::marbl_w));
map(0xfffeec, 0xfffeed).rw(m_dma0, FUNC(h8s_dma_channel_device::ioarb_r), FUNC(h8s_dma_channel_device::ioarb_w));
map(0xfffeee, 0xfffeef).rw(m_dma0, FUNC(h8s_dma_channel_device::etcrb_r), FUNC(h8s_dma_channel_device::etcrb_w));
map(0xfffef0, 0xfffef1).rw(m_dma1, FUNC(h8s_dma_channel_device::marah_r), FUNC(h8s_dma_channel_device::marah_w));
map(0xfffef2, 0xfffef3).rw(m_dma1, FUNC(h8s_dma_channel_device::maral_r), FUNC(h8s_dma_channel_device::maral_w));
map(0xfffef4, 0xfffef5).rw(m_dma1, FUNC(h8s_dma_channel_device::ioara_r), FUNC(h8s_dma_channel_device::ioara_w));
map(0xfffef6, 0xfffef7).rw(m_dma1, FUNC(h8s_dma_channel_device::etcra_r), FUNC(h8s_dma_channel_device::etcra_w));
map(0xfffef8, 0xfffef9).rw(m_dma1, FUNC(h8s_dma_channel_device::marbh_r), FUNC(h8s_dma_channel_device::marbh_w));
map(0xfffefa, 0xfffefb).rw(m_dma1, FUNC(h8s_dma_channel_device::marbl_r), FUNC(h8s_dma_channel_device::marbl_w));
map(0xfffefc, 0xfffefd).rw(m_dma1, FUNC(h8s_dma_channel_device::ioarb_r), FUNC(h8s_dma_channel_device::ioarb_w));
map(0xfffefe, 0xfffeff).rw(m_dma1, FUNC(h8s_dma_channel_device::etcrb_r), FUNC(h8s_dma_channel_device::etcrb_w));
map(0xffff00, 0xffff00).rw(m_dma, FUNC(h8s_dma_device::dmawer_r), FUNC(h8s_dma_device::dmawer_w));
map(0xffff01, 0xffff01).rw(m_dma, FUNC(h8s_dma_device::dmatcr_r), FUNC(h8s_dma_device::dmatcr_w));
map(0xffff02, 0xffff03).rw(m_dma0, FUNC(h8s_dma_channel_device::dmacr_r), FUNC(h8s_dma_channel_device::dmacr_w));
map(0xffff04, 0xffff05).rw(m_dma1, FUNC(h8s_dma_channel_device::dmacr_r), FUNC(h8s_dma_channel_device::dmacr_w));
map(0xffff06, 0xffff07).rw(m_dma, FUNC(h8s_dma_device::dmabcr_r), FUNC(h8s_dma_device::dmabcr_w));
map(0xffff2c, 0xffff2c).rw(m_intc, FUNC(h8s_intc_device::iscrh_r), FUNC(h8s_intc_device::iscrh_w));
map(0xffff2d, 0xffff2d).rw(m_intc, FUNC(h8s_intc_device::iscrl_r), FUNC(h8s_intc_device::iscrl_w));
map(0xffff2e, 0xffff2e).rw(m_intc, FUNC(h8s_intc_device::ier_r), FUNC(h8s_intc_device::ier_w));
@ -192,6 +217,9 @@ void h8s2655_device::device_add_mconfig(machine_config &config)
{
H8S_INTC(config, m_intc, *this);
H8_ADC_2655(config, m_adc, *this, m_intc, 28);
H8S_DMA(config, m_dma, *this);
H8S_DMA_CHANNEL(config, m_dma0, *this, m_dma, m_intc);
H8S_DMA_CHANNEL(config, m_dma1, *this, m_dma, m_intc);
H8_PORT(config, m_port1, *this, h8_device::PORT_1, 0x00, 0x00);
H8_PORT(config, m_port2, *this, h8_device::PORT_2, 0x00, 0x00);
H8_PORT(config, m_port3, *this, h8_device::PORT_3, 0xc0, 0xc0);

4
src/devices/cpu/h8/h8s2655.h
View File

@ -20,6 +20,7 @@
#include "h8s2600.h"
#include "h8_intc.h"
#include "h8_adc.h"
#include "h8_dma.h"
#include "h8_port.h"
#include "h8_timer8.h"
#include "h8_timer16.h"
@ -36,6 +37,9 @@ public:
protected:
required_device<h8s_intc_device> m_intc;
required_device<h8_adc_device> m_adc;
required_device<h8s_dma_device> m_dma;
required_device<h8s_dma_channel_device> m_dma0;
required_device<h8s_dma_channel_device> m_dma1;
required_device<h8_port_device> m_port1;
required_device<h8_port_device> m_port2;
required_device<h8_port_device> m_port3;

1
src/devices/machine/t10mmc.cpp
View File

@ -927,7 +927,6 @@ void t10mmc::ReadData( uint8_t *data, int dataLength )
break;
case T10MMC_CMD_READ_DISC_STRUCTURE:
m_device->machine().debug_break();
m_device->logerror("T10MMC: READ DISC STRUCTURE, data\n");
data[0] = data[1] = 0;
data[2] = data[3] = 0;

2
src/devices/video/zr36110.cpp
View File

@ -301,7 +301,7 @@ void zr36110_device::cmdx_w(u16 data)
void zr36110_device::dma8_w(u8 data)
{
logerror("dna %02x\n", data);
// logerror("dma %02x\n", data);
}
void zr36110_device::dma_w(u16 data)

53
src/mame/nichibutsu/hrdvd.cpp
View File

@ -97,8 +97,14 @@ public:
uint16_t m_mux_data;
uint8_t m_p5, m_pa, m_pb;
uint8_t m_p6, m_pa, m_pb;
bool m_mpeg_dreq;
void mpeg_dreq_w(int state);
uint16_t p6_r();
void p6_w(uint16_t data);
uint16_t pb_r();
void pb_w(uint16_t data);
void pa_w(uint16_t data);
@ -113,6 +119,7 @@ public:
void ata_irq(int state);
void ata_drq(int state);
virtual void machine_start() override;
virtual void machine_reset() override;
void general_init(int patchaddress, int patchvalue);
@ -124,6 +131,29 @@ public:
static void dvdrom_config(device_t *device);
};
void hrdvd_state::mpeg_dreq_w(int state)
{
m_mpeg_dreq = state;
m_subcpu->set_input_line(H8_INPUT_LINE_DREQ0, m_mpeg_dreq && !(m_p6 & 0x04));
}
uint16_t hrdvd_state::p6_r()
{
return m_p6;
}
void hrdvd_state::p6_w(uint16_t data)
{
u8 delta = data ^ m_p6;
m_p6 = data;
if(delta & 0x02)
m_mpeg->reset();
m_subcpu->set_input_line(H8_INPUT_LINE_DREQ0, m_mpeg_dreq && !(m_p6 & 0x04));
logerror("p6 %02x\n", m_p6);
}
uint16_t hrdvd_state::pb_r()
{
return m_pb;
@ -241,17 +271,15 @@ void hrdvd_state::hrdvd_sub_map(address_map &map)
map(0x040018, 0x040019).rw(m_ata, FUNC(hrdvd_ata_controller_device::dma_read), FUNC(hrdvd_ata_controller_device::dma_write));
map(0x040028, 0x04002f).rw(m_ata, FUNC(hrdvd_ata_controller_device::read), FUNC(hrdvd_ata_controller_device::write));
map(0x060000, 0x06bfff).ram();
map(0x078000, 0x07ffff).mirror(0xf80000).ram(); //.share("nvram");
map(0x060000, 0x07ffff).mirror(0xf80000).ram(); //.share("nvram");
}
void hrdvd_state::hrdvd_sub_io_map(address_map &map)
{
map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(hrdvd_state::p6_r), FUNC(hrdvd_state::p6_w));
map(h8_device::PORT_A, h8_device::PORT_A).w (FUNC(hrdvd_state::pa_w));
map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(hrdvd_state::pb_r), FUNC(hrdvd_state::pb_w));
// map(h8_device::PORT_6, h8_device::PORT_6).noprw();
}
@ -402,11 +430,22 @@ static INPUT_PORTS_START( hrdvd )
INPUT_PORTS_END
void hrdvd_state::machine_start()
{
save_item(NAME(m_mux_data));
save_item(NAME(m_p6));
save_item(NAME(m_pa));
save_item(NAME(m_pb));
save_item(NAME(m_mpeg_dreq));
}
void hrdvd_state::machine_reset()
{
m_p5 = 0;
m_mux_data = 0;
m_p6 = 0;
m_pa = 0;
m_pb = 0;
m_mpeg_dreq = false;
}
void hrdvd_state::ata_irq(int state)
@ -474,7 +513,7 @@ void hrdvd_state::hrdvd(machine_config &config)
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
ZR36110(config, m_mpeg, 27_MHz_XTAL/2);
m_mpeg->drq_w().set_inputline(m_maincpu, H8_INPUT_LINE_DREQ0);
m_mpeg->drq_w().set(FUNC(hrdvd_state::mpeg_dreq_w));
NN71003F(config, m_mpega, 0);
m_mpega->add_route(0, m_lspeaker, 1.0);