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mips3: fix some bugs

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This commit is contained in:
Patrick Mackinlay 2022-02-15 19:26:17 +07:00
parent 406e442148
commit 3897034412
1 changed files with 6 additions and 10 deletions
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16
src/devices/cpu/mips/mips3.cpp
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@ -345,11 +345,9 @@ void mips3_device::generate_exception(int exception, int backup)
void mips3_device::generate_tlb_exception(int exception, offs_t address)
{
m_core->cpr[0][COP0_BadVAddr] = address;
if(exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE || exception == EXCEPTION_TLBLOAD_FILL || exception == EXCEPTION_TLBSTORE_FILL)
{
m_core->cpr[0][COP0_Context] = (m_core->cpr[0][COP0_Context] & 0xff800000) | ((address >> 9) & 0x007ffff0);
m_core->cpr[0][COP0_EntryHi] = (address & 0xffffe000) | (m_core->cpr[0][COP0_EntryHi] & 0xff);
}
m_core->cpr[0][COP0_Context] = (m_core->cpr[0][COP0_Context] & 0xff800000) | ((address >> 9) & 0x007ffff0);
m_core->cpr[0][COP0_EntryHi] = (address & 0xffffe000) | (m_core->cpr[0][COP0_EntryHi] & 0xff);
generate_exception(exception, 1);
}
@ -1720,7 +1718,7 @@ void mips3_device::set_cop0_reg(int idx, uint64_t val)
{
case COP0_Cause:
CAUSE = (CAUSE & 0xfc00) | (val & ~0xfc00);
if (CAUSE & 0x300)
if ((CAUSE & SR & 0x300) && (SR & SR_IE) && !(SR & (SR_EXL | SR_ERL)))
{
/* if we're in a delay slot, propogate the target PC before generating the exception */
if (m_nextpc != ~0)
@ -5208,9 +5206,8 @@ void mips3_device::execute_run()
m_core->llbit = 1;
if LL_BREAK
machine().debug_break();
break;
}
[[fallthrough]];
break;
case 0x31: /* LWC1 */
if (!(SR & SR_COP1))
{
@ -5231,9 +5228,8 @@ void mips3_device::execute_run()
m_core->llbit = 1;
if LL_BREAK
machine().debug_break();
break;
}
[[fallthrough]];
break;
case 0x35: /* LDC1 */
if (!(SR & SR_COP1))
{