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Updated to the latest source tree

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This commit is contained in:
Angelo Salese 2010-08-17 09:50:06 +00:00
parent 0829705164
commit 3951c85f8a
2 changed files with 34 additions and 2 deletions
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7
src/mame/drivers/aristmk5.c
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@ -5,7 +5,7 @@
Note: ARM250 mapping is not identical to plain AA
code DASMing of POST (Adonis):
code DASMing of POST (adonis):
- bp 0x3400224:
checks work RAM [0x87000], if bit 0 active high then all tests are ok, otherwise check what went wrong;
- bp 0x3400230: EPROM checksum branch test
@ -23,12 +23,15 @@
IRQA status bit 0, that's "printer busy" on original AA but here it have a completely
different meaning.
- bp 0x34002f8: DRAM emulator branch tests
bp 0x34002f4:
- R0 == 0 "DRAM emulator found"
- R0 == 1 "DRAM emulator found"
- R0 == 3 "DRAM emulator not found - Error"
- R0 == 4 "DRAM emulator found instead of DRAM - Error"
- R0 == x "Undefined error in DRAM emulator area"
It r/w RAM location 0 and it expects to NOT read-back value written.
goldprmd: checks if a "keyboard IRQ" fires (IRQ status B bit 6), returns an External Video Crystal Error (bp 3400278)
*/
@ -274,7 +277,7 @@ ROM_START( magicmsk )
ROM_REGION( 0x800000, "maincpu", 0 ) /* ARM Code */
ROM_LOAD32_WORD( "magicmsk.u7", 0x000000, 0x80000, CRC(17317eb9) SHA1(3ddb8d61f23461c3194af534928164550208bbee) )
ROM_LOAD32_WORD( "magicmsk.u11", 0x000002, 0x80000, CRC(23aefb5a) SHA1(ba4488754794f75f53b9c81b74b6ccd992c64acc) )
ROM_LOAD32_WORD( "magicmsk.u8", 0x100000, 0x80000, CRC(23aefb5a) SHA1(ba4488754794f75f53b9c81b74b6ccd992c64acc) )
ROM_LOAD32_WORD( "magicmsk.u8", 0x100000, 0x80000, BAD_DUMP CRC(971bbf63) SHA1(082f81115209c7089c76fb207248da3c347a080b) ) //same as dmdtouch u8 ROM
ROM_LOAD32_WORD( "magicmsk.u12", 0x100002, 0x80000, CRC(6829a7bf) SHA1(97eed83763d0ec5e753d6ad194e906b1307c4940) )
ROM_END

29
src/mame/machine/archimds.c
View File

@ -53,10 +53,13 @@ emu_timer *vbl_timer;
#define CONTROL 0
#define IRQ_STATUS_A 4
#define IRQ_REQUEST_A 5
#define IRQ_MASK_A 6
#define IRQ_STATUS_B 8
#define IRQ_REQUEST_B 9
#define IRQ_MASK_B 10
#define FIQ_STATUS 12
#define FIQ_REQUEST 13
#define FIQ_MASK 14
void archimedes_request_irq_a(running_machine *machine, int mask)
@ -347,6 +350,7 @@ READ32_HANDLER(archimedes_ioc_r)
#endif
if (offset*4 >= 0x200000 && offset*4 < 0x300000)
{
if(((offset & 0x1f) != 16) && ((offset & 0x1f) != 17) && ((offset & 0x1f) != 24) && ((offset & 0x1f) != 25))
logerror("IOC: R %s = %02x (PC=%x) %02x\n", ioc_regnames[offset&0x1f], ioc_regs[offset&0x1f], cpu_get_pc( space->cpu ),offset & 0x1f);
switch (offset & 0x1f)
@ -367,9 +371,30 @@ READ32_HANDLER(archimedes_ioc_r)
case IRQ_STATUS_A:
return (ioc_regs[IRQ_STATUS_A] & 0x7f) | 0x80; // Force IRQ is always '1'
case IRQ_REQUEST_A:
return (ioc_regs[IRQ_STATUS_A] & ioc_regs[IRQ_MASK_A]);
case IRQ_MASK_A:
return (ioc_regs[IRQ_MASK_A]);
case IRQ_STATUS_B:
return (ioc_regs[IRQ_STATUS_B]);
case IRQ_REQUEST_B:
return (ioc_regs[IRQ_STATUS_B] & ioc_regs[IRQ_MASK_B]);
case IRQ_MASK_B:
return (ioc_regs[IRQ_MASK_B]);
case FIQ_STATUS:
return (ioc_regs[FIQ_STATUS] & 0x7f) | 0x80; // Force FIQ is always '1'
case FIQ_REQUEST:
return (ioc_regs[FIQ_STATUS] & ioc_regs[FIQ_MASK]);
case FIQ_MASK:
return (ioc_regs[FIQ_MASK]);
case 16: // timer 0 read
return ioc_timerout[0]&0xff;
case 17:
@ -414,6 +439,7 @@ WRITE32_HANDLER(archimedes_ioc_w)
if (offset*4 >= 0x200000 && offset*4 < 0x300000)
{
if(((offset & 0x1f) != 16) && ((offset & 0x1f) != 17) && ((offset & 0x1f) != 24) && ((offset & 0x1f) != 25))
logerror("IOC: W %02x @ reg %s (PC=%x)\n", data&0xff, ioc_regnames[offset&0x1f], cpu_get_pc( space->cpu ));
switch (offset&0x1f)
@ -598,6 +624,9 @@ WRITE32_HANDLER(archimedes_vidc_w)
g = (val & 0x00f0) >> 4;
r = (val & 0x000f) >> 0;
if(reg == 0x40 && val & 0xfff)
logerror("WARNING: border color write here (PC=%08x)!\n",cpu_get_pc(space->cpu));
palette_set_color_rgb(space->machine, reg >> 2, pal4bit(r), pal4bit(g), pal4bit(b) );
}
else if (reg >= 0x80 && reg <= 0xbc)