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misc arcompact (nw)

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This commit is contained in:
mamehaze 2014-12-05 16:45:18 +00:00
parent ad547dff03
commit 39e127e9b2
1 changed files with 88 additions and 7 deletions
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95
src/emu/cpu/arcompact/arcompactdasm.c
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@ -100,13 +100,34 @@ static const char *conditions[0x20] =
/* 1f */ "0x1f Reserved"
};
static const char *table01_01_0x[0x10] =
{
/* 00 */ "BREQ",
/* 01 */ "BRNE",
/* 02 */ "BRLT",
/* 03 */ "BRGE",
/* 04 */ "BRLO",
/* 05 */ "BRHS",
/* 06 */ "<reserved>",
/* 07 */ "<reserved>",
/* 08 */ "<reserved>",
/* 09 */ "<reserved>",
/* 0a */ "<reserved>",
/* 0b */ "<reserved>",
/* 0c */ "<reserved>",
/* 0d */ "<reserved>",
/* 0e */ "<BBIT0>",
/* 0f */ "<BBIT1>"
};
#define ARCOMPACT_OPERATION ((op & 0xf800) >> 11)
CPU_DISASSEMBLE(arcompact)
{
int size = 2;
UINT32 op = oprom[0] | (oprom[1] << 8);
UINT32 op = oprom[2] | (oprom[3] << 8);
output = buffer;
UINT8 instruction = ARCOMPACT_OPERATION;
@ -115,34 +136,94 @@ CPU_DISASSEMBLE(arcompact)
{
size = 4;
op <<= 16;
op |= oprom[2] | (oprom[3] << 8);
op |= oprom[0] | (oprom[1] << 8);
switch (instruction)
{
case 0x00:
if (op & 0x00010000)
{ // Branch Unconditionally Far
// 00000 ssssssssss 1 SSSSSSSSSS N 0 TTTT
UINT32 address = (op & 0x07fe0000) >> 17;
// 00000 ssssssssss 1 SSSSSSSSSS N R TTTT
INT32 address = (op & 0x07fe0000) >> 17;
address |= ((op & 0x0000ffc0) >> 6) << 10;
address |= ((op & 0x0000000f) >> 0) << 20;
if (address & 0x800000) address = -(address&0x7fffff);
print("B %08x (%08x)", address<<1, op & ~0xffffffcf );
print("B %08x (%08x)", pc + (address *2) + 4, op & ~0xffffffcf );
}
else
{ // Branch Conditionally
// 00000 ssssssssss 0 SSSSSSSSSS N QQQQQ
UINT32 address = (op & 0x07fe0000) >> 17;
INT32 address = (op & 0x07fe0000) >> 17;
address |= ((op & 0x0000ffc0) >> 6) << 10;
if (address & 0x800000) address = -(address&0x7fffff);
UINT8 condition = op & 0x0000001f;
print("B(%s) %08x (%08x)", conditions[condition], address<<1, op & ~0xffffffdf );
print("B(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 4, op & ~0xffffffdf );
}
break;
case 0x01:
if (op & 0x00010000)
{
if (op & 0x00000010)
{ // Branch on Compare / Bit Test - Register-Immediate
// 00001 bbb sssssss 1 S BBB UUUUUU N 1 iiii
UINT8 subinstr = op & 0x0000000f;
INT32 address = (op & 0x00fe0000) >> 17;
address |= ((op & 0x00008000) >> 15) << 7;
if (address & 0x80) address = -(address&0x7f);
print("%s (reg-imm) %08x (%08x)", table01_01_0x[subinstr], pc + (address *2) + 4, op & ~0xf8fe800f);
}
else
{
// Branch on Compare / Bit Test - Register-Register
// 00001 bbb sssssss 1 S BBB CCCCCC N 0 iiii
UINT8 subinstr = op & 0x0000000f;
INT32 address = (op & 0x00fe0000) >> 17;
address |= ((op & 0x00008000) >> 15) << 7;
if (address & 0x80) address = -(address&0x7f);
print("%s (reg-reg) %08x (%08x)", table01_01_0x[subinstr], pc + (address *2) + 4, op & ~0xf8fe800f);
}
}
else
{
if (op & 0x00020000)
{ // Branch and Link Unconditionally Far
// 00001 sssssssss 10 SSSSSSSSSS N R TTTT
INT32 address = (op & 0x07fc0000) >> 17;
address |= ((op & 0x0000ffc0) >> 6) << 10;
address |= ((op & 0x0000000f) >> 0) << 20;
if (address & 0x800000) address = -(address&0x7fffff);
print("BL %08x (%08x)", pc + (address *2) + 4, op & ~0xffffffcf );
}
else
{ // Branch and Link Conditionally
// 00001 sssssssss 00 SSSSSSSSSS N QQQQQ
INT32 address = (op & 0x07fc0000) >> 17;
address |= ((op & 0x0000ffc0) >> 6) << 10;
if (address & 0x800000) address = -(address&0x7fffff);
UINT8 condition = op & 0x0000001f;
print("BL(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 4, op & ~0xffffffdf );
}
}
break;
default:
print("%s (%08x)", basic[instruction], op & ~0xf8000000 );
break;