From 3a20bc6fcef5c97def6fbdd2ecd0f0a0a5a3782e Mon Sep 17 00:00:00 2001 From: hap Date: Tue, 23 Feb 2021 16:46:05 +0100 Subject: [PATCH] hh_cops1: qkracerm ram is 8x12 --- src/devices/cpu/cops1/cops1base.cpp | 2 ++ src/devices/cpu/cops1/mm5799.cpp | 5 ++++- src/mame/drivers/hh_cops1.cpp | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/devices/cpu/cops1/cops1base.cpp b/src/devices/cpu/cops1/cops1base.cpp index 08f882df59c..540724e61c2 100644 --- a/src/devices/cpu/cops1/cops1base.cpp +++ b/src/devices/cpu/cops1/cops1base.cpp @@ -25,6 +25,8 @@ TODO: - documentation says that LB 10 is either 0 or 4, depending on RAM configuration, but on qkracerm it's 5 (also confirmed in patent source code), so I assume LB 10 is fully configurable as mask option +- MM5799 RAM layout is derived from MCU decap, documentation suggests that the + secondary option is literally 6x16 but according to the decap it's 4x16 + 4x8 */ diff --git a/src/devices/cpu/cops1/mm5799.cpp b/src/devices/cpu/cops1/mm5799.cpp index bffb5e64a66..7ea0ce4a1ff 100644 --- a/src/devices/cpu/cops1/mm5799.cpp +++ b/src/devices/cpu/cops1/mm5799.cpp @@ -29,11 +29,14 @@ void mm5799_device::data_map(address_map &map) // 8x12x4 for (int i = 0; i < 0x80; i += 0x10) map(i | 0x04, i | 0x0f).ram(); + map(0x00, 0x03).mirror(0x70).noprw(); } else { // 6x16x4 - map(0x00, 0x5f).ram(); + map(0x00, 0x3f).ram(); + for (int i = 0x40; i < 0x80; i += 0x10) + map(i | 0x00, i | 0x07).ram().mirror(0x08); } } diff --git a/src/mame/drivers/hh_cops1.cpp b/src/mame/drivers/hh_cops1.cpp index b83b1931fcc..e5d87f8fa3e 100644 --- a/src/mame/drivers/hh_cops1.cpp +++ b/src/mame/drivers/hh_cops1.cpp @@ -8,7 +8,6 @@ MCU die label for MM5799 games says MM4799, but they are in fact MM5799. TODO: - - qkracerm RAM configuration is unknown (it also works fine with 8x12) - qkracerm link cable ***************************************************************************/ @@ -399,6 +398,7 @@ void qkracerm_state::qkracerm(machine_config &config) { /* basic machine hardware */ MM5799(config, m_maincpu, 220000); // approximation + m_maincpu->set_option_ram_d12(true); m_maincpu->set_option_lb_10(5); m_maincpu->write_do().set(FUNC(qkracerm_state::write_do)); m_maincpu->write_s().set(FUNC(qkracerm_state::write_s));