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Clean-ups and version bump

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This commit is contained in:
Miodrag Milanovic 2012-07-02 07:06:11 +00:00
parent a78e9cf6cf
commit 3a36a15a02
30 changed files with 297 additions and 297 deletions
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6
src/emu/ioport.c
View File

@ -2650,13 +2650,13 @@ time_t ioport_manager::initialize()
int player_offset = 0;
for (device_t *device = iter.first(); device != NULL; device = iter.next())
{
int players = 0;
int players = 0;
for (ioport_port *port = first_port(); port != NULL; port = port->next())
{
if (&port->device()==device)
{
for (ioport_field *field = port->first_field(); field != NULL; field = field->next())
if (field->type_class()==INPUT_CLASS_CONTROLLER)
if (field->type_class()==INPUT_CLASS_CONTROLLER)
{
if (players < field->player() + 1) players = field->player() + 1;
field->set_player(field->player() + player_offset);
@ -3064,7 +3064,7 @@ g_profiler.start(PROFILER_INPUT);
ioport_value newvalue = port->read();
for (dynamic_field *dynfield = port->live().writelist.first(); dynfield != NULL; dynfield = dynfield->next())
if (dynfield->field().type() != IPT_OUTPUT)
dynfield->write(newvalue);
dynfield->write(newvalue);
}
g_profiler.stop();

14
src/emu/machine/pci.c
View File

@ -207,8 +207,8 @@ WRITE32_MEMBER( pci_bus_legacy_device::write )
READ64_MEMBER(pci_bus_legacy_device::read_64be)
{
READ64_MEMBER(pci_bus_legacy_device::read_64be)
{
UINT64 result = 0;
mem_mask = FLIPENDIAN_INT64(mem_mask);
if (ACCESSING_BITS_0_31)
@ -219,7 +219,7 @@ READ64_MEMBER(pci_bus_legacy_device::read_64be)
}
WRITE64_MEMBER(pci_bus_legacy_device::write_64be)
{
{
data = FLIPENDIAN_INT64(data);
mem_mask = FLIPENDIAN_INT64(mem_mask);
if (ACCESSING_BITS_0_31)
@ -420,8 +420,8 @@ WRITE32_MEMBER( pci_bus_device::write )
READ64_MEMBER(pci_bus_device::read_64be)
{
READ64_MEMBER(pci_bus_device::read_64be)
{
UINT64 result = 0;
mem_mask = FLIPENDIAN_INT64(mem_mask);
if (ACCESSING_BITS_0_31)
@ -432,7 +432,7 @@ READ64_MEMBER(pci_bus_device::read_64be)
}
WRITE64_MEMBER(pci_bus_device::write_64be)
{
{
data = FLIPENDIAN_INT64(data);
mem_mask = FLIPENDIAN_INT64(mem_mask);
if (ACCESSING_BITS_0_31)
@ -480,7 +480,7 @@ void pci_bus_device::device_start()
pci_connector *conn = downcast<pci_connector *>(subdevice(id));
if (conn!=NULL)
m_device[i] = conn->get_device();
else
else
m_device[i] = NULL;
}

30
src/emu/machine/pci.h
View File

@ -29,15 +29,15 @@ public:
DECLARE_READ64_MEMBER( read_64be );
DECLARE_WRITE64_MEMBER( write_64be );
void set_busnum(int busnum) { m_busnum = busnum; }
void set_father(const char *father) { m_father = father; }
void set_device(int num, const char *tag, pci_read_func read_func, pci_write_func write_func) {
void set_device(int num, const char *tag, pci_read_func read_func, pci_write_func write_func) {
m_devtag[num] = tag; m_read_callback[num] = read_func; m_write_callback[num] = write_func; }
pci_bus_legacy_device *pci_search_bustree(int busnum, int devicenum, pci_bus_legacy_device *pcibus);
void add_sibling(pci_bus_legacy_device *sibling, int busnum);
protected:
// device-level overrides
virtual void device_start();
@ -54,7 +54,7 @@ private:
pci_bus_legacy_device * m_siblings[8];
UINT8 m_siblings_busnum[8];
int m_siblings_count;
offs_t m_address;
INT8 m_devicenum; // device number we are addressing
INT8 m_busnumber; // pci bus number we are addressing
@ -80,7 +80,7 @@ extern const device_type PCI_BUS_LEGACY;
downcast<pci_bus_legacy_device *>(device)->set_father(_father_tag); \
// NEW IMPLEMENTATION
// NEW IMPLEMENTATION
//**************************************************************************
// TYPE DEFINITIONS
@ -95,14 +95,14 @@ public:
// construction/destruction
pci_device_interface(const machine_config &mconfig, device_t &device);
virtual ~pci_device_interface();
virtual UINT32 pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask) = 0;
virtual void pci_write(pci_bus_device *pcibus, int function, int offset, UINT32 data, UINT32 mem_mask) = 0;
virtual void pci_write(pci_bus_device *pcibus, int function, int offset, UINT32 data, UINT32 mem_mask) = 0;
private:
};
class pci_connector: public device_t,
public device_slot_interface
public device_slot_interface
{
public:
pci_connector(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
@ -129,15 +129,15 @@ public:
DECLARE_READ64_MEMBER( read_64be );
DECLARE_WRITE64_MEMBER( write_64be );
void set_busnum(int busnum) { m_busnum = busnum; }
void set_father(const char *father) { m_father = father; }
void set_device(int num, const char *tag) {
void set_device(int num, const char *tag) {
m_devtag[num] = tag; }
pci_bus_device *pci_search_bustree(int busnum, int devicenum, pci_bus_device *pcibus);
void add_sibling(pci_bus_device *sibling, int busnum);
protected:
// device-level overrides
virtual void device_start();
@ -154,7 +154,7 @@ private:
pci_bus_device * m_siblings[8];
UINT8 m_siblings_busnum[8];
int m_siblings_count;
offs_t m_address;
INT8 m_devicenum; // device number we are addressing
INT8 m_busnumber; // pci bus number we are addressing
@ -168,7 +168,7 @@ extern const device_type PCI_BUS;
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
#define MCFG_PCI_BUS_ADD(_tag, _busnum) \
MCFG_DEVICE_ADD(_tag, PCI_BUS, 0) \
downcast<pci_bus_device *>(device)->set_busnum(_busnum); \

246
src/emu/sound/qs1000.c
View File

@ -6,119 +6,119 @@
****************************************************************************
The QS1000 is a 32-voice wavetable synthesizer, believed to be based on
the OPTi 82C941. It contains an 8051 core, 256b of RAM and an (undumped)
internal program ROM. The internal ROM can be bypassed in favour of an
external ROM. Commands are issued to the chip via the 8051 serial port.
The QS1000 is a 32-voice wavetable synthesizer, believed to be based on
the OPTi 82C941. It contains an 8051 core, 256b of RAM and an (undumped)
internal program ROM. The internal ROM can be bypassed in favour of an
external ROM. Commands are issued to the chip via the 8051 serial port.
The QS1000 can access 24Mb of sample ROM. To reduce demand on the CPU,
instrument parameters such as playback rate, envelope and filter values
are encoded in ROM and directly accessed by the wavetable engine.
There are table entries for every note of every instrument.
The QS1000 can access 24Mb of sample ROM. To reduce demand on the CPU,
instrument parameters such as playback rate, envelope and filter values
are encoded in ROM and directly accessed by the wavetable engine.
There are table entries for every note of every instrument.
Registers
=========
Registers
=========
[200] = Key on/off
0 = Key on
1 = ?
2 = key off
[201] = Address byte 0 (LSB)
[202] = Address byte 1
[203] = Address byte 2
[204] = Pitch
[205] = Pitch high byte? (Usually 0)
[206] = Left volume
[207] = Right volume
[208] = Volume
[209] = ?
[20a] = ?
[20b] = ?
[20c] = ?
[20d] = Velocity
[20e] = Channel select
[20f] = Modulation
[210] = Modulation
[211] = 0 - Select global registers?
3 - Select channel registers?
[200] = Key on/off
0 = Key on
1 = ?
2 = key off
[201] = Address byte 0 (LSB)
[202] = Address byte 1
[203] = Address byte 2
[204] = Pitch
[205] = Pitch high byte? (Usually 0)
[206] = Left volume
[207] = Right volume
[208] = Volume
[209] = ?
[20a] = ?
[20b] = ?
[20c] = ?
[20d] = Velocity
[20e] = Channel select
[20f] = Modulation
[210] = Modulation
[211] = 0 - Select global registers?
3 - Select channel registers?
Velocity register values for MIDI range 0-127:
Velocity register values for MIDI range 0-127:
01 01 01 01 01 01 01 02 02 03 03 04 04 05 05 06
06 07 07 08 08 09 09 0A 0A 0B 0B 0C 0C 0D 0D 0E
0E 0F 10 11 11 12 13 14 14 15 16 17 17 18 19 1A
1A 1B 1C 1D 1D 1E 1F 20 20 21 22 23 23 24 25 26
26 27 28 29 29 2A 2B 2C 2C 2D 2E 2F 2F 30 31 32
35 38 3B 3E 41 44 47 4A 4D 50 4F 51 52 53 54 56
57 58 59 5B 5C 5D 5E 60 61 62 63 65 66 67 6A 6B
6C 6E 6F 70 71 73 74 75 76 78 79 7A 7B 7D 7E 7F
01 01 01 01 01 01 01 02 02 03 03 04 04 05 05 06
06 07 07 08 08 09 09 0A 0A 0B 0B 0C 0C 0D 0D 0E
0E 0F 10 11 11 12 13 14 14 15 16 17 17 18 19 1A
1A 1B 1C 1D 1D 1E 1F 20 20 21 22 23 23 24 25 26
26 27 28 29 29 2A 2B 2C 2C 2D 2E 2F 2F 30 31 32
35 38 3B 3E 41 44 47 4A 4D 50 4F 51 52 53 54 56
57 58 59 5B 5C 5D 5E 60 61 62 63 65 66 67 6A 6B
6C 6E 6F 70 71 73 74 75 76 78 79 7A 7B 7D 7E 7F
(TODO: Other register values)
(TODO: Other register values)
This is the sequence of register writes used to play the Iron Fortress credit sound:
This is the sequence of register writes used to play the Iron Fortress credit sound:
[211] 0 Select global registers?
[200] 1 ?
[203] d6 Address byte 2
[202] a9 Address byte 1
[201] 1 Address byte 0
[204] 80 Pitch
[205] 0 ?
[206] 80 Left volume
[207] 80 Right volume
[208] b3 Volume
[209] 0 ?
[20a] ff ?
[20b] 0 ?
[20c] 0 ?
[20d] 78 Velocity
[211] 3 Select channel registers
[20e] 0 Select channel
[200] 0 Key on
Sound Headers
=============
The address registers point to a 6 byte entry in the sound ROM:
[019be0]
097b 397f 1510
^ ^ ^
| | |
| | +----- Sound descriptor pointer
| +---------- ?
+--------------- Playback frequency (fixed point value representing 24MHz clock periods)
This in turn points to a 24 byte descriptor:
[1510]:
0 4502D 4508E 45F91 D0 7F 0F 2A 1F 90 00 FF
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
| | | | | | | | | | | |
| | | | | | | | | | | +-- ?
| | | | | | | | | | +----- ?
| | | | | | | | | +-------- ?
| | | | | | | | +----------- ?
| | | | | | | +-------------- ?
| | | | | | +----------------- Bit 7: Format (0:PCM 1:ADPCM)
| | | | | +-------------------- ?
| | | | +----------------------- ?
| | | +----------------------------- Loop end address
| | +----------------------------------- Loop start address
| +----------------------------------------- Start address
+------------------------------------------- Address most-significant nibble (shared with loop addresses)
* The unknown parameters are most likely envelope and filter parameters.
* Is there a loop flag or do sounds loop indefinitely until stopped?
[211] 0 Select global registers?
[200] 1 ?
[203] d6 Address byte 2
[202] a9 Address byte 1
[201] 1 Address byte 0
[204] 80 Pitch
[205] 0 ?
[206] 80 Left volume
[207] 80 Right volume
[208] b3 Volume
[209] 0 ?
[20a] ff ?
[20b] 0 ?
[20c] 0 ?
[20d] 78 Velocity
[211] 3 Select channel registers
[20e] 0 Select channel
[200] 0 Key on
TODO:
* Looping is currently disabled
* Figure out unknown sound header parameters
* Figure out and implement envelopes and filters
* Pitch bending
* Dump the internal ROM
Sound Headers
=============
The address registers point to a 6 byte entry in the sound ROM:
[019be0]
097b 397f 1510
^ ^ ^
| | |
| | +----- Sound descriptor pointer
| +---------- ?
+--------------- Playback frequency (fixed point value representing 24MHz clock periods)
This in turn points to a 24 byte descriptor:
[1510]:
0 4502D 4508E 45F91 D0 7F 0F 2A 1F 90 00 FF
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
| | | | | | | | | | | |
| | | | | | | | | | | +-- ?
| | | | | | | | | | +----- ?
| | | | | | | | | +-------- ?
| | | | | | | | +----------- ?
| | | | | | | +-------------- ?
| | | | | | +----------------- Bit 7: Format (0:PCM 1:ADPCM)
| | | | | +-------------------- ?
| | | | +----------------------- ?
| | | +----------------------------- Loop end address
| | +----------------------------------- Loop start address
| +----------------------------------------- Start address
+------------------------------------------- Address most-significant nibble (shared with loop addresses)
* The unknown parameters are most likely envelope and filter parameters.
* Is there a loop flag or do sounds loop indefinitely until stopped?
TODO:
* Looping is currently disabled
* Figure out unknown sound header parameters
* Figure out and implement envelopes and filters
* Pitch bending
* Dump the internal ROM
***************************************************************************/
#define ADDRESS_MAP_MODERN
@ -183,7 +183,7 @@ ADDRESS_MAP_END
// qs1000_device - constructor
//-------------------------------------------------
qs1000_device::qs1000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, QS1000, "QS1000", "qs1000", tag, owner, clock),
: device_t(mconfig, QS1000, "QS1000", "qs1000", tag, owner, clock),
device_sound_interface(mconfig, *this),
device_memory_interface(mconfig, *this),
m_space_config("samples", ENDIANNESS_LITTLE, 8, 24, 0, NULL),
@ -245,7 +245,7 @@ void qs1000_device::device_start()
//-------------------------------------------------
// serial_in - send data to the chip
// serial_in - send data to the chip
//-------------------------------------------------
void qs1000_device::serial_in(UINT8 data)
{
@ -258,7 +258,7 @@ void qs1000_device::serial_in(UINT8 data)
//-------------------------------------------------
// set_irq - interrupt the internal CPU
// set_irq - interrupt the internal CPU
//-------------------------------------------------
void qs1000_device::set_irq(int state)
{
@ -420,7 +420,7 @@ WRITE8_MEMBER( qs1000_device::wave_w )
// TODO
for (int i = 0; i < 16; ++i)
m_channels[ch].m_regs[i] = m_wave_regs[i];
// Key on
start_voice(ch);
}
@ -448,7 +448,7 @@ WRITE8_MEMBER( qs1000_device::wave_w )
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0d:
{
if (m_wave_regs[0x11] == 3)
{
@ -462,7 +462,7 @@ WRITE8_MEMBER( qs1000_device::wave_w )
}
break;
}
default:
m_wave_regs[offset] = data;
}
@ -470,14 +470,14 @@ WRITE8_MEMBER( qs1000_device::wave_w )
//-------------------------------------------------
// sound_stream_update -
// sound_stream_update -
//-------------------------------------------------
void qs1000_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
{
// Rset the output stream
memset(outputs[0], 0x0, samples * sizeof(*outputs[0]));
memset(outputs[1], 0x0, samples * sizeof(*outputs[1]));
// Iterate over voices and accumulate sample data
for (int ch = 0; ch < QS1000_CHANNELS; ch++)
{
@ -485,7 +485,7 @@ void qs1000_device::sound_stream_update(sound_stream &stream, stream_sample_t **
UINT8 lvol = chan.m_regs[6];
UINT8 rvol = chan.m_regs[7];
UINT8 vol = chan.m_regs[8];
UINT8 vol = chan.m_regs[8];
if (chan.m_flags & QS1000_PLAYING)
{
@ -503,8 +503,8 @@ void qs1000_device::sound_stream_update(sound_stream &stream, stream_sample_t **
else
#endif
{
chan.m_flags &= ~QS1000_PLAYING;
break;
chan.m_flags &= ~QS1000_PLAYING;
break;
}
}
@ -512,10 +512,10 @@ void qs1000_device::sound_stream_update(sound_stream &stream, stream_sample_t **
while (chan.m_start + chan.m_adpcm_addr != chan.m_addr)
{
chan.m_adpcm_addr++;
if (chan.m_start + chan.m_adpcm_addr >= chan.m_loop_end)
chan.m_adpcm_addr = chan.m_loop_start - chan.m_start;
UINT8 data = m_direct->read_raw_byte(chan.m_start + (chan.m_adpcm_addr >> 1));
UINT8 nibble = (chan.m_adpcm_addr & 1 ? data : data >> 4) & 0xf;
chan.m_adpcm_signal = chan.m_adpcm.clock(nibble);
@ -536,7 +536,7 @@ void qs1000_device::sound_stream_update(sound_stream &stream, stream_sample_t **
{
if (chan.m_addr >= chan.m_loop_end)
{
#if 0 // Looping disabled until envelopes work
#if 0 // Looping disabled until envelopes work
if (chan.m_flags & QS1000_KEYON)
{
chan.m_addr = chan.m_loop_start;
@ -544,8 +544,8 @@ void qs1000_device::sound_stream_update(sound_stream &stream, stream_sample_t **
else
#endif
{
chan.m_flags &= ~QS1000_PLAYING;
break;
chan.m_flags &= ~QS1000_PLAYING;
break;
}
}
@ -616,8 +616,8 @@ void qs1000_device::start_voice(int ch)
UINT8 byte12 = m_direct->read_raw_byte(base + 12);
UINT8 byte13 = m_direct->read_raw_byte(base + 13);
UINT8 byte14 = m_direct->read_raw_byte(base + 14);
UINT8 byte15 = m_direct->read_raw_byte(base + 15);
UINT8 byte15 = m_direct->read_raw_byte(base + 15);
printf("[%.6x] Sample Start:%.6x Loop Start:%.6x Loop End:%.6x Params: %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x\n", base, start_addr, loop_start, loop_end, byte8, byte9, byte10, byte11, byte12, byte13, byte14, byte15);
}
@ -633,7 +633,7 @@ void qs1000_device::start_voice(int ch)
{
m_channels[ch].m_adpcm.reset();
m_channels[ch].m_adpcm_addr = -1;
// m_channels[ch].m_adpcm_signal = -2;
// m_channels[ch].m_adpcm_signal = -2;
m_channels[ch].m_flags |= QS1000_ADPCM;
}
}
}

16
src/emu/sound/qs1000.h
View File

@ -88,21 +88,21 @@ public:
DECLARE_READ8_MEMBER( p0_r );
DECLARE_WRITE8_MEMBER( p0_w );
DECLARE_READ8_MEMBER( p1_r );
DECLARE_WRITE8_MEMBER( p1_w );
DECLARE_READ8_MEMBER( p2_r );
DECLARE_WRITE8_MEMBER( p2_w );
DECLARE_READ8_MEMBER( p3_r );
DECLARE_WRITE8_MEMBER( p3_w );
enum
{
QS1000_KEYON = 1,
QS1000_PLAYING = 2,
QS1000_ADPCM = 4,
QS1000_PLAYING = 2,
QS1000_ADPCM = 4,
};
void start_voice(int ch);
@ -118,10 +118,10 @@ public:
// Internal state
const address_space_config m_space_config;
sound_stream * m_stream;
sound_stream * m_stream;
direct_read_data * m_direct;
required_device<i8052_device> m_cpu;
// Wavetable engine
UINT8 m_serial_data_in;
UINT8 m_wave_regs[18];
@ -132,7 +132,7 @@ public:
INT32 m_adpcm_signal;
UINT32 m_start;
UINT32 m_addr;
UINT32 m_adpcm_addr;
UINT32 m_adpcm_addr;
UINT32 m_loop_start;
UINT32 m_loop_end;
UINT16 m_freq;

8
src/lib/formats/esq8_dsk.c
View File

@ -3,7 +3,7 @@
formats/esq8_dsk.c
Formats for 8-bit Ensoniq synthesizers and samplers
Disk is PC MFM, 40 tracks, single (Mirage) or double (SQ-80) sided,
with 6 sectors per track.
Sectors 0-4 are 1024 bytes, sector 5 is 512 bytes
@ -119,9 +119,9 @@ bool esq8img_format::load(io_generic *io, UINT32 form_factor, floppy_image *imag
int track_size = (5*1024) + 512;
for(int track=0; track < track_count; track++)
for(int track=0; track < track_count; track++)
{
for(int head=0; head < head_count; head++)
for(int head=0; head < head_count; head++)
{
io_generic_read(io, sectdata, (track*head_count + head)*track_size, track_size);
generate_track(esq_6_desc, track, head, sectors, sector_count, 109376, image);
@ -149,7 +149,7 @@ bool esq8img_format::save(io_generic *io, floppy_image *image)
sector_count = 6;
UINT8 sectdata[10*512];
int track_size = (5*1024) + 512;
int track_size = (5*1024) + 512;
for(int track=0; track < track_count; track++) {
for(int head=0; head < head_count; head++) {

2
src/lib/formats/esq8_dsk.h
View File

@ -3,7 +3,7 @@
formats/esq8_dsk.h
Formats for 8-bit Ensoniq synthesizers and samplers
Disk is PC MFM, 40 tracks, single (Mirage) or double (SQ-80) sided,
with 6 sectors per track.
Sectors 0-4 are 1024 bytes, sector 5 is 512 bytes

8
src/mame/drivers/8080bw.c
View File

@ -2516,7 +2516,7 @@ WRITE8_MEMBER(_8080bw_state::invmulti_eeprom_w)
// d6: reset
eeprom->set_cs_line((data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
// d4: write latch or select next bit to read
eeprom->set_clock_line((data & 0x10) ? ASSERT_LINE : CLEAR_LINE);
}
@ -2532,7 +2532,7 @@ WRITE8_MEMBER(_8080bw_state::invmulti_bank_w)
static MACHINE_RESET( invmulti )
{
_8080bw_state *state = machine.driver_data<_8080bw_state>();
state->invmulti_bank_w(*state->m_maincpu->memory().space(AS_PROGRAM), 0, 0);
MACHINE_RESET_CALL(mw8080bw);
@ -2543,9 +2543,9 @@ MACHINE_CONFIG_DERIVED_CLASS( invmulti, invaders, _8080bw_state )
/* basic machine hardware */
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(invmulti_map)
MCFG_EEPROM_93C46_8BIT_ADD("eeprom")
MCFG_MACHINE_RESET(invmulti)
MACHINE_CONFIG_END

12
src/mame/drivers/atlantis.c
View File

@ -8,7 +8,7 @@
* Midway Skins Game
* Midway Skins Game Tournament Edition (not dumped)
* Midway Swingers Tour (not dumped)
Hardware overview:
* VR4310 CPU (similar to the N64's VR4300)
* VR4373 "Nile 3" system controller / PCI bridge
@ -18,12 +18,12 @@
* Midway Zeus-series custom video
* TL16c552 dual UART
* ADSP-2181 based DCS2 audio (unclear which variant)
TODO:
* Proper VR4373 implementation
* Proper PCI bus implementation
* PCI peripherals
***************************************************************************/
#include "emu.h"
@ -50,7 +50,7 @@ public:
static MACHINE_START( mwskins )
{
// atlantis_state *state = machine.driver_data<atlantis_state>();
// atlantis_state *state = machine.driver_data<atlantis_state>();
/* set the fastest DRC options */
mips3drc_set_options(machine.device("maincpu"), MIPS3DRC_FASTEST_OPTIONS);
}
@ -173,7 +173,7 @@ MACHINE_CONFIG_END
ROM_START( mwskins )
ROM_REGION32_LE( 0x80000, "user1", 0 ) /* 512k for R4310 code */
ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
DISK_REGION( "drive_0" )
DISK_IMAGE( "mwskins", 0, SHA1(5cb293a6fdb2478293f48ddfc93cdd018acb2bb5) )
@ -181,7 +181,7 @@ ROM_END
ROM_START( mwskinsa )
ROM_REGION32_LE( 0x80000, "user1", 0 ) /* 512k for R4310 code */
ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
DISK_REGION( "drive_0" )
DISK_IMAGE( "mwskinsa", 0, SHA1(72497917b31156eb11a46bbcc6f22a254dcec044) )

2
src/mame/drivers/blitz68k.c
View File

@ -2807,7 +2807,7 @@ static DRIVER_INIT( cj3play )
// loop
ROM[0x2773c/2] = 0x4e71;
// ROM[0x3491a/2] = 0x4e71;
// ROM[0x3491a/2] = 0x4e71;
// ERROR CHECKSUM ROM PROGRAM
ROM[0x20ab0/2] = 0x6050;

4
src/mame/drivers/centiped.c
View File

@ -617,7 +617,7 @@ READ8_MEMBER(centiped_state::bullsdrt_data_port_r)
case 0x0033:
case 0x6b19:
return 0x01;
default:
break;
}
@ -873,7 +873,7 @@ WRITE8_MEMBER(centiped_state::multiped_prgbank_w)
{
m_prg_bank = bank;
multiped_gfxbank_w(space, 0, m_gfx_bank << 6);
// TODO: prg bankswitch and alt memory map layout for centiped
}
}

2
src/mame/drivers/cmmb.c
View File

@ -303,7 +303,7 @@ static INTERRUPT_GEN( cmmb_irq )
{
//if(device->machine().input().code_pressed_once(KEYCODE_Z))
//if(device->machine().input().code_pressed(KEYCODE_Z))
// device_set_input_line(device, 0, HOLD_LINE);
// device_set_input_line(device, 0, HOLD_LINE);
}
static MACHINE_RESET( cmmb )

10
src/mame/drivers/ddenlovr.c
View File

@ -3724,7 +3724,7 @@ READ8_MEMBER(dynax_state::daimyojn_keyb1_r)
else if (!BIT(m_keyb, 3)) val = ioport("KEY3")->read() | hopper_bit;
else if (!BIT(m_keyb, 4)) val = ioport("KEY4")->read() | hopper_bit;
// val |= ioport("BET")->read();
// val |= ioport("BET")->read();
return val;
}
@ -8563,7 +8563,7 @@ static const ay8910_interface quiz365_ay8910_interface =
{
AY8910_LEGACY_OUTPUT,
AY8910_DEFAULT_LOADS,
// A B
// A B
DEVCB_HANDLER(quiz365_input_r), DEVCB_NULL, // R
DEVCB_NULL, DEVCB_HANDLER(ddenlovr_select_w) // W
};
@ -8963,7 +8963,7 @@ static const ay8910_interface mjmyster_ay8910_interface =
{
AY8910_LEGACY_OUTPUT,
AY8910_DEFAULT_LOADS,
// A B
// A B
DEVCB_NULL, DEVCB_NULL, // R
DEVCB_NULL, DEVCB_HANDLER(ddenlovr_select_w) // W
};
@ -9035,7 +9035,7 @@ static const ay8910_interface hginga_ay8910_interface =
{
AY8910_LEGACY_OUTPUT,
AY8910_DEFAULT_LOADS,
// A B
// A B
DEVCB_HANDLER(hginga_dsw_r), DEVCB_NULL, // R
DEVCB_NULL, DEVCB_HANDLER(ddenlovr_select_w) // W
};
@ -9355,7 +9355,7 @@ static const ay8910_interface seljan2_ay8910_interface =
{
AY8910_LEGACY_OUTPUT,
AY8910_DEFAULT_LOADS,
// A B
// A B
DEVCB_HANDLER(seljan2_dsw_r), DEVCB_NULL, // R
DEVCB_NULL, DEVCB_HANDLER(ddenlovr_select_w) // W
};

4
src/mame/drivers/dec0.c
View File

@ -635,8 +635,8 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( secretab_map, AS_PROGRAM, 16, dec0_automat_state )
AM_RANGE(0x000000, 0x05ffff) AM_ROM
// AM_RANGE(0x240000, 0x240007) AM_DEVWRITE_LEGACY("tilegen2", deco_bac06_pf_control_0_w)
// AM_RANGE(0x240010, 0x240017) AM_DEVWRITE_LEGACY("tilegen2", deco_bac06_pf_control_1_w)
// AM_RANGE(0x240000, 0x240007) AM_DEVWRITE_LEGACY("tilegen2", deco_bac06_pf_control_0_w)
// AM_RANGE(0x240010, 0x240017) AM_DEVWRITE_LEGACY("tilegen2", deco_bac06_pf_control_1_w)
AM_RANGE(0x246000, 0x247fff) AM_DEVREADWRITE_LEGACY("tilegen2", deco_bac06_pf_data_r, deco_bac06_pf_data_w)
// AM_RANGE(0x240000, 0x24007f) AM_DEVREADWRITE_LEGACY("tilegen2", deco_bac06_pf_colscroll_r, deco_bac06_pf_colscroll_w)
// AM_RANGE(0x240400, 0x2407ff) AM_DEVREADWRITE_LEGACY("tilegen2", deco_bac06_pf_rowscroll_r, deco_bac06_pf_rowscroll_w)

110
src/mame/drivers/eolith.c
View File

@ -161,7 +161,7 @@ READ32_MEMBER(eolith_state::hidctch3_pen2_r)
WRITE32_MEMBER( eolith_state::sound_w )
{
// printf("CPU Command: %x\n", m_sound_data);
// printf("CPU Command: %x\n", m_sound_data);
m_sound_data = data;
m_soundcpu->set_input_line(MCS51_INT0_LINE, ASSERT_LINE);
@ -196,16 +196,16 @@ WRITE8_MEMBER( eolith_state::sound_p1_w )
*************************************/
/*
Possible port mapping:
Possible port mapping:
P30 (O) A16 (RxD)
P31 (O) A17 (TxD)
P32 (O) A18 (/INT0)
P33 (I) INT_68 (/INT1)
P34 (O) PCM1 (T0)
P35 (O) SET_INT (T1)
P36 (O) PCM0
P37 (O) RDB (/RD)
P30 (O) A16 (RxD)
P31 (O) A17 (TxD)
P32 (O) A18 (/INT0)
P33 (I) INT_68 (/INT1)
P34 (O) PCM1 (T0)
P35 (O) SET_INT (T1)
P36 (O) PCM0
P37 (O) RDB (/RD)
*/
READ8_MEMBER( eolith_state::qs1000_p1_r )
@ -225,12 +225,12 @@ WRITE8_MEMBER( eolith_state::qs1000_p1_w )
* Sound CPU <-> QS1000 CPU
*
*************************************/
static void soundcpu_to_qs1000(device_t *device, int data)
{
qs1000_device *qs1000 = device->machine().device<qs1000_device>("qs1000");
qs1000->serial_in(data);
device->machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(250));
}
@ -240,7 +240,7 @@ static void soundcpu_to_qs1000(device_t *device, int data)
* Main CPU memory map
*
*************************************/
static ADDRESS_MAP_START( eolith_map, AS_PROGRAM, 32, eolith_state )
AM_RANGE(0x00000000, 0x001fffff) AM_RAM // fort2b wants ram here
AM_RANGE(0x40000000, 0x401fffff) AM_RAM
@ -268,7 +268,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_io_map, AS_IO, 8, eolith_state )
AM_RANGE(0x0000, 0x7fff) AM_ROMBANK("sound_bank")
AM_RANGE(0x8000, 0x8000) AM_READ(sound_cmd_r)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(sound_p1_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(sound_p1_w)
ADDRESS_MAP_END
@ -277,7 +277,7 @@ ADDRESS_MAP_END
* Inputs
*
*************************************/
static INPUT_PORTS_START( common )
PORT_START("IN0")
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_START1 )
@ -549,7 +549,7 @@ static QS1000_INTERFACE( qs1000_intf )
{
/* External ROM */
true,
/* P1-P3 read handlers */
DEVCB_DRIVER_MEMBER(eolith_state, qs1000_p1_r),
DEVCB_NULL,
@ -582,9 +582,9 @@ static MACHINE_CONFIG_START( eolith45, eolith_state )
MCFG_EEPROM_ADD("eeprom", eeprom_interface_93C66)
// for testing sound sync
// MCFG_QUANTUM_PERFECT_CPU("maincpu")
// MCFG_QUANTUM_TIME(attotime::from_hz(6000))
// for testing sound sync
// MCFG_QUANTUM_PERFECT_CPU("maincpu")
// MCFG_QUANTUM_TIME(attotime::from_hz(6000))
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@ -694,9 +694,9 @@ ROM_START( ironfort )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "u108", 0x00000, 0x80000, CRC(89233144) SHA1(74e87679a7559450934b80fcfcb667d9845977a7) ) /* 27C040 eprom with no label */
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "u107", 0x0000, 0x8000, CRC(89450a2f) SHA1(d58efa805f497bec179fdbfb8c5860ac5438b4ec) ) /* 27C256 eprom with no label */
ROM_LOAD( "u107", 0x0000, 0x8000, CRC(89450a2f) SHA1(d58efa805f497bec179fdbfb8c5860ac5438b4ec) ) /* 27C256 eprom with no label */
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "u97", 0x00000, 0x80000, CRC(47b9d43a) SHA1(e0bc42892480cb563dc694fcefa8ca0b984749dd) ) /* 27C040 eprom with no label */
@ -744,12 +744,12 @@ ROM_START( linkypip )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "u108.bin", 0x00000, 0x80000, CRC(ca65856f) SHA1(f45868552389ccd637b5ccb1067b94e1226001ce) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "u107.bin", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_LOAD( "u107.bin", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "u97.bin", 0x00000, 0x80000, CRC(4465fe8d) SHA1(4d77169fff2fee5424e8da833088a544318b2981) )
ROM_LOAD( "u97.bin", 0x00000, 0x80000, CRC(4465fe8d) SHA1(4d77169fff2fee5424e8da833088a544318b2981) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -844,9 +844,9 @@ ROM_START( nhidctch )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "u108", 0x00000, 0x80000, CRC(2bae46cb) SHA1(7c43f1002dfc20b9c1bb1647f7261dfa7ed2b4f9) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "u107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_LOAD( "u107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "u97", 0x00000, 0x80000, CRC(ebf9f77b) SHA1(5d472aeb84fc011e19b9e61d34aeddfe7d6ac216) )
@ -923,15 +923,15 @@ ROM_START( hidctch2 )
ROM_REGION( 0x008000, "soundcpu", 0 ) /* AT89c52 */
/* This is the first 2K of hc2j.u111 from hidctch2a, verify against the internal dump when decapped */
ROM_LOAD( "hc2.103", 0x0000, 0x0800, BAD_DUMP CRC(92797034) SHA1(b600f19972986b2e09c56be0ea0c09f92a9fe422) ) /* MCU internal 2K flash */
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "u108", 0x00000, 0x80000, CRC(75fc7a65) SHA1(308715ab62d28787ee894ddcf7304464e2543b2e) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "u107", 0x0000, 0x8000, CRC(89450a2f) SHA1(d58efa805f497bec179fdbfb8c5860ac5438b4ec) )
ROM_LOAD( "u107", 0x0000, 0x8000, CRC(89450a2f) SHA1(d58efa805f497bec179fdbfb8c5860ac5438b4ec) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "u97", 0x00000, 0x80000, CRC(a7a1627e) SHA1(a93ced858d839daac1fa9a85f4f8c89cb179bad5) )
ROM_LOAD( "u97", 0x00000, 0x80000, CRC(a7a1627e) SHA1(a93ced858d839daac1fa9a85f4f8c89cb179bad5) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -962,12 +962,12 @@ ROM_START( hidctch2a )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "u108", 0x00000, 0x80000, CRC(75fc7a65) SHA1(308715ab62d28787ee894ddcf7304464e2543b2e) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "u107", 0x0000, 0x8000, CRC(89450a2f) SHA1(d58efa805f497bec179fdbfb8c5860ac5438b4ec) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "u97", 0x00000, 0x80000, CRC(a7a1627e) SHA1(a93ced858d839daac1fa9a85f4f8c89cb179bad5) )
ROM_LOAD( "u97", 0x00000, 0x80000, CRC(a7a1627e) SHA1(a93ced858d839daac1fa9a85f4f8c89cb179bad5) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -1053,12 +1053,12 @@ ROM_START( raccoon )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "racoon-u.108", 0x00000, 0x80000, CRC(fc4f30ee) SHA1(74b9e60cceb03ad572e0e080fbe1de5cffa1b2c3) )
ROM_REGION( 0x08000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "racoon-u.107", 0x0000, 0x8000, CRC(89450a2f) SHA1(d58efa805f497bec179fdbfb8c5860ac5438b4ec) )
ROM_LOAD( "racoon-u.107", 0x0000, 0x8000, CRC(89450a2f) SHA1(d58efa805f497bec179fdbfb8c5860ac5438b4ec) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "racoon-u.97", 0x00000, 0x80000, CRC(fef828b1) SHA1(38352b67d18300db40113df9426c2aceec12a29b) )
ROM_LOAD( "racoon-u.97", 0x00000, 0x80000, CRC(fef828b1) SHA1(38352b67d18300db40113df9426c2aceec12a29b) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -1091,12 +1091,12 @@ ROM_START( landbrk )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "rom2.u108", 0x00000, 0x80000, CRC(f3b327ef) SHA1(4b359171afd6ca10275961f795f3fe64f9df9897) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "lb.107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_LOAD( "lb.107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "lb_3.u97", 0x00000, 0x80000, CRC(5b34dff0) SHA1(1668763e977e272781ddcc74beba97b53477cc9d) )
ROM_LOAD( "lb_3.u97", 0x00000, 0x80000, CRC(5b34dff0) SHA1(1668763e977e272781ddcc74beba97b53477cc9d) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -1121,12 +1121,12 @@ ROM_START( landbrka )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "lb_2.108", 0x00000, 0x80000, CRC(a99182d7) SHA1(628c8d09efb3917a4e97d9e02b6b0ca1f339825d) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "lb.107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_LOAD( "lb.107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "lb_3.u97", 0x00000, 0x80000, CRC(5b34dff0) SHA1(1668763e977e272781ddcc74beba97b53477cc9d) )
ROM_LOAD( "lb_3.u97", 0x00000, 0x80000, CRC(5b34dff0) SHA1(1668763e977e272781ddcc74beba97b53477cc9d) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -1158,9 +1158,9 @@ ROM_START( penfan )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "pfg.u108", 0x00000, 0x80000, CRC(ac97c23b) SHA1(85319cbff811c84af2a802c2f609bd58cf9e7bc3) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "pfg.u107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_LOAD( "pfg.u107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "pfg.u97", 0x00000, 0x80000, CRC(0c713eef) SHA1(4c4ea19fec5af4f0cb983c8b9f71152d05c15047) )
@ -1196,12 +1196,12 @@ ROM_START( stealsee )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "ss.u108", 0x00000, 0x80000, CRC(95bd136d) SHA1(a6e2d75fc5e8d600d4dceab13c596f6a7edb6e72) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "ss.u107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "ss.u97", 0x00000, 0x80000, CRC(56c9f4a4) SHA1(dfc7cb8b68ec9e77854287b8998131e3ef4ca18d) )
ROM_LOAD( "ss.u97", 0x00000, 0x80000, CRC(56c9f4a4) SHA1(dfc7cb8b68ec9e77854287b8998131e3ef4ca18d) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -1270,9 +1270,9 @@ ROM_START( fort2b )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "3.u108", 0x00000, 0x80000, CRC(9b996b60) SHA1(c4e34601f754ae2908dd6d59ea9da0c5c6f56f2d) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "5.u107", 0x00000, 0x08000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_LOAD( "5.u107", 0x00000, 0x08000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sapmle ROMs */
ROM_LOAD( "2.u97", 0x00000, 0x80000, CRC(8a431b14) SHA1(5a9824280f30ef2e7b7f16652b2f9f9559cb764f) )
@ -1299,12 +1299,12 @@ ROM_START( fort2ba )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "ftii009.u108", 0x00000, 0x80000, CRC(9b996b60) SHA1(c4e34601f754ae2908dd6d59ea9da0c5c6f56f2d) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "ftii010.u107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_LOAD( "ftii010.u107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "ftii011.u97", 0x00000, 0x80000, CRC(8a431b14) SHA1(5a9824280f30ef2e7b7f16652b2f9f9559cb764f) )
ROM_LOAD( "ftii011.u97", 0x00000, 0x80000, CRC(8a431b14) SHA1(5a9824280f30ef2e7b7f16652b2f9f9559cb764f) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -1337,12 +1337,12 @@ ROM_START( puzzlekg )
ROM_REGION( 0x080000, "sounddata", 0 ) /* Music data */
ROM_LOAD( "u108.bin", 0x00000, 0x80000, CRC(e4555c6b) SHA1(128196a5b47d13ee7163981043b96f7b4b27204b) )
ROM_REGION( 0x008000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
ROM_LOAD( "u107.bin", 0x0000, 0x8000, CRC(f3add818) SHA1(96e77950154ced9f3234200de2aa29060c00d47f) )
ROM_LOAD( "u107.bin", 0x0000, 0x8000, CRC(f3add818) SHA1(96e77950154ced9f3234200de2aa29060c00d47f) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "u97.bin", 0x00000, 0x80000, CRC(f4604ce8) SHA1(e061b203ef5df386120dbf089ece094d16a1b59b) )
ROM_LOAD( "u97.bin", 0x00000, 0x80000, CRC(f4604ce8) SHA1(e061b203ef5df386120dbf089ece094d16a1b59b) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -1428,7 +1428,7 @@ ROM_START( hidctch3 )
ROM_LOAD( "u107", 0x0000, 0x8000, CRC(afd5263d) SHA1(71ace1b749d8a6b84d08b97185e7e512d04e4b8d) )
ROM_REGION( 0x1000000, "qs1000", 0 ) /* QDSP sample ROMs */
ROM_LOAD( "u97", 0x00000, 0x80000, CRC(6d37aa1a) SHA1(6827e500d9bf66e2e9236be563456ff88c78db91) )
ROM_LOAD( "u97", 0x00000, 0x80000, CRC(6d37aa1a) SHA1(6827e500d9bf66e2e9236be563456ff88c78db91) )
ROM_LOAD( "qs1001a.u96", 0x80000, 0x80000, CRC(d13c6407) SHA1(57b14f97c7d4f9b5d9745d3571a0b7115fbe3176) )
ROM_END
@ -1446,7 +1446,7 @@ static DRIVER_INIT( eolith )
// Sound CPU -> QS1000 CPU serial link
i8051_set_serial_tx_callback(machine.device("soundcpu"), soundcpu_to_qs1000);
// Configure the sound ROM banking
machine.root_device().membank("sound_bank")->configure_entries(0, 16, state->memregion("sounddata")->base(), 0x8000);
}
@ -1478,7 +1478,7 @@ static DRIVER_INIT( hidctch2 )
//it fails compares in memory like in landbrka
UINT32 *rombase = (UINT32*)machine.root_device().memregion("maincpu")->base();
rombase[0xbcc8/4] = (rombase[0xbcc8/4] & 0xffff) | 0x03000000; /* Change BR to NOP */
DRIVER_INIT_CALL(eolith);
}

6
src/mame/drivers/eolithsp.c
View File

@ -25,7 +25,7 @@ void eolith_speedup_read(address_space *space)
// printf("%s:eolith speedup_read data %02x\n",space->machine().describe_context(), eolith_vblank);
if (eolith_vblank==0 && eolith_scanline < eolith_speedup_resume_scanline)
{
{
int pc = cpu_get_pc(&space->device());
if ((pc==eolith_speedup_address) || (pc==eolith_speedup_address2))
@ -60,9 +60,9 @@ static const struct
{ "fort2ba", 0x000081e0, -1, 240 },
{ "penfan", 0x4001FA66, -1, 240 },
{ "candy", 0x4001990C, -1, 240 },
/* eolith16.c */
/* eolith16.c */
{ "klondkp", 0x0001a046, -1, 240 },
/* vegaeo.c */
/* vegaeo.c */
{ "crazywar", 0x00008cf8, -1, 240 },
{ NULL, 0, 0 }
};

4
src/mame/drivers/ghosteo.c
View File

@ -375,7 +375,7 @@ READ32_MEMBER( ghosteo_state::touryuu_port_10000000_r )
case 0xB : data = machine().root_device().ioport( "10000000-0B")->read(); break;
case 0xC : data = machine().root_device().ioport( "10000000-0C")->read(); break;
}
// logerror( "touryuu_port_10000000_r (%08X) -> %08X\n", port_g, data);
// logerror( "touryuu_port_10000000_r (%08X) -> %08X\n", port_g, data);
return data;
}
@ -729,4 +729,4 @@ static DRIVER_INIT( touryuu )
GAME( 2003, bballoon, 0, bballoon, bballoon, bballoon, ROT0, "Eolith", "BnB Arcade", GAME_NO_SOUND )
GAME( 2005, hapytour, 0, bballoon, bballoon, bballoon, ROT0, "GAV Company", "Happy Tour", GAME_NO_SOUND )
GAME( 2005, touryuu, 0, touryuu, touryuu, touryuu, ROT0, "Yuki Enterprise", "Touryuumon (V1.1)?", GAME_NO_SOUND ) // On first boot inputs won't work, TODO: hook-up default eeprom
GAME( 2005, touryuu, 0, touryuu, touryuu, touryuu, ROT0, "Yuki Enterprise", "Touryuumon (V1.1)?", GAME_NO_SOUND ) // On first boot inputs won't work, TODO: hook-up default eeprom

4
src/mame/drivers/igs011.c
View File

@ -748,8 +748,8 @@ static void nkishusp_decrypt(running_machine &machine)
// ryukobou xor:
// if ( (j & 0x00100) && (j & 0x00400) )
// x ^= 0x0200;
// if ( (j & 0x00100) && (j & 0x00400) )
// x ^= 0x0200;
if ( !(j & 0x00004) || !(j & 0x02000) || (!(j & 0x00080) && !(j & 0x00010) ) )
x ^= 0x0020;

24
src/mame/drivers/limenko.c
View File

@ -73,11 +73,11 @@ public:
DECLARE_READ32_MEMBER(sb2003_speedup_r);
DECLARE_READ32_MEMBER(spotty_speedup_r);
DECLARE_CUSTOM_INPUT_MEMBER(spriteram_bit_r);
DECLARE_READ8_MEMBER(qs1000_p1_r);
DECLARE_WRITE8_MEMBER(qs1000_p1_w);
DECLARE_WRITE8_MEMBER(qs1000_p2_w);
DECLARE_WRITE8_MEMBER(qs1000_p3_w);
DECLARE_WRITE8_MEMBER(qs1000_p3_w);
};
@ -164,12 +164,12 @@ WRITE32_MEMBER(limenko_state::spriteram_buffer_w)
WRITE32_MEMBER(limenko_state::limenko_soundlatch_w)
{
qs1000_device *qs1000 = machine().device<qs1000_device>("qs1000");
qs1000_device *qs1000 = machine().device<qs1000_device>("qs1000");
soundlatch_byte_w(space, 0, data >> 16);
qs1000->set_irq(ASSERT_LINE);
machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
}
WRITE32_MEMBER(limenko_state::spotty_soundlatch_w)
@ -178,7 +178,7 @@ WRITE32_MEMBER(limenko_state::spotty_soundlatch_w)
}
READ8_MEMBER(limenko_state::qs1000_p1_r)
{
{
return soundlatch_byte_r(space, 0);
}
@ -199,7 +199,7 @@ WRITE8_MEMBER(limenko_state::qs1000_p3_w)
// ..x. .... - /IRQ clear
qs1000_device *qs1000 = machine().device<qs1000_device>("qs1000");
membank("qs1000:bank")->set_entry(data & 0x07);
if (!BIT(data, 5))
@ -727,12 +727,12 @@ static QS1000_INTERFACE( qs1000_intf )
{
/* External ROM */
true,
/* P1-P3 read handlers */
DEVCB_DRIVER_MEMBER(limenko_state, qs1000_p1_r),
DEVCB_NULL,
DEVCB_NULL,
/* P1-P3 write handlers */
DEVCB_DRIVER_MEMBER(limenko_state, qs1000_p1_w),
DEVCB_DRIVER_MEMBER(limenko_state, qs1000_p2_w),
@ -1118,8 +1118,8 @@ static DRIVER_INIT( common )
// Set up the QS1000 program ROM banking, taking care not to overlap the internal RAM
machine.device("qs1000:cpu")->memory().space(AS_IO)->install_read_bank(0x0100, 0xffff, "bank");
state->membank("qs1000:bank")->configure_entries(0, 8, state->memregion("qs1000:cpu")->base()+0x100, 0x10000);
state->membank("qs1000:bank")->configure_entries(0, 8, state->memregion("qs1000:cpu")->base()+0x100, 0x10000);
state->m_spriteram_bit = 1;
}

6
src/mame/drivers/midvunit.c
View File

@ -719,7 +719,7 @@ static INPUT_PORTS_START( crusnwld )
PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:3")
PORT_DIPSETTING( 0x0020, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x0000, "Sitdown" )
PORT_DIPUNUSED_DIPLOC( 0x0040, 0x0040, "SW2:2" ) /* Manual shows Not Used */
PORT_DIPUNUSED_DIPLOC( 0x0040, 0x0040, "SW2:2" ) /* Manual shows Not Used */
PORT_SERVICE_DIPLOC( 0x0080, IP_ACTIVE_LOW, "SW2:1" )
/* DSW3 at U19 */
@ -834,7 +834,7 @@ static INPUT_PORTS_START( offroadc )
PORT_START("DSW")
/* DSW2 at U97 */
PORT_DIPUNUSED_DIPLOC( 0x0001, 0x0001, "SW2:8" ) /* Manual shows Not Used & "No Effect" for both On & Off */
PORT_DIPUNUSED_DIPLOC( 0x0001, 0x0001, "SW2:8" ) /* Manual shows Not Used & "No Effect" for both On & Off */
PORT_DIPNAME( 0x0002, 0x0000, "Gear Shifter Switch" ) PORT_DIPLOCATION("SW2:7")
PORT_DIPSETTING( 0x0002, "Normally Closed" )
PORT_DIPSETTING( 0x0000, "Normally Open" )
@ -844,7 +844,7 @@ static INPUT_PORTS_START( offroadc )
PORT_DIPNAME( 0x0008, 0x0008, "Graphic Effects" ) PORT_DIPLOCATION("SW2:5")
PORT_DIPSETTING( 0x0008, "Roadkill Present" )
PORT_DIPSETTING( 0x0000, "Roadkill Missing" )
PORT_DIPUNUSED_DIPLOC( 0x0010, 0x0010, "SW2:4" ) /* Manual shows Not Used & "No Effect" for both On & Off */
PORT_DIPUNUSED_DIPLOC( 0x0010, 0x0010, "SW2:4" ) /* Manual shows Not Used & "No Effect" for both On & Off */
PORT_DIPNAME( 0x0020, 0x0020, "Link" ) PORT_DIPLOCATION("SW2:3")
PORT_DIPSETTING( 0x0020, "Disabled" )
PORT_DIPSETTING( 0x0000, "Enabled" )

2
src/mame/drivers/missile.c
View File

@ -1310,7 +1310,7 @@ static DRIVER_INIT( missilem )
{
int a = BITSWAP16(i, 15,2,3,0,8,9,7,5,1,4,6,14,13,12,10,11);
int d = BITSWAP8(src[a], 3,2,4,5,6,1,7,0);
a = i;
a ^= (~a >> 1 & 0x400);
a ^= (~a >> 4 & 0x100);

4
src/mame/drivers/pacman.c
View File

@ -798,7 +798,7 @@ READ8_MEMBER(pacman_state::rocktrv2_question_r)
/*
This is a kit that upgrades an original Midway Pacman PCB to allow it to run many Pacman games.
It includes two small PCBs and two PROMs. The large PCB plugs into the CPU socket at 6B and the
It includes two small PCBs and two PROMs. The large PCB plugs into the CPU socket at 6B and the
Sync Bus Controller socket at 6D. The CPU that was in the socket at 6B plugs into the Super ABC PCB.
The large PCB contains the following parts.....
@ -821,7 +821,7 @@ WRITE8_MEMBER(pacman_state::superabc_bank_w)
membank("bank1")->set_base(memregion("maincpu")->base() + bank * 0x10000 + 0x0000);
membank("bank2")->set_base(memregion("maincpu")->base() + bank * 0x10000 + 0x4000);
membank("bank3")->set_base(memregion("maincpu")->base() + bank * 0x10000 + 0xa000); // looks like a15 is not connected and a16-onwards is shifted 1 bit
if (bank != m_charbank)
{
m_spritebank = bank;

8
src/mame/drivers/pgm2.c
View File

@ -12,10 +12,10 @@
PGM2 Motherboard Components:
IS61LV25616AL(SRAM)
IGS037(GFX PROCESSOR)
YMZ774-S(SOUND)
R5F21256SN(extra MCU for protection and ICcard communication)
IS61LV25616AL(SRAM)
IGS037(GFX PROCESSOR)
YMZ774-S(SOUND)
R5F21256SN(extra MCU for protection and ICcard communication)
*/

26
src/mame/drivers/vamphalf.c
View File

@ -95,7 +95,7 @@ public:
UINT8 *m_finalgdr_backupram;
int m_has_extra_gfx;
UINT8 m_qs1000_data;
DECLARE_WRITE16_MEMBER(flipscreen_w);
DECLARE_WRITE32_MEMBER(flipscreen32_w);
DECLARE_WRITE16_MEMBER(jmpbreak_flipscreen_w);
@ -107,7 +107,7 @@ public:
DECLARE_WRITE32_MEMBER(finalgdr_prize_w);
DECLARE_WRITE16_MEMBER(boonggab_prize_w);
DECLARE_WRITE16_MEMBER(boonggab_lamps_w);
DECLARE_CUSTOM_INPUT_MEMBER(boonggab_photo_sensors_r);
DECLARE_CUSTOM_INPUT_MEMBER(boonggab_photo_sensors_r);
DECLARE_READ16_MEMBER(vamphalf_speedup_r);
DECLARE_READ16_MEMBER(vamphafk_speedup_r);
@ -136,16 +136,16 @@ public:
DECLARE_WRITE32_MEMBER(finalgdr_eeprom_w);
DECLARE_WRITE32_MEMBER(finalgdr_backupram_bank_w);
DECLARE_READ32_MEMBER(finalgdr_backupram_r);
DECLARE_WRITE32_MEMBER(finalgdr_backupram_w);
DECLARE_WRITE32_MEMBER(finalgdr_backupram_w);
DECLARE_WRITE32_MEMBER(finalgdr_oki_bank_w);
DECLARE_WRITE32_MEMBER(aoh_oki_bank_w);
DECLARE_WRITE16_MEMBER(boonggab_oki_bank_w);
DECLARE_WRITE32_MEMBER(wyvernwg_snd_w);
DECLARE_WRITE16_MEMBER(misncrft_snd_w);
DECLARE_READ8_MEMBER(qs1000_p1_r);
DECLARE_WRITE8_MEMBER(qs1000_p3_w);
DECLARE_WRITE8_MEMBER(qs1000_p3_w);
};
READ16_MEMBER(vamphalf_state::eeprom_r)
@ -363,7 +363,7 @@ WRITE32_MEMBER( vamphalf_state::wyvernwg_snd_w )
m_qs1000_data = data & 0xff;
qs1000->set_irq(ASSERT_LINE);
machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
}
WRITE16_MEMBER( vamphalf_state::misncrft_snd_w )
@ -372,7 +372,7 @@ WRITE16_MEMBER( vamphalf_state::misncrft_snd_w )
m_qs1000_data = data & 0xff;
qs1000->set_irq(ASSERT_LINE);
machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
}
READ8_MEMBER( vamphalf_state::qs1000_p1_r )
@ -422,7 +422,7 @@ static ADDRESS_MAP_START( misncrft_io, AS_IO, 16, vamphalf_state )
AM_RANGE(0x200, 0x203) AM_READ_PORT("P1_P2")
AM_RANGE(0x240, 0x243) AM_READ_PORT("SYSTEM")
AM_RANGE(0x3c0, 0x3c3) AM_WRITE(eeprom_w)
AM_RANGE(0x400, 0x403) AM_WRITE(misncrft_snd_w)
AM_RANGE(0x400, 0x403) AM_WRITE(misncrft_snd_w)
AM_RANGE(0x580, 0x583) AM_READ(eeprom_r)
ADDRESS_MAP_END
@ -731,7 +731,7 @@ static SCREEN_UPDATE_IND16( common )
static SCREEN_UPDATE_IND16( aoh )
{
// vamphalf_handle_flipped_visible_area(screen); // not on this?
// vamphalf_handle_flipped_visible_area(screen); // not on this?
bitmap.fill(0, cliprect);
draw_sprites_aoh(screen, bitmap);
return 0;
@ -933,7 +933,7 @@ static QS1000_INTERFACE( qs1000_intf )
{
/* External ROM */
true,
/* P1-P3 read handlers */
DEVCB_DRIVER_MEMBER(vamphalf_state, qs1000_p1_r),
DEVCB_NULL,
@ -1869,7 +1869,7 @@ ROM_START( misncrft )
ROM_RELOAD( 0x20000, 0x20000 )
ROM_RELOAD( 0x40000, 0x20000 )
ROM_RELOAD( 0x60000, 0x20000 )
ROM_REGION( 0x800000, "gfx1", 0 )
ROM_LOAD32_WORD( "roml00", 0x000000, 0x200000, CRC(748c5ae5) SHA1(28005f655920e18c82eccf05c0c449dac16ee36e) )
ROM_LOAD32_WORD( "romh00", 0x000002, 0x200000, CRC(f34ae697) SHA1(2282e3ef2d100f3eea0167b25b66b35a64ddb0f8) )
@ -2461,10 +2461,10 @@ static DRIVER_INIT( misncrft )
state->m_palshift = 0;
state->m_flip_bit = 1;
// Configure the QS1000 ROM banking. Care must be taken not to overlap the 256b internal RAM
machine.device("qs1000:cpu")->memory().space(AS_IO)->install_read_bank(0x0100, 0xffff, "data");
state->membank("qs1000:data")->configure_entries(0, 16, state->memregion("qs1000:cpu")->base()+0x100, 0x8000-0x100);
state->membank("qs1000:data")->configure_entries(0, 16, state->memregion("qs1000:cpu")->base()+0x100, 0x8000-0x100);
}
static DRIVER_INIT( coolmini )

2
src/mame/drivers/vegaeo.c
View File

@ -64,7 +64,7 @@ WRITE8_MEMBER( vegaeo_state::qs1000_p3_w )
qs1000_device *qs1000 = machine().device<qs1000_device>("qs1000");
membank("qs1000:bank")->set_entry(data & 0x07);
membank("qs1000:bank")->set_entry(data & 0x07);
if (!BIT(data, 5))
qs1000->set_irq(CLEAR_LINE);

18
src/mame/drivers/wildpkr.c
View File

@ -22,7 +22,7 @@
CPU:
- 1x MC68000P12 ; 68000 CPU @ 12 MHz, from Motorola.
- 1x D8751H ; 8751 MCU (3.6864 MHz?)
Sound device:
- 1x AY8930 ; Sound IC, from Yamaha.
@ -32,12 +32,12 @@
- 2x HD63486CP32 ; Hitachi - Graphic Video Attribute Controller (GVAC).
Other:
- 1x MC68681 ; Motorola - Dual Asynchronous Receiver/Transmitter.
- 1x MC68681 ; Motorola - Dual Asynchronous Receiver/Transmitter.
- 4x XTALs.... ; 3.6864 / 12.000 / 26.000 / 24.000 MHz.
.--------.
PCB Layout: --+--------+--
.---------------------------------------------------------------------------------------+ +-----------------------------------------------------.
.---------------------------------------------------------------------------------------+ +-----------------------------------------------------.
| | DB9 | |
| .--------. .--------. | | .--------. |
| |::::::::| |::::::::| '--------' |74HCT32P| |
@ -101,12 +101,12 @@
XTAL 1: 3.6864 MHz.
XTAL 2: 12.000 MHz.
XTAL 3: 26.000 MHz.
XTAL 4: 24.000 MHz.
XTAL 4: 24.000 MHz.
TL: TL7705ACP
DSW1: DSW2: DSW3: DSW4:
DSW1: DSW2: DSW3: DSW4:
.--------. .--------. .--------. .--------.
1| oo oooo|8 1|oooooooo|8 1|oooooooo|8 1| o |8 ON
|--------| |--------| |--------| |--------|
@ -128,7 +128,7 @@
---------------------------------
00000 - 7FFFF ; ROM space.
*******************************************************************************
@ -184,7 +184,7 @@ static VIDEO_START( wildpkr )
static SCREEN_UPDATE_IND16( wildpkr )
{
// wildpkr_state *state = screen.machine().driver_data<wildpkr_state>();
// wildpkr_state *state = screen.machine().driver_data<wildpkr_state>();
return 0;
}
@ -266,7 +266,7 @@ static MACHINE_CONFIG_START( wildpkr, wildpkr_state )
MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 512-1)
MCFG_SCREEN_UPDATE_STATIC(wildpkr)
// MCFG_HD63484_ADD("hd63484", wildpkr_hd63484_intf)
// MCFG_HD63484_ADD("hd63484", wildpkr_hd63484_intf)
MCFG_PALETTE_INIT(wildpkr)
MCFG_PALETTE_LENGTH(256)

10
src/mame/includes/eolith.h
View File

@ -4,13 +4,13 @@ public:
eolith_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_soundcpu(*this, "soundcpu")
m_soundcpu(*this, "soundcpu")
{ }
int m_coin_counter_bit;
int m_buffer;
UINT32 *m_vram;
UINT8 m_sound_data;
UINT8 m_data_to_qs1000;
@ -19,17 +19,17 @@ public:
DECLARE_READ32_MEMBER(eolith_custom_r);
DECLARE_WRITE32_MEMBER(systemcontrol_w);
DECLARE_WRITE32_MEMBER(sound_w);
DECLARE_WRITE32_MEMBER(sound_w);
DECLARE_READ32_MEMBER(hidctch3_pen1_r);
DECLARE_READ32_MEMBER(hidctch3_pen2_r);
DECLARE_WRITE32_MEMBER(eolith_vram_w);
DECLARE_READ32_MEMBER(eolith_vram_r);
DECLARE_CUSTOM_INPUT_MEMBER(eolith_speedup_getvblank);
DECLARE_CUSTOM_INPUT_MEMBER(stealsee_speedup_getvblank);
DECLARE_READ8_MEMBER(sound_cmd_r);
DECLARE_WRITE8_MEMBER(sound_p1_w);
DECLARE_READ8_MEMBER(qs1000_p1_r);
DECLARE_WRITE8_MEMBER(qs1000_p1_w);
};

2
src/mame/video/dec0.c
View File

@ -386,7 +386,7 @@ VIDEO_START( dec0 )
VIDEO_START( automat )
{
// dec0_state *state = machine.driver_data<dec0_state>();
// dec0_state *state = machine.driver_data<dec0_state>();
}
/******************************************************************************/

2
src/mame/video/decmxc06.c
View File

@ -167,7 +167,7 @@ void deco_mxc06_device::draw_sprites_bootleg( running_machine &machine, bitmap_i
while (offs < 0x800 / 2)
{
int sx, sy, code, color, flipx, flipy;
code = spriteram[offs];
sy = 240-spriteram[offs + 1]; // 241- will align robocop with the ground but causes other issues too
sx = spriteram[offs + 2];

2
src/version.c
View File

@ -38,4 +38,4 @@
***************************************************************************/
extern const char build_version[];
const char build_version[] = "0.146u1 ("__DATE__")";
const char build_version[] = "0.146u2 ("__DATE__")";