video/s3virge.cpp: initial steps for major structural refactoring
- flatten s3dvirge.s3d down to one struct (m_bitblt), get rid of src_stride and dest_stride fns, update QA - RAMDAC runs in unpacked mode if streams processor disabled - add primary streams stride override, fix Ubuntu flavor gfxs - move NOP logic in dequeue fn - merge draw & command timers in one, simplify state logic, workaround GFX corruption issue - refine a bit FIFO status - base conversion to FIFO
This commit is contained in:
angelosa
parent
de5879d489
commit
3b5e60b420
@ -31,7 +31,8 @@ void virge_pci_device::mmio_map(address_map& map)
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// image transfer ports
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map(0x0000,0x7fff).w(m_vga, FUNC(s3virge_vga_device::image_xfer));
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//map(0x8180,0x81ff) primary/secondary stream control
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//map(0x8000,0x8043) PCI Configuration Space regs
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map(0x8180,0x81ff).m(m_vga, FUNC(s3virge_vga_device::streams_control_map));
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//map(0x8200,0x821f) memory port controller
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//map(0x8220,0x8227) DMA control
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@ -39,23 +40,33 @@ void virge_pci_device::mmio_map(address_map& map)
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// MMIO address map
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map(0x83b0,0x83df).m(m_vga, FUNC(s3virge_vga_device::io_map));
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map(0x8504,0x8507).rw(m_vga, FUNC(s3virge_vga_device::s3d_sub_status_r), FUNC(s3virge_vga_device::s3d_sub_control_w));
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// TODO: writeable
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map(0x850c,0x850f).r(m_vga, FUNC(s3virge_vga_device::s3d_func_ctrl_r));
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//map(0x8580,0x858b) video DMA
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//map(0x8590,0x859f) command DMA
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// S3D engine registers
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map(0xa000,0xb7ff).rw(m_vga, FUNC(s3virge_vga_device::s3d_register_r), FUNC(s3virge_vga_device::s3d_register_w));
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map(0xa000,0xb7ff).m(m_vga, FUNC(s3virge_vga_device::s3d_register_map));
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// alternate image transfer ports
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map(0xd000,0xefff).w(m_vga, FUNC(s3virge_vga_device::image_xfer));
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//map(0xff00, 0xff43) LPB control
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//map(0xff00, 0xff5f) LPB Local Peripheral Bus control
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//map(0xff1c, 0xff1f) LPB GIP/GOP General Input/Output Port (for OEM implementations)
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//map(0xff20, 0xff23) Serial Port Register (DDC/I2C, pins 205-206, aliased at I/O ports $e2 or $e8)
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//map(0xff24, 0xff27) LPB Video Input Window Size
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//map(0xff28, 0xff2b) LPB Video Data Offsets
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//map(0xff2c, 0xff2f) LPB Horizontal Decimation Control Register
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//map(0xff30, 0xff33) LPB Vertical Decimation Control Register
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//map(0xff34, 0xff37) LPB Line Stride
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//map(0xff40, 0xff5f) LPB Output FIFO Register
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}
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void virge_pci_device::lfb_map(address_map& map)
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{
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map(0x0, 0x00ffffff).rw(m_vga, FUNC(s3virge_vga_device::fb_r), FUNC(s3virge_vga_device::fb_w));
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// NOTE: upper mirror is i/f for BE hosts.
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map(0x0, 0x00ffffff).mirror(0x02000000).rw(m_vga, FUNC(s3virge_vga_device::fb_r), FUNC(s3virge_vga_device::fb_w));
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}
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void virge_pci_device::config_map(address_map &map)
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@ -152,6 +163,12 @@ void virge_pci_device::device_start()
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add_map(64 * 1024 * 1024, M_MEM | M_DISABLED, FUNC(virge_pci_device::lfb_map));
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set_map_address(0, 0x70000000);
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command = 0x0000;
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// DAC SNP / BME / MEM / I/O
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command_mask = 0x27;
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// medium DEVSELB
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status = 0x0200;
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remap_cb();
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machine().save().register_postload(save_prepost_delegate(FUNC(virge_pci_device::postload), this));
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}
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@ -174,18 +191,23 @@ void virgedx_pci_device::device_start()
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void virge_pci_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
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uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
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{
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memory_space->install_readwrite_handler(0xa0000, 0xbffff, read8sm_delegate(*this, FUNC(virge_pci_device::vram_r)), write8sm_delegate(*this, FUNC(virge_pci_device::vram_w)));
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io_space->install_device(0x03b0, 0x03df, *this, &virge_pci_device::legacy_io_map);
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// NOTE: this looks unrelated to the linear addressing
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// xubuntu 6.10 and BeOS 3.x definitely wants it this way.
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if(downcast<s3virge_vga_device *>(m_vga.target())->is_new_mmio_active())
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if (BIT(command, 1))
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{
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const u32 get_bar_address = get_vga_linear_address() | 0x01000000;
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memory_space->install_readwrite_handler(0xa0000, 0xbffff, read8sm_delegate(*this, FUNC(virge_pci_device::vram_r)), write8sm_delegate(*this, FUNC(virge_pci_device::vram_w)));
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// NOTE: this looks unrelated to the linear addressing
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// xubuntu 6.10 and BeOS 3.x definitely wants it this way.
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if(downcast<s3virge_vga_device *>(m_vga.target())->is_new_mmio_active())
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{
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u32 get_bar_address = get_vga_linear_address() | 0x01000000;
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memory_space->install_device(get_bar_address, get_bar_address | 0xffff, *this, &virge_pci_device::mmio_map);
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memory_space->install_device(get_bar_address, get_bar_address | 0xffff, *this, &virge_pci_device::mmio_map);
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get_bar_address |= 0x02000000;
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memory_space->install_device(get_bar_address, get_bar_address | 0xffff, *this, &virge_pci_device::mmio_map);
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}
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}
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if (BIT(command, 0))
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io_space->install_device(0x03b0, 0x03df, *this, &virge_pci_device::legacy_io_map);
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}
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void virge_pci_device::device_add_mconfig(machine_config &config)
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@ -1161,7 +1161,7 @@ void vga_device::sequencer_map(address_map &map)
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vga.sequencer.char_sel.A = (((data & 0xc) >> 2)<<1) | ((data & 0x20) >> 5);
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vga.sequencer.char_sel.B = (((data & 0x3) >> 0)<<1) | ((data & 0x10) >> 4);
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if(data)
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popmessage("Char SEL checker, contact MAMEdev (%02x %02x)\n",vga.sequencer.char_sel.A,vga.sequencer.char_sel.B);
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popmessage("Char SEL checker (%02x %02x)\n",vga.sequencer.char_sel.A,vga.sequencer.char_sel.B);
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})
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);
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// Sequencer Memory Mode Register
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File diff suppressed because it is too large
Load Diff
@ -34,42 +34,28 @@ public:
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uint32_t s3d_func_ctrl_r();
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// void s3d_func_ctrl_w(offs_t offset, uint32_t data, u32 mem_mask = ~0);
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uint32_t s3d_register_r(offs_t offset);
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void s3d_register_w(offs_t offset, uint32_t data);
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void s3d_register_map(address_map &map);
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void image_xfer(uint32_t data)
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void streams_control_map(address_map &map);
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void image_xfer(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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// if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x00000080)
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{
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// logerror("IMG Xfer:(%u):%08x X:%u(%u) Y:%u(%u)\n",s3virge.s3d.bitblt_step_count,data,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_width,s3virge.s3d.bitblt_y_current,s3virge.s3d.bitblt_height);
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s3virge.s3d.image_xfer = data;
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bitblt_step();
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}
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if (mem_mask != 0xffff'ffff)
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logerror("Warning: image_xfer access with non-32 parallelism %08x & %08x\n", data, mem_mask);
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m_xfer_fifo.enqueue(data);
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//machine().scheduler().synchronize();
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}
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uint32_t get_linear_address() { return s3virge.linear_address; }
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void set_linear_address(uint32_t addr) { s3virge.linear_address = addr; }
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uint8_t get_linear_address_size() { return s3virge.linear_address_size; }
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uint32_t get_linear_address_size_full() { return s3virge.linear_address_size_full; }
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bool is_linear_address_active() { return s3virge.linear_address_enable; }
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uint32_t get_linear_address() { return m_linear_address; }
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void set_linear_address(uint32_t addr) { m_linear_address = addr; }
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uint8_t get_linear_address_size() { return m_linear_address_size; }
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uint32_t get_linear_address_size_full() { return m_linear_address_size_full; }
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bool is_linear_address_active() { return m_linear_address_enable; }
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bool is_new_mmio_active() { return s3.cr53 & 0x08; }
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uint16_t src_stride()
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{
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return (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_DEST_SRC_STR] >> 0) & 0xfff8;
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}
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uint16_t dest_stride()
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{
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// if((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x0000001c) == 0x08)
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// {
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// popmessage("Stride=%08x",(((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_DEST_SRC_STR] >> 16) & 0xfff8) / 3)
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// + ((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_DEST_SRC_STR] >> 16) & 0xfff8));
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// return (((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_DEST_SRC_STR] >> 16) & 0xfff8) / 3)
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// + ((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_DEST_SRC_STR] >> 16) & 0xfff8);
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// }
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// else
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return (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_DEST_SRC_STR] >> 16) & 0xfff8;
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}
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// has no 8514/A device
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// FIXME: should map this dependency in machine_config
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ibm8514a_device* get_8514() { fatalerror("s3virge requested non-existent 8514/A device\n"); return nullptr; }
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protected:
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@ -100,9 +86,10 @@ protected:
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OP_3DTRI
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};
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enum
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enum s3d_state_t
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{
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S3D_STATE_IDLE = 0,
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S3D_STATE_COMMAND_RX,
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S3D_STATE_BITBLT,
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S3D_STATE_2DLINE,
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S3D_STATE_2DPOLY,
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@ -110,81 +97,75 @@ protected:
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S3D_STATE_3DPOLY
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};
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enum
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{
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S3D_REG_SRC_BASE = 0xd4/4,
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S3D_REG_DEST_BASE = 0xd8/4,
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S3D_REG_CLIP_L_R = 0xdc/4,
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S3D_REG_CLIP_T_B = 0xe0/4,
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S3D_REG_DEST_SRC_STR = 0xe4/4,
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S3D_REG_MONO_PAT_0 = 0xe8/4,
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S3D_REG_MONO_PAT_1 = 0xec/4,
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S3D_REG_PAT_BG_CLR = 0xf0/4,
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S3D_REG_PAT_FG_CLR = 0xf4/4,
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S3D_REG_SRC_BG_CLR = 0xf8/4,
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S3D_REG_SRC_FG_CLR = 0xfc/4,
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S3D_REG_COMMAND = 0x100/4,
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S3D_REG_RWIDTH_HEIGHT = 0x104/4,
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S3D_REG_RSRC_XY = 0x108/4,
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S3D_REG_RDEST_XY = 0x10c/4
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};
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struct {
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u8 psidf = 0;
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u8 pshfc = 0;
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u16 primary_stride = 0;
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} m_streams;
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u32 m_interrupt_enable = 0;
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bool m_linear_address_enable = false;
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u32 m_linear_address = 0;
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u8 m_linear_address_size = 0;
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u32 m_linear_address_size_full = 0;
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u8 m_cr66 = 0;
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// util::fifo<u32, 16 * 15> m_bitblt_fifo;
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// TODO: sketchy, command pipeline size is unclear
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util::fifo<u32, 0x8000> m_bitblt_fifo;
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util::fifo<u32, 0x8000> m_xfer_fifo;
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// TODO: sketchy type, verify implications of using a struct class with util::fifo
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// (may be required if we want to glue in a "execute command" insert flag)
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u32 m_bitblt_latch[15]{};
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s3d_state_t m_s3d_state = S3D_STATE_IDLE;
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struct
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{
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uint32_t linear_address;
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uint8_t linear_address_size;
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uint32_t linear_address_size_full;
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bool linear_address_enable;
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uint32_t interrupt_enable;
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bool xfer_mode = false;
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struct
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{
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int state;
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bool busy;
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struct
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{
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uint32_t reg[256];
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int op_type;
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} cmd_fifo[16];
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int cmd_fifo_next_ptr; // command added here in FIFO
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int cmd_fifo_current_ptr; // command currently being processed in FIFO
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int cmd_fifo_slots_free;
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u8 pattern[0xc0]{};
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uint8_t pattern[0xc0];
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uint32_t reg[5][256];
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u16 x_src = 0;
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u16 y_src = 0;
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u16 x_dst = 0;
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u16 y_dst = 0;
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s16 x_current = 0;
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s16 y_current = 0;
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s16 x_src_current = 0;
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s16 y_src_current = 0;
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s8 pat_x = 0;
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s8 pat_y = 0;
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u16 height = 0;
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u16 width = 0;
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u32 step_count = 0;
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u64 mono_pattern = 0;
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u32 current_pixel = 0;
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// current position in a pixel (for packed 24bpp colour image transfers)
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u32 pixel_pos = 0;
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// source data via image transfer ports
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u32 image_xfer = 0;
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u16 clip_l = 0;
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u16 clip_r = 0;
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u16 clip_t = 0;
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u16 clip_b = 0;
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u32 command = 0;
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u32 src_base = 0;
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u32 dest_base = 0;
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u32 pat_bg_clr = 0;
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u32 pat_fg_clr = 0;
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u32 src_bg_clr = 0;
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u32 src_fg_clr = 0;
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u16 dest_stride = 0;
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u16 src_stride = 0;
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} m_bitblt;
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// BitBLT command state
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uint16_t bitblt_x_src;
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uint16_t bitblt_y_src;
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uint16_t bitblt_x_dst;
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uint16_t bitblt_y_dst;
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int16_t bitblt_x_current;
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int16_t bitblt_y_current;
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int16_t bitblt_x_src_current;
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int16_t bitblt_y_src_current;
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int8_t bitblt_pat_x;
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int8_t bitblt_pat_y;
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uint16_t bitblt_height;
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uint16_t bitblt_width;
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uint32_t bitblt_step_count;
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uint64_t bitblt_mono_pattern;
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uint32_t bitblt_current_pixel;
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uint32_t bitblt_pixel_pos; // current position in a pixel (for packed 24bpp colour image transfers)
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uint32_t image_xfer; // source data via image transfer ports
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uint16_t clip_l;
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uint16_t clip_r;
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uint16_t clip_t;
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uint16_t clip_b;
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} s3d;
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} s3virge;
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TIMER_CALLBACK_MEMBER(op_timer_cb);
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TIMER_CALLBACK_MEMBER(draw_step_tick);
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inline void write_pixel32(uint32_t base, uint16_t x, uint16_t y, uint32_t val);
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inline void write_pixel24(uint32_t base, uint16_t x, uint16_t y, uint32_t val);
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inline void write_pixel16(uint32_t base, uint16_t x, uint16_t y, uint16_t val);
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inline void write_pixel8(uint32_t base, uint16_t x, uint16_t y, uint8_t val);
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inline uint32_t read_pixel32(uint32_t base, uint16_t x, uint16_t y, u16 stride_select);
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inline uint32_t read_pixel24(uint32_t base, uint16_t x, uint16_t y, u16 stride_select);
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inline uint16_t read_pixel16(uint32_t base, uint16_t x, uint16_t y, u16 stride_select);
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inline uint8_t read_pixel8(uint32_t base, uint16_t x, uint16_t y, u16 stride_select);
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@ -196,9 +177,8 @@ protected:
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virtual void s3_define_video_mode(void) override;
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// has no 8514/A device
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private:
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emu_timer* m_draw_timer;
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emu_timer *m_op_timer;
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void bitblt_step();
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void bitblt_colour_step();
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void bitblt_monosrc_step();
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@ -206,9 +186,12 @@ private:
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void poly2d_step();
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void line3d_step();
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void poly3d_step();
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void add_command(int cmd_type);
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void command_start();
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void add_command(u8 cmd_type);
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void command_enqueue(u8 op_type);
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void command_dequeue(u8 op_type);
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void command_finish();
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void s3d_reset();
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};
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