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h8: appears to be better for performance without virtual calls for r/w functions

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hap 2024-02-18 22:25:12 +01:00
parent 4a6ef39923
commit 3bb9487dfc
4 changed files with 34 additions and 59 deletions
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36
src/devices/cpu/h8/h8.cpp
View File

@ -474,33 +474,51 @@ void h8_device::state_string_export(const device_state_entry &entry, std::string
}
}
// FIXME: one-state bus cycles are only provided for on-chip ROM & RAM in H8S/2000 and H8S/2600.
// All other accesses take *at least* two states each, and additional wait states are often programmed for external memory!
u16 h8_device::read16i(u32 adr)
{
m_icount -= 2;
if(m_has_exr)
m_icount--;
else
m_icount -= 2;
return m_cache.read_word(adr & ~1);
}
u8 h8_device::read8(u32 adr)
{
m_icount -= 2;
if(m_has_exr)
m_icount--;
else
m_icount -= 2;
return m_program.read_byte(adr);
}
void h8_device::write8(u32 adr, u8 data)
{
m_icount -= 2;
if(m_has_exr)
m_icount--;
else
m_icount -= 2;
m_program.write_byte(adr, data);
}
u16 h8_device::read16(u32 adr)
{
m_icount -= 2;
if(m_has_exr)
m_icount--;
else
m_icount -= 2;
return m_program.read_word(adr & ~1);
}
void h8_device::write16(u32 adr, u16 data)
{
m_icount -= 2;
if(m_has_exr)
m_icount--;
else
m_icount -= 2;
m_program.write_word(adr & ~1, data);
}
@ -563,9 +581,11 @@ void h8_device::set_irq(int irq_vector, int irq_level, bool irq_nmi)
void h8_device::internal(int cycles)
{
// all internal operations take an even number of states (at least 2 each)
// this only applies to: H8/300, H8/300L, H8/300H (not H8S)
m_icount -= cycles + 1;
// on H8/300, H8/300L, H8/300H (not H8S), all internal operations take an even number of states (at least 2 each)
if(!m_has_exr)
m_icount -= cycles + 1;
else
m_icount -= cycles;
}
void h8_device::illegal()

12
src/devices/cpu/h8/h8.h
View File

@ -191,12 +191,12 @@ protected:
virtual int trapa_setup();
virtual void irq_setup() = 0;
virtual u16 read16i(u32 adr);
virtual u8 read8(u32 adr);
virtual void write8(u32 adr, u8 data);
virtual u16 read16(u32 adr);
virtual void write16(u32 adr, u16 data);
virtual void internal(int cycles);
u16 read16i(u32 adr);
u8 read8(u32 adr);
void write8(u32 adr, u8 data);
u16 read16(u32 adr);
void write16(u32 adr, u16 data);
void internal(int cycles);
void prefetch_switch(u32 pc, u16 ir) { m_NPC = pc & 0xffffff; m_PC = pc+2; m_PIR = ir; }
void prefetch_done();
void prefetch_done_noirq();

38
src/devices/cpu/h8/h8s2000.cpp
View File

@ -15,42 +15,4 @@ std::unique_ptr<util::disasm_interface> h8s2000_device::create_disassembler()
return std::make_unique<h8s2000_disassembler>();
}
// FIXME: one-state bus cycles are only provided for on-chip ROM & RAM in H8S/2000 and H8S/2600.
// All other accesses take *at least* two states each, and additional wait states are often programmed for external memory!
u16 h8s2000_device::read16i(u32 adr)
{
m_icount--;
return m_cache.read_word(adr & ~1);
}
u8 h8s2000_device::read8(u32 adr)
{
m_icount--;
return m_program.read_byte(adr);
}
void h8s2000_device::write8(u32 adr, u8 data)
{
m_icount--;
m_program.write_byte(adr, data);
}
u16 h8s2000_device::read16(u32 adr)
{
m_icount--;
return m_program.read_word(adr & ~1);
}
void h8s2000_device::write16(u32 adr, u16 data)
{
m_icount--;
m_program.write_word(adr & ~1, data);
}
void h8s2000_device::internal(int cycles)
{
m_icount -= cycles;
}
#include "cpu/h8/h8s2000.hxx"

7
src/devices/cpu/h8/h8s2000.h
View File

@ -29,13 +29,6 @@ protected:
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
virtual u16 read16i(u32 adr) override;
virtual u8 read8(u32 adr) override;
virtual void write8(u32 adr, u8 data) override;
virtual u16 read16(u32 adr) override;
virtual void write16(u32 adr, u16 data) override;
virtual void internal(int cycles) override;
virtual void do_exec_full() override;
virtual void do_exec_partial() override;