mirror of
https://github.com/holub/mame
synced 2025-04-18 22:49:58 +03:00
cpu/e132xs: Untangled device types.
* Got package option (T, N or B suffix) out of device type. * Enabled 4x PLL clock multiplier for GMS30C2216/GMS30C2232. * Implemented entering power down mode via MCR for E1 and E1-X cores. * Marginally better code generation for a few instructions. * Log available bus/memory configuration options for different cores. * Added post load handler for E1-XS and E1-XSR cores to install SDRAM mode/configuration handlers if necessary. * Improved comment about different Hynix and Hyperstone CPU models. -cpu/drcbearm64.cpp: Don't update flags that aren't requested in a few places.
This commit is contained in:
Vas Crabb
parent
9d1ff6e8ee
commit
3c27e2fd8d
@ -3612,7 +3612,12 @@ template <bool CarryIn> void drcbe_arm64::op_add(a64::Assembler &a, const uml::i
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}
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if (inst.flags())
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store_carry(a);
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{
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if (inst.flags() & FLAG_C)
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store_carry(a);
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else
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m_carry_state = carry_state::POISON;
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}
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}
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template <bool CarryIn> void drcbe_arm64::op_sub(a64::Assembler &a, const uml::instruction &inst)
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@ -3696,7 +3701,12 @@ template <bool CarryIn> void drcbe_arm64::op_sub(a64::Assembler &a, const uml::i
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}
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if (inst.flags())
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store_carry(a, true);
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{
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if (inst.flags() & FLAG_C)
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store_carry(a, true);
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else
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m_carry_state = carry_state::POISON;
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}
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}
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void drcbe_arm64::op_cmp(a64::Assembler &a, const uml::instruction &inst)
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@ -3727,7 +3737,10 @@ void drcbe_arm64::op_cmp(a64::Assembler &a, const uml::instruction &inst)
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a.cmp(src1, src2);
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}
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store_carry(a, true);
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if (inst.flags() & FLAG_C)
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store_carry(a, true);
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else
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m_carry_state = carry_state::POISON;
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}
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void drcbe_arm64::op_mulu(a64::Assembler &a, const uml::instruction &inst)
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@ -5050,8 +5063,12 @@ void drcbe_arm64::op_fcmp(a64::Assembler &a, const uml::instruction &inst)
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a.fcmp(srcreg1, srcreg2);
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store_carry(a, true);
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store_unordered(a);
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if (inst.flags() & FLAG_C)
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store_carry(a, true);
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else
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m_carry_state = carry_state::POISON;
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if (inst.flags() & FLAG_U)
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store_unordered(a);
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}
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template <a64::Inst::Id Opcode> void drcbe_arm64::op_float_alu(a64::Assembler &a, const uml::instruction &inst)
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@ -8,27 +8,48 @@
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Hyperstone models:
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16 bits
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- E1-16T
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- E1-16XT
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- E1-16XS
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- E1-16XSR
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32bits
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- E1-32N or E1-32T
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- E1-32XN or E1-32XT
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- E1-32XS
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- E1-32XSR
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Model Core IRAM Process Bus Package
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E1-16T E1 4 KiB DRAM 16-bit 100-pin TQFP
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E1-32T E1 4 KiB DRAM 32-bit 144-pin TQFP
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E1-32N E1 4 KiB DRAM 32-bit 160-pin PQFP
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E1-16XT E1-X 8 KiB DRAM 0.5 µm 16-bit 100-pin TQFP
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E1-32XT E1-X 8 KiB DRAM 0.5 µm 32-bit 144-pin TQFP
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E1-32XN E1-X 8 KiB DRAM 0.5 µm 32-bit 160-pin PQFP
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E1-16XS E1-XS 16 KiB SRAM 0.25 µm 16-bit 100-pin LQFP
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E1-16XSB E1-XS 16 KiB SRAM 0.25 µm 16-bit 100-pin TFBGA
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E1-32XS E1-XS 16 KiB SRAM 0.25 µm 32-bit 144-pin LQFP
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E1-16XSR E1-XSR 16 KiB SRAM 0.25 µm 16-bit 100-pin LQFP
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E1-32XSR E1-XSR 16 KiB SRAM 0.25 µm 32-bit 144-pin LQFP
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Hynix models:
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16 bits
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- GMS30C2116
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- GMS30C2216
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Model Core IRAM Process Bus Package
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GMS30C2116 E1 4 KiB DRAM 0.6 µm 16-bit 100-pin TQFP
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GMS30C2132 E1 4 KiB DRAM 0.6 µm 32-bit 144-pin TQFP, 160-pin MQFP
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GMS30C2216 E1-X 8 KiB DRAM 0.35 µm 16-bit 100-pin TQFP
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GMS30C2232 E1-X 8 KiB DRAM 0.35 µm 32-bit 144-pin TQFP, 160-pin MQFP
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32bits
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- GMS30C2132
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- GMS30C2232
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E1-X changes:
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* Added PLL with up to 4* multiplication
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* Increases IRAM to 8 KiB
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* Adds MEM0 EDO DRAM support
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* Adds MEM0/MEM1/MEM2/MEM3 parity support
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* Adds MEM0/MEM1/MEM2 byte write strobe/byte enable selection
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* Adds MEM2 wait support
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* Changes to bus hold break always enabled for DRAM
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* Moves power down from MCR to an I/O address
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E-1XS changes:
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* Increases PLL options to up to 8* multiplication
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* Increases IRAM to 16 KiB
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* Changes IRAM to SRAM
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* Adds MEM0 SDRAM support
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* Removes bus output voltage and input threshold selection
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E-1XS changes:
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* Changes DRAM timing options
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* Adds more DRAM clock configuration options
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* Removes MEM0/MEM1/MEM2 byte write strobe/byte enable selection
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TODO:
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- All instructions should clear the H flag (not just MOV/MOVI)
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@ -42,6 +63,10 @@
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- Verify register wrapping with sregf/dregf on hardware
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- Tracing doesn't work properly for the recompiler
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DRC does not generate trace exceptions on branch or return
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- INT/IO polarity
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- IO3 timing and timer interrupt modes
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- Watchdog
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- Sleep mode
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*********************************************************************/
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@ -61,40 +86,25 @@
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// INTERNAL ADDRESS MAP
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//**************************************************************************
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// 4Kb IRAM (On-Chip Memory)
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// 4KiB IRAM (On-Chip Memory)
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void hyperstone_device::e116_4k_iram_map(address_map &map)
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{
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map(0xc0000000, 0xc0000fff).ram().mirror(0x1ffff000);
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}
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void hyperstone_device::e132_4k_iram_map(address_map &map)
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void hyperstone_device::iram_4k_map(address_map &map)
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{
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map(0xc0000000, 0xc0000fff).ram().mirror(0x1ffff000);
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}
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// 8Kb IRAM (On-Chip Memory)
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// 8KiB IRAM (On-Chip Memory)
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void hyperstone_device::e116_8k_iram_map(address_map &map)
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{
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map(0xc0000000, 0xc0001fff).ram().mirror(0x1fffe000);
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}
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void hyperstone_device::e132_8k_iram_map(address_map &map)
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void hyperstone_x_device::iram_8k_map(address_map &map)
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{
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map(0xc0000000, 0xc0001fff).ram().mirror(0x1fffe000);
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}
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// 16Kb IRAM (On-Chip Memory)
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// 16KiB IRAM (On-Chip Memory)
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void hyperstone_device::e116_16k_iram_map(address_map &map)
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{
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map(0xc0000000, 0xc0003fff).ram().mirror(0x1fffc000);
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}
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void hyperstone_device::e132_16k_iram_map(address_map &map)
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void hyperstone_xs_device::iram_16k_map(address_map &map)
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{
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map(0xc0000000, 0xc0003fff).ram().mirror(0x1fffc000);
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}
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@ -106,10 +116,10 @@ void hyperstone_device::e132_16k_iram_map(address_map &map)
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hyperstone_device::hyperstone_device(
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const machine_config &mconfig,
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const device_type type,
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const char *tag,
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device_t *owner,
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uint32_t clock,
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const device_type type,
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uint32_t prg_data_width,
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uint32_t io_data_width,
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address_map_constructor internal_map)
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@ -146,21 +156,25 @@ hyperstone_device::~hyperstone_device()
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//-------------------------------------------------
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// e116t_device - constructor
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// e116_device - constructor
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//-------------------------------------------------
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e116t_device::e116t_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E116T, 16, 16, address_map_constructor(FUNC(e116t_device::e116_4k_iram_map), this))
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e116_device::e116_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(
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mconfig, E116, tag, owner, clock,
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16, 16, address_map_constructor(FUNC(e116_device::iram_4k_map), this))
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{
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}
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//-------------------------------------------------
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// e116xt_device - constructor
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// e116x_device - constructor
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//-------------------------------------------------
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e116xt_device::e116xt_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E116XT, 16, 16, address_map_constructor(FUNC(e116xt_device::e116_8k_iram_map), this))
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e116x_device::e116x_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_x_device(
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mconfig, E116X, tag, owner, clock,
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16, 16, address_map_constructor(FUNC(e116x_device::iram_8k_map), this))
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{
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}
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@ -170,7 +184,9 @@ e116xt_device::e116xt_device(const machine_config &mconfig, const char *tag, dev
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//-------------------------------------------------
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e116xs_device::e116xs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E116XS, 16, 16, address_map_constructor(FUNC(e116xs_device::e116_16k_iram_map), this))
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: hyperstone_xs_device(
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mconfig, E116XS, tag, owner, clock,
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16, 16, address_map_constructor(FUNC(e116xs_device::iram_16k_map), this))
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{
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}
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@ -180,47 +196,33 @@ e116xs_device::e116xs_device(const machine_config &mconfig, const char *tag, dev
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//-------------------------------------------------
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e116xsr_device::e116xsr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E116XSR, 16, 16, address_map_constructor(FUNC(e116xsr_device::e116_16k_iram_map), this))
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: hyperstone_xsr_device(
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mconfig, E116XSR, tag, owner, clock,
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16, 16, address_map_constructor(FUNC(e116xsr_device::iram_16k_map), this))
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{
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}
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//-------------------------------------------------
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// e132n_device - constructor
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// e132_device - constructor
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//-------------------------------------------------
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e132n_device::e132n_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E132N, 32, 32, address_map_constructor(FUNC(e132n_device::e132_4k_iram_map), this))
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e132_device::e132_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(
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mconfig, E132, tag, owner, clock,
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32, 32, address_map_constructor(FUNC(e132_device::iram_4k_map), this))
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{
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}
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//-------------------------------------------------
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// e132t_device - constructor
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// e132x_device - constructor
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//-------------------------------------------------
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e132t_device::e132t_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E132T, 32, 32, address_map_constructor(FUNC(e132t_device::e132_4k_iram_map), this))
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{
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}
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//-------------------------------------------------
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// e132xn_device - constructor
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//-------------------------------------------------
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e132xn_device::e132xn_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E132XN, 32, 32, address_map_constructor(FUNC(e132xn_device::e132_8k_iram_map), this))
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{
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}
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//-------------------------------------------------
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// e132xt_device - constructor
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//-------------------------------------------------
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e132xt_device::e132xt_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E132XT, 32, 32, address_map_constructor(FUNC(e132xt_device::e132_8k_iram_map), this))
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e132x_device::e132x_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_x_device(
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mconfig, E132X, tag, owner, clock,
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32, 32, address_map_constructor(FUNC(e132x_device::iram_8k_map), this))
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{
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}
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@ -230,7 +232,9 @@ e132xt_device::e132xt_device(const machine_config &mconfig, const char *tag, dev
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//-------------------------------------------------
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e132xs_device::e132xs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E132XS, 32, 32, address_map_constructor(FUNC(e132xs_device::e132_16k_iram_map), this))
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: hyperstone_xs_device(
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mconfig, E132XS, tag, owner, clock,
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32, 32, address_map_constructor(FUNC(e132xs_device::iram_16k_map), this))
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{
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}
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@ -240,7 +244,9 @@ e132xs_device::e132xs_device(const machine_config &mconfig, const char *tag, dev
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//-------------------------------------------------
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e132xsr_device::e132xsr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, E132XSR, 32, 32, address_map_constructor(FUNC(e132xsr_device::e132_16k_iram_map), this))
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: hyperstone_xsr_device(
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mconfig, E132XSR, tag, owner, clock,
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32, 32, address_map_constructor(FUNC(e132xsr_device::iram_16k_map), this))
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{
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}
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@ -250,7 +256,9 @@ e132xsr_device::e132xsr_device(const machine_config &mconfig, const char *tag, d
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//-------------------------------------------------
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gms30c2116_device::gms30c2116_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, GMS30C2116, 16, 16, address_map_constructor(FUNC(gms30c2116_device::e116_4k_iram_map), this))
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: hyperstone_device(
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mconfig, GMS30C2116, tag, owner, clock,
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16, 16, address_map_constructor(FUNC(gms30c2116_device::iram_4k_map), this))
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{
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}
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@ -260,7 +268,9 @@ gms30c2116_device::gms30c2116_device(const machine_config &mconfig, const char *
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//-------------------------------------------------
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gms30c2132_device::gms30c2132_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, GMS30C2132, 32, 32, address_map_constructor(FUNC(gms30c2132_device::e132_4k_iram_map), this))
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: hyperstone_device(
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mconfig, GMS30C2132, tag, owner, clock,
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32, 32, address_map_constructor(FUNC(gms30c2132_device::iram_4k_map), this))
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{
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}
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@ -270,7 +280,9 @@ gms30c2132_device::gms30c2132_device(const machine_config &mconfig, const char *
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//-------------------------------------------------
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gms30c2216_device::gms30c2216_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, GMS30C2216, 16, 16, address_map_constructor(FUNC(gms30c2216_device::e116_8k_iram_map), this))
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: hyperstone_x_device(
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mconfig, GMS30C2216, tag, owner, clock,
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16, 16, address_map_constructor(FUNC(gms30c2216_device::iram_8k_map), this))
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{
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}
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@ -280,7 +292,9 @@ gms30c2216_device::gms30c2216_device(const machine_config &mconfig, const char *
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//-------------------------------------------------
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gms30c2232_device::gms30c2232_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hyperstone_device(mconfig, tag, owner, clock, GMS30C2232, 32, 32, address_map_constructor(FUNC(gms30c2232_device::e132_8k_iram_map), this))
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: hyperstone_x_device(
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mconfig, GMS30C2232, tag, owner, clock,
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32, 32, address_map_constructor(FUNC(gms30c2232_device::iram_8k_map), this))
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{
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}
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@ -445,13 +459,197 @@ void hyperstone_device::update_bus_control()
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BIT(val, 28, 4) + 1,
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BIT(val, 8, 3),
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BIT(val, 7));
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}
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void hyperstone_xsr_device::update_bus_control()
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{
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const uint32_t val = m_core->global_regs[BCR_REGISTER];
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LOG("%s: Set BCR = 0x%08x\n", machine().describe_context(), val);
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if (BIT(m_core->global_regs[MCR_REGISTER], 21))
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{
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LOG("MEM0 access time %d cycles, hold time %d cycles, setup time %d cycles\n",
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BIT(val, 16, 4) + 1,
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BIT(val, 11, 3),
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BIT(val, 14, 2));
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}
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else
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{
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char const *const refresh[8] = {
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"every 256 prescaler time units",
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"every 128 prescaler time units",
|
||||
"every 64 prescaler time units",
|
||||
"every 32 prescaler time units",
|
||||
"every 16 prescaler time units",
|
||||
"every 8 prescaler time units",
|
||||
"every 4 prescaler time units",
|
||||
"disabled" };
|
||||
char const *const page[8] = { "64K", "32K", "16K", "8K", "4K", "2K", "1K", "512" };
|
||||
unsigned ras_precharge, cas_access, ras_to_cas;
|
||||
if (BIT(m_core->global_regs[MCR_REGISTER], 22))
|
||||
{
|
||||
ras_precharge = BIT(val, 18, 2) + 1 + (BIT(m_core->global_regs[MCR_REGISTER], 8) * 2);
|
||||
cas_access = BIT(val, 16, 2) + 1 + (BIT(m_core->global_regs[MCR_REGISTER], 8) * 2);
|
||||
ras_to_cas = BIT(val, 14, 2) + 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
ras_precharge = (BIT(val, 18, 2) + 1) << BIT(m_core->global_regs[MCR_REGISTER], 8);
|
||||
cas_access = (BIT(val, 16, 2) + 1) << BIT(m_core->global_regs[MCR_REGISTER], 8);
|
||||
ras_to_cas = (BIT(val, 14, 2) + 1) << BIT(m_core->global_regs[MCR_REGISTER], 8);
|
||||
}
|
||||
LOG("MEM0 RAS precharge time %d cycles, RAS to CAS delay time %d cycles, CAS access time %d cycles, %s byte rows, refresh %s\n",
|
||||
ras_precharge,
|
||||
ras_to_cas,
|
||||
cas_access,
|
||||
page[BIT(val, 4, 3)],
|
||||
refresh[BIT(val, 11, 3)]);
|
||||
}
|
||||
LOG("MEM1 access time %d cycles, hold time %d cycles\n",
|
||||
BIT(val, 20, 3) + 1,
|
||||
BIT(val, 22) + BIT(val, 23));
|
||||
LOG("MEM2 access time %d cycles, hold time %d cycles, setup time %d cycles\n",
|
||||
BIT(val, 24, 4) + 1,
|
||||
BIT(val, 0, 3),
|
||||
BIT(val, 3));
|
||||
LOG("MEM3 access time %d cycles, hold time %d cycles, setup time %d cycles\n",
|
||||
BIT(val, 28, 4) + 1,
|
||||
BIT(val, 8, 3),
|
||||
BIT(val, 7));
|
||||
}
|
||||
|
||||
void hyperstone_device::update_memory_control()
|
||||
{
|
||||
const uint32_t val = m_core->global_regs[MCR_REGISTER];
|
||||
|
||||
static char const *const entrymap[8] = { "MEM0", "MEM1", "MEM2", "IRAM", "reserved", "reserved", "reserved", "MEM3" };
|
||||
LOG("%s: Set MCR = 0x%08x, entry map in %s, %s output voltage, input threshold for VDD=%sV\n",
|
||||
machine().describe_context(),
|
||||
val,
|
||||
entrymap[BIT(val, 12, 3)],
|
||||
BIT(val, 25) ? "rail-to-rail" : "reduced",
|
||||
BIT(val, 24) ? "5.0" : "3.3");
|
||||
|
||||
static char const *const size[4] = { "32 bit", "reserved", "16 bit", "8 bit" };
|
||||
char const *const refresh[8] = {
|
||||
"every 128 prescaler time units",
|
||||
"every 64 prescaler time units",
|
||||
"every 32 prescaler time units",
|
||||
"every 16 prescaler time units",
|
||||
"every 8 prescaler time units",
|
||||
"every 4 prescaler time units",
|
||||
"every 2 prescaler time units",
|
||||
"disabled" };
|
||||
LOG("IRAM %s mode, refresh %s\n",
|
||||
BIT(val, 20) ? "normal" : "test", // IRAM refresh test
|
||||
refresh[BIT(val, 16, 2)]); // IRAM refresh rate
|
||||
LOG("MEM0 %s %sDRAM, bus hold break %s\n",
|
||||
size[BIT(val, 0, 2)], // MEM0 bus size
|
||||
BIT(val, 21) ? "non-" : "fast page ", // MEM0 memory type
|
||||
BIT(val, 8) ? "disabled" : "enabled"); // MEM0 bus hold break
|
||||
LOG("MEM1 %s, bus hold break %s\n",
|
||||
size[BIT(val, 2, 2)], // MEM1 bus size
|
||||
BIT(val, 9) ? "disabled" : "enabled"); // MEM1 bus hold break
|
||||
LOG("MEM2 %s, bus hold break %s\n",
|
||||
size[BIT(val, 4, 2)], // MEM2 bus size
|
||||
BIT(val, 10) ? "disabled" : "enabled"); // MEM2 bus hold break
|
||||
LOG("MEM3 %s, bus hold break %s\n",
|
||||
size[BIT(val, 6, 2)], // MEM3 bus size
|
||||
BIT(val, 11) ? "disabled" : "enabled"); // MEM3 bus hold break
|
||||
|
||||
// bits 14..12 EntryTableMap
|
||||
const int which = (val & 0x7000) >> 12;
|
||||
assert(which < 4 || which == 7);
|
||||
m_core->trap_entry = s_trap_entries[which];
|
||||
|
||||
const uint8_t power_down_req = BIT(val, 22);
|
||||
if (!power_down_req && m_power_down_req)
|
||||
{
|
||||
LOG("entering power down\n");
|
||||
m_core->powerdown = 1;
|
||||
}
|
||||
m_power_down_req = power_down_req;
|
||||
}
|
||||
|
||||
void hyperstone_x_device::update_memory_control()
|
||||
{
|
||||
const uint32_t val = m_core->global_regs[MCR_REGISTER];
|
||||
|
||||
// GMS30C22xx drops bus output voltage/input threshold selecting while E1-X apparently doesn't
|
||||
|
||||
static char const *const entrymap[8] = { "MEM0", "MEM1", "MEM2", "IRAM", "reserved", "reserved", "reserved", "MEM3" };
|
||||
LOG("%s: Set MCR = 0x%08x, entry map in %s, %s output voltage, input threshold for VDD=%sV\n",
|
||||
machine().describe_context(),
|
||||
val,
|
||||
entrymap[BIT(val, 12, 3)],
|
||||
BIT(val, 25) ? "rail-to-rail" : "reduced",
|
||||
BIT(val, 24) ? "5.0" : "3.3");
|
||||
|
||||
static char const *const size[4] = { "32 bit", "reserved", "16 bit", "8 bit" };
|
||||
char const *const refresh[8] = {
|
||||
"every 128 prescaler time units",
|
||||
"every 64 prescaler time units",
|
||||
"every 32 prescaler time units",
|
||||
"every 16 prescaler time units",
|
||||
"every 8 prescaler time units",
|
||||
"every 4 prescaler time units",
|
||||
"every 2 prescaler time units",
|
||||
"disabled" };
|
||||
LOG("IRAM %s mode, refresh %s\n",
|
||||
BIT(val, 20) ? "normal" : "test", // IRAM refresh test
|
||||
refresh[BIT(val, 16, 2)]); // IRAM refresh rate
|
||||
if (BIT(val, 21))
|
||||
{
|
||||
LOG("MEM0 %s, bus hold break %s, parity %s, byte %s\n",
|
||||
size[BIT(val, 0, 2)], // MEM0 bus size
|
||||
BIT(val, 8) ? "disabled" : "enabled", // MEM0 bus hold break
|
||||
BIT(val, 28) ? "disabled" : "enabled", // MEM0 parity
|
||||
BIT(val, 15) ? "strobe" : "enable"); // MEM0 byte mode
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG("MEM0 %s %s DRAM, hold time %s, parity %s\n",
|
||||
size[BIT(val, 0, 2)], // MEM0 bus size
|
||||
BIT(val, 15) ? "fast page" : "EDO", // MEM0 DRAM type
|
||||
BIT(val, 8) ? "1 cycle" : "0 cycles", // MEM0 bus hold
|
||||
BIT(val, 28) ? "disabled" : "enabled"); // MEM0 parity
|
||||
}
|
||||
LOG("MEM1 %s, bus hold break %s, parity %s, byte %s\n",
|
||||
size[BIT(val, 2, 2)], // MEM1 bus size
|
||||
BIT(val, 9) ? "disabled" : "enabled", // MEM1 bus hold break
|
||||
BIT(val, 29) ? "disabled" : "enabled", // MEM1 parity
|
||||
BIT(val, 19) ? "strobe" : "enable"); // MEM1 byte mode
|
||||
LOG("MEM2 %s, bus hold break %s, parity %s, byte %s, wait %s\n",
|
||||
size[BIT(val, 4, 2)], // MEM2 bus size
|
||||
BIT(val, 10) ? "disabled" : "enabled", // MEM2 bus hold break
|
||||
BIT(val, 30) ? "disabled" : "enabled", // MEM2 parity
|
||||
BIT(val, 23) ? "strobe" : "enable", // MEM2 byte mode
|
||||
BIT(val, 26) ? "disabled" : "enabled"); // MEM2 wait
|
||||
LOG("MEM3 %s, bus hold break %s, parity %s\n",
|
||||
size[BIT(val, 6, 2)], // MEM3 bus size
|
||||
BIT(val, 11) ? "disabled" : "enabled", // MEM3 bus hold break
|
||||
BIT(val, 31) ? "disabled" : "enabled"); // MEM3 parity
|
||||
|
||||
// bits 14..12 EntryTableMap
|
||||
const int which = (val & 0x7000) >> 12;
|
||||
assert(which < 4 || which == 7);
|
||||
m_core->trap_entry = s_trap_entries[which];
|
||||
|
||||
// this was moved to an I/O address for the E1-X core
|
||||
// apparently this method still works as the Limenko games use it
|
||||
const uint8_t power_down_req = BIT(val, 22);
|
||||
if (!power_down_req && m_power_down_req)
|
||||
{
|
||||
LOG("entering power down\n");
|
||||
m_core->powerdown = 1;
|
||||
}
|
||||
m_power_down_req = power_down_req;
|
||||
}
|
||||
|
||||
void hyperstone_xs_device::update_memory_control()
|
||||
{
|
||||
const uint32_t val = m_core->global_regs[MCR_REGISTER];
|
||||
|
||||
static char const *const entrymap[8] = { "MEM0", "MEM1", "MEM2", "IRAM", "reserved", "reserved", "reserved", "MEM3" };
|
||||
LOG("%s: Set MCR = 0x%08x, entry map in %s\n",
|
||||
machine().describe_context(),
|
||||
@ -473,9 +671,8 @@ void hyperstone_device::update_memory_control()
|
||||
LOG("MEM0 %s %sDRAM, hold time %s, parity %s\n",
|
||||
size[BIT(val, 0, 2)], // MEM0 bus size
|
||||
dramtype[bitswap<2>(val, 22, 15)], // MEM0 DRAM type
|
||||
BIT(val, 8) ? "1 cycle" : "0 cycles", // MEM0 bus hold
|
||||
BIT(val, 28) ? "disabled" : "enabled", // MEM0 parity
|
||||
BIT(val, 15) ? "strobe" : "enable"); // MEM0 byte mode
|
||||
BIT(val, 8) ? "1 cycle" : "0 cycles", // MEM0 bus hold
|
||||
BIT(val, 28) ? "disabled" : "enabled"); // MEM0 parity
|
||||
}
|
||||
LOG("MEM1 %s, bus hold break %s, parity %s, byte %s\n",
|
||||
size[BIT(val, 2, 2)], // MEM1 bus size
|
||||
@ -495,11 +692,7 @@ void hyperstone_device::update_memory_control()
|
||||
|
||||
// install SDRAM mode and control handlers if appropriate
|
||||
if (!BIT(val, 21) && !BIT(val, 22))
|
||||
{
|
||||
m_program->unmap_read(0x20000000, 0x3fffffff);
|
||||
m_program->install_write_handler(0x20000000, 0x2fffffff, emu::rw_delegate(*this, FUNC(hyperstone_device::sdram_mode_w)));
|
||||
m_program->install_write_handler(0x30000000, 0x3fffffff, emu::rw_delegate(*this, FUNC(hyperstone_device::sdram_control_w)));
|
||||
}
|
||||
install_sdram_mode_control();
|
||||
|
||||
// bits 14..12 EntryTableMap
|
||||
const int which = (val & 0x7000) >> 12;
|
||||
@ -507,13 +700,64 @@ void hyperstone_device::update_memory_control()
|
||||
m_core->trap_entry = s_trap_entries[which];
|
||||
}
|
||||
|
||||
void hyperstone_device::sdram_mode_w(offs_t offset, uint32_t data)
|
||||
void hyperstone_xsr_device::update_memory_control()
|
||||
{
|
||||
const uint32_t val = m_core->global_regs[MCR_REGISTER];
|
||||
|
||||
static char const *const entrymap[8] = { "MEM0", "MEM1", "MEM2", "IRAM", "reserved", "reserved", "reserved", "MEM3" };
|
||||
LOG("%s: Set MCR = 0x%08x, entry map in %s\n",
|
||||
machine().describe_context(),
|
||||
val,
|
||||
entrymap[BIT(val, 12, 3)]);
|
||||
|
||||
static char const *const size[4] = { "32 bit", "reserved", "16 bit", "8 bit" };
|
||||
if (BIT(val, 21))
|
||||
{
|
||||
LOG("MEM0 %s, bus hold break %s, parity %s\n",
|
||||
size[BIT(val, 0, 2)], // MEM0 bus size
|
||||
BIT(val, 8) ? "disabled" : "enabled", // MEM0 bus hold break
|
||||
BIT(val, 28) ? "disabled" : "enabled"); // MEM0 parity
|
||||
}
|
||||
else
|
||||
{
|
||||
static char const *const dramtype[4] = { "S", "S", "EDO ", "fast page " };
|
||||
LOG("MEM0 %s %sDRAM, hold time %s, parity %s\n",
|
||||
size[BIT(val, 0, 2)], // MEM0 bus size
|
||||
dramtype[bitswap<2>(val, 22, 15)], // MEM0 DRAM type
|
||||
BIT(val, 8) ? "1 cycle" : "0 cycles", // MEM0 bus hold
|
||||
BIT(val, 28) ? "disabled" : "enabled"); // MEM0 parity
|
||||
}
|
||||
LOG("MEM1 %s, bus hold break %s, parity %s\n",
|
||||
size[BIT(val, 2, 2)], // MEM1 bus size
|
||||
BIT(val, 9) ? "disabled" : "enabled", // MEM1 bus hold break
|
||||
BIT(val, 29) ? "disabled" : "enabled"); // MEM1 parity
|
||||
LOG("MEM2 %s, bus hold break %s, parity %s, wait %s\n",
|
||||
size[BIT(val, 4, 2)], // MEM2 bus size
|
||||
BIT(val, 10) ? "disabled" : "enabled", // MEM2 bus hold break
|
||||
BIT(val, 30) ? "disabled" : "enabled", // MEM2 parity
|
||||
BIT(val, 26) ? "disabled" : "enabled"); // MEM2 wait
|
||||
LOG("MEM3 %s, bus hold break %s, parity %s\n",
|
||||
size[BIT(val, 6, 2)], // MEM3 bus size
|
||||
BIT(val, 11) ? "disabled" : "enabled", // MEM3 bus hold break
|
||||
BIT(val, 31) ? "disabled" : "enabled"); // MEM3 parity
|
||||
|
||||
// install SDRAM mode and control handlers if appropriate
|
||||
if (!BIT(val, 21) && !BIT(val, 22))
|
||||
install_sdram_mode_control();
|
||||
|
||||
// bits 14..12 EntryTableMap
|
||||
const int which = (val & 0x7000) >> 12;
|
||||
assert(which < 4 || which == 7);
|
||||
m_core->trap_entry = s_trap_entries[which];
|
||||
}
|
||||
|
||||
void hyperstone_xs_device::sdram_mode_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
// writes to mode register of the connected SDRAM
|
||||
LOG("%s: set SDRAM mode = 0x%07x\n", machine().describe_context(), offset);
|
||||
}
|
||||
|
||||
void hyperstone_device::sdram_control_w(offs_t offset, uint32_t data)
|
||||
void hyperstone_xs_device::sdram_control_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
const uint32_t val = offset << 2;
|
||||
LOG("%s: set SDCR = 0x%08x\n", machine().describe_context(), val);
|
||||
@ -525,24 +769,58 @@ void hyperstone_device::sdram_control_w(offs_t offset, uint32_t data)
|
||||
BIT(val, 3) ? " / 2" : "");
|
||||
}
|
||||
|
||||
void hyperstone_xsr_device::sdram_control_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
const uint32_t val = offset << 2;
|
||||
static char const *const sdclk[4] = { "CPU clock", "reserved", "CPU clock / 2", "CPU clock / 4" };
|
||||
LOG("%s: set SDCR = 0x%08x\n", machine().describe_context(), val);
|
||||
LOG("MEM0 SDRAM bank bits 0x%08x, second SDRAM chip select CS#1 %s, A%u selects CS#0/CS#1, CAS latency %s, SDCLK based on %s %s, %sdelayed synchronisation\n",
|
||||
BIT(val, 12, 9) << 20,
|
||||
BIT(val, 11) ? "disabled" : "enabled",
|
||||
BIT(val, 8, 3) + 21,
|
||||
BIT(val, 6) ? "2 clock cycles" : "1 clock cycle",
|
||||
BIT(val, 5) ? "rising" : "falling",
|
||||
sdclk[BIT(val, 2, 2)],
|
||||
BIT(val, 4) ? "non-" : "");
|
||||
}
|
||||
|
||||
void hyperstone_xs_device::install_sdram_mode_control()
|
||||
{
|
||||
if (!m_sdram_installed)
|
||||
{
|
||||
m_program->unmap_read(0x20000000, 0x3fffffff);
|
||||
m_program->install_write_handler(0x20000000, 0x2fffffff, emu::rw_delegate(*this, FUNC(hyperstone_xs_device::sdram_mode_w)));
|
||||
m_program->install_write_handler(0x30000000, 0x3fffffff, emu::rw_delegate(*this, FUNC(hyperstone_xs_device::sdram_control_w)));
|
||||
|
||||
m_sdram_installed = true;
|
||||
}
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER( hyperstone_device::timer_callback )
|
||||
{
|
||||
int update = param;
|
||||
|
||||
/* update the values if necessary */
|
||||
// update the values if necessary
|
||||
if (update)
|
||||
{
|
||||
update_timer_prescale();
|
||||
}
|
||||
|
||||
/* see if the timer is right for firing */
|
||||
// see if the timer is right for firing
|
||||
compute_tr();
|
||||
if (!((m_core->tr_result - TCR) & 0x80000000))
|
||||
{
|
||||
m_core->timer_int_pending = 1;
|
||||
|
||||
/* adjust ourselves for the next time */
|
||||
if (!BIT(FCR, 23))
|
||||
{
|
||||
if (m_core->powerdown)
|
||||
LOG("exiting power down for timer\n");
|
||||
m_core->powerdown = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// adjust ourselves for the next time
|
||||
adjust_timer_interrupt();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1060,8 +1338,6 @@ void hyperstone_device::check_interrupts()
|
||||
|
||||
void hyperstone_device::device_start()
|
||||
{
|
||||
m_instruction_length_valid = false;
|
||||
|
||||
m_core = (internal_hyperstone_state *)m_cache.alloc_near(sizeof(internal_hyperstone_state));
|
||||
memset(m_core, 0, sizeof(internal_hyperstone_state));
|
||||
|
||||
@ -1081,9 +1357,14 @@ void hyperstone_device::device_start()
|
||||
memset(m_op_counts, 0, sizeof(uint32_t) * 256);
|
||||
memset(m_core->global_regs, 0, sizeof(uint32_t) * 32);
|
||||
memset(m_core->local_regs, 0, sizeof(uint32_t) * 64);
|
||||
m_op = 0;
|
||||
m_core->intblock = 0;
|
||||
m_core->powerdown = 0;
|
||||
|
||||
m_power_down_req = 1;
|
||||
|
||||
m_op = 0;
|
||||
m_instruction_length = 0;
|
||||
m_instruction_length_valid = false;
|
||||
|
||||
m_program = &space(AS_PROGRAM);
|
||||
if (m_program->data_width() == 16)
|
||||
@ -1135,6 +1416,7 @@ void hyperstone_device::device_start()
|
||||
m_drcuml->symbol_add(&m_core->delay_slot, sizeof(m_core->delay_slot), "delay_slot");
|
||||
m_drcuml->symbol_add(&m_core->delay_slot_taken, sizeof(m_core->delay_slot_taken), "delay_slot_taken");
|
||||
m_drcuml->symbol_add(&m_core->intblock, sizeof(m_core->intblock), "intblock");
|
||||
m_drcuml->symbol_add(&m_core->powerdown, sizeof(m_core->powerdown), "powerdown");
|
||||
m_drcuml->symbol_add(&m_core->arg0, sizeof(m_core->arg0), "arg0");
|
||||
m_drcuml->symbol_add(&m_core->arg1, sizeof(m_core->arg1), "arg1");
|
||||
m_drcuml->symbol_add(&m_core->icount, sizeof(m_core->icount), "icount");
|
||||
@ -1225,8 +1507,8 @@ void hyperstone_device::device_start()
|
||||
save_item(NAME(m_core->global_regs));
|
||||
save_item(NAME(m_core->local_regs));
|
||||
save_item(NAME(m_core->trap_entry));
|
||||
save_item(NAME(m_instruction_length));
|
||||
save_item(NAME(m_core->intblock));
|
||||
save_item(NAME(m_core->powerdown));
|
||||
save_item(NAME(m_core->delay_pc));
|
||||
save_item(NAME(m_core->delay_slot));
|
||||
save_item(NAME(m_core->delay_slot_taken));
|
||||
@ -1241,33 +1523,40 @@ void hyperstone_device::device_start()
|
||||
save_item(NAME(m_core->clock_cycles_4));
|
||||
save_item(NAME(m_core->clock_cycles_6));
|
||||
save_item(NAME(m_core->clock_cycles_36));
|
||||
save_item(NAME(m_power_down_req));
|
||||
save_item(NAME(m_instruction_length));
|
||||
|
||||
// set our instruction counter
|
||||
set_icountptr(m_core->icount);
|
||||
}
|
||||
|
||||
void e116t_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 0;
|
||||
}
|
||||
|
||||
void e116xt_device::device_start()
|
||||
void hyperstone_x_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 3;
|
||||
}
|
||||
|
||||
void e116xs_device::device_start()
|
||||
void hyperstone_xs_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
|
||||
m_core->clock_scale_mask = 7;
|
||||
m_sdram_installed = false;
|
||||
}
|
||||
|
||||
void e116xsr_device::device_start()
|
||||
void hyperstone_xs_device::device_post_load()
|
||||
{
|
||||
hyperstone_device::device_post_load();
|
||||
|
||||
const uint32_t mcr = m_core->global_regs[MCR_REGISTER];
|
||||
if (!BIT(mcr, 21) && !BIT(mcr, 22))
|
||||
install_sdram_mode_control();
|
||||
}
|
||||
|
||||
void e116_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 7;
|
||||
m_core->clock_scale_mask = 0;
|
||||
}
|
||||
|
||||
void gms30c2116_device::device_start()
|
||||
@ -1276,60 +1565,18 @@ void gms30c2116_device::device_start()
|
||||
m_core->clock_scale_mask = 0;
|
||||
}
|
||||
|
||||
void gms30c2216_device::device_start()
|
||||
void e132_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 0;
|
||||
}
|
||||
|
||||
void e132n_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 0;
|
||||
}
|
||||
|
||||
void e132t_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 0;
|
||||
}
|
||||
|
||||
void e132xn_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 3;
|
||||
}
|
||||
|
||||
void e132xt_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 3;
|
||||
}
|
||||
|
||||
void e132xs_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 7;
|
||||
}
|
||||
|
||||
void e132xsr_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 7;
|
||||
}
|
||||
|
||||
void gms30c2132_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 0;
|
||||
}
|
||||
|
||||
void gms30c2232_device::device_start()
|
||||
{
|
||||
hyperstone_device::device_start();
|
||||
m_core->clock_scale_mask = 0;
|
||||
}
|
||||
|
||||
void hyperstone_device::device_reset()
|
||||
{
|
||||
//TODO: Add different reset initializations for BCR, MCR, FCR, TPR
|
||||
@ -1557,10 +1804,31 @@ uint32_t hyperstone_device::execute_max_cycles() const noexcept
|
||||
|
||||
void hyperstone_device::execute_set_input(int inputnum, int state)
|
||||
{
|
||||
if (state)
|
||||
ISR |= 1 << inputnum;
|
||||
else
|
||||
ISR &= ~(1 << inputnum);
|
||||
if (inputnum < 7)
|
||||
{
|
||||
if (state)
|
||||
{
|
||||
ISR |= 1 << inputnum;
|
||||
|
||||
if ((inputnum < 4) && !BIT(FCR, 28 + inputnum))
|
||||
{
|
||||
if (m_core->powerdown)
|
||||
LOG("exiting power down for INT%d\n", inputnum + 1);
|
||||
m_core->powerdown = 0;
|
||||
}
|
||||
|
||||
if ((inputnum == 7) && ((FCR & 0x00000500) == 0x00000400))
|
||||
{
|
||||
if (m_core->powerdown)
|
||||
LOG("exiting power down for IO3\n", inputnum + 1);
|
||||
m_core->powerdown = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ISR &= ~(1 << inputnum);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void hyperstone_device::hyperstone_reserved()
|
||||
@ -1636,6 +1904,12 @@ void hyperstone_device::execute_run()
|
||||
|
||||
while (m_core->icount > 0)
|
||||
{
|
||||
if (m_core->powerdown)
|
||||
{
|
||||
m_core->icount = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (--m_core->intblock <= 0)
|
||||
{
|
||||
m_core->intblock = 0;
|
||||
@ -1934,14 +2208,12 @@ void hyperstone_device::execute_run()
|
||||
}
|
||||
}
|
||||
|
||||
DEFINE_DEVICE_TYPE(E116T, e116t_device, "e116t", "hyperstone E1-16T")
|
||||
DEFINE_DEVICE_TYPE(E116XT, e116xt_device, "e116xt", "hyperstone E1-16XT")
|
||||
DEFINE_DEVICE_TYPE(E116, e116_device, "e116", "hyperstone E1-16")
|
||||
DEFINE_DEVICE_TYPE(E116X, e116x_device, "e116x", "hyperstone E1-16X")
|
||||
DEFINE_DEVICE_TYPE(E116XS, e116xs_device, "e116xs", "hyperstone E1-16XS")
|
||||
DEFINE_DEVICE_TYPE(E116XSR, e116xsr_device, "e116xsr", "hyperstone E1-16XSR")
|
||||
DEFINE_DEVICE_TYPE(E132N, e132n_device, "e132n", "hyperstone E1-32N")
|
||||
DEFINE_DEVICE_TYPE(E132T, e132t_device, "e132t", "hyperstone E1-32T")
|
||||
DEFINE_DEVICE_TYPE(E132XN, e132xn_device, "e132xn", "hyperstone E1-32XN")
|
||||
DEFINE_DEVICE_TYPE(E132XT, e132xt_device, "e132xt", "hyperstone E1-32XT")
|
||||
DEFINE_DEVICE_TYPE(E132, e132_device, "e132", "hyperstone E1-32")
|
||||
DEFINE_DEVICE_TYPE(E132X, e132x_device, "e132x", "hyperstone E1-32X")
|
||||
DEFINE_DEVICE_TYPE(E132XS, e132xs_device, "e132xs", "hyperstone E1-32XS")
|
||||
DEFINE_DEVICE_TYPE(E132XSR, e132xsr_device, "e132xsr", "hyperstone E1-32XSR")
|
||||
DEFINE_DEVICE_TYPE(GMS30C2116, gms30c2116_device, "gms30c2116", "Hynix GMS30C2116")
|
||||
|
||||
@ -104,6 +104,7 @@ enum
|
||||
E132XS_L60, E132XS_L61, E132XS_L62, E132XS_L63
|
||||
};
|
||||
|
||||
|
||||
// Used by core CPU interface
|
||||
class hyperstone_device : public cpu_device, public hyperstone_disassembler::config
|
||||
{
|
||||
@ -157,6 +158,7 @@ protected:
|
||||
uint32_t delay_slot_taken;
|
||||
|
||||
int32_t intblock;
|
||||
uint32_t powerdown;
|
||||
|
||||
uint32_t arg0;
|
||||
uint32_t arg1;
|
||||
@ -221,10 +223,10 @@ protected:
|
||||
// construction/destruction
|
||||
hyperstone_device(
|
||||
const machine_config &mconfig,
|
||||
const device_type type,
|
||||
const char *tag,
|
||||
device_t *owner,
|
||||
uint32_t clock,
|
||||
const device_type type,
|
||||
uint32_t prg_data_width,
|
||||
uint32_t io_data_width,
|
||||
address_map_constructor internal_map);
|
||||
@ -258,18 +260,10 @@ protected:
|
||||
void update_timer_prescale();
|
||||
void compute_tr();
|
||||
void adjust_timer_interrupt();
|
||||
void update_bus_control();
|
||||
void update_memory_control();
|
||||
virtual void update_bus_control();
|
||||
virtual void update_memory_control();
|
||||
|
||||
void sdram_mode_w(offs_t offset, uint32_t data);
|
||||
void sdram_control_w(offs_t offset, uint32_t data);
|
||||
|
||||
void e116_16k_iram_map(address_map &map) ATTR_COLD;
|
||||
void e116_4k_iram_map(address_map &map) ATTR_COLD;
|
||||
void e116_8k_iram_map(address_map &map) ATTR_COLD;
|
||||
void e132_16k_iram_map(address_map &map) ATTR_COLD;
|
||||
void e132_4k_iram_map(address_map &map) ATTR_COLD;
|
||||
void e132_8k_iram_map(address_map &map) ATTR_COLD;
|
||||
void iram_4k_map(address_map &map) ATTR_COLD;
|
||||
|
||||
static uint32_t imm_length(uint16_t op);
|
||||
|
||||
@ -284,11 +278,14 @@ protected:
|
||||
std::function<const void * (offs_t)> m_prptr;
|
||||
address_space *m_io;
|
||||
|
||||
uint16_t m_op; // opcode
|
||||
|
||||
/* core state */
|
||||
// core state
|
||||
internal_hyperstone_state *m_core;
|
||||
|
||||
// onboard peripheral state
|
||||
uint8_t m_power_down_req;
|
||||
|
||||
// stuff used by the interpreter while handling one instruction
|
||||
uint16_t m_op;
|
||||
int32_t m_instruction_length;
|
||||
bool m_instruction_length_valid;
|
||||
|
||||
@ -427,6 +424,7 @@ private:
|
||||
uml::code_handle *m_nocode;
|
||||
uml::code_handle *m_interrupt_checks;
|
||||
uml::code_handle *m_out_of_cycles;
|
||||
uml::code_handle *m_eat_all_cycles;
|
||||
uml::code_handle *m_delay_taken[4];
|
||||
|
||||
uml::code_handle *m_mem_read8;
|
||||
@ -579,155 +577,124 @@ private:
|
||||
void generate_do(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc);
|
||||
};
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(E116T, e116t_device)
|
||||
DECLARE_DEVICE_TYPE(E116XT, e116xt_device)
|
||||
DECLARE_DEVICE_TYPE(E116XS, e116xs_device)
|
||||
DECLARE_DEVICE_TYPE(E116XSR, e116xsr_device)
|
||||
DECLARE_DEVICE_TYPE(E132N, e132n_device)
|
||||
DECLARE_DEVICE_TYPE(E132T, e132t_device)
|
||||
DECLARE_DEVICE_TYPE(E132XN, e132xn_device)
|
||||
DECLARE_DEVICE_TYPE(E132XT, e132xt_device)
|
||||
DECLARE_DEVICE_TYPE(E132XS, e132xs_device)
|
||||
DECLARE_DEVICE_TYPE(E132XSR, e132xsr_device)
|
||||
DECLARE_DEVICE_TYPE(GMS30C2116, gms30c2116_device)
|
||||
DECLARE_DEVICE_TYPE(GMS30C2132, gms30c2132_device)
|
||||
DECLARE_DEVICE_TYPE(GMS30C2216, gms30c2216_device)
|
||||
DECLARE_DEVICE_TYPE(GMS30C2232, gms30c2232_device)
|
||||
|
||||
class hyperstone_x_device : public hyperstone_device
|
||||
{
|
||||
protected:
|
||||
using hyperstone_device::hyperstone_device;
|
||||
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
|
||||
virtual void update_memory_control() override;
|
||||
|
||||
void iram_8k_map(address_map &map) ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> e116t_device
|
||||
class hyperstone_xs_device : public hyperstone_device
|
||||
{
|
||||
protected:
|
||||
using hyperstone_device::hyperstone_device;
|
||||
|
||||
class e116t_device : public hyperstone_device
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
virtual void device_post_load() override ATTR_COLD;
|
||||
|
||||
virtual void update_memory_control() override;
|
||||
|
||||
void sdram_mode_w(offs_t offset, uint32_t data);
|
||||
virtual void sdram_control_w(offs_t offset, uint32_t data);
|
||||
|
||||
void install_sdram_mode_control();
|
||||
|
||||
void iram_16k_map(address_map &map) ATTR_COLD;
|
||||
|
||||
private:
|
||||
bool m_sdram_installed;
|
||||
};
|
||||
|
||||
|
||||
class hyperstone_xsr_device : public hyperstone_xs_device
|
||||
{
|
||||
protected:
|
||||
using hyperstone_xs_device::hyperstone_xs_device;
|
||||
|
||||
virtual void update_bus_control() override;
|
||||
virtual void update_memory_control() override;
|
||||
|
||||
virtual void sdram_control_w(offs_t offset, uint32_t data) override;
|
||||
};
|
||||
|
||||
|
||||
class e116_device : public hyperstone_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e116t_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
e116_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> e116xt_device
|
||||
|
||||
class e116xt_device : public hyperstone_device
|
||||
class e116x_device : public hyperstone_x_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e116xt_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
e116x_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
};
|
||||
|
||||
|
||||
// ======================> e116xs_device
|
||||
|
||||
class e116xs_device : public hyperstone_device
|
||||
class e116xs_device : public hyperstone_xs_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e116xs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> e116xsr_device
|
||||
|
||||
class e116xsr_device : public hyperstone_device
|
||||
class e116xsr_device : public hyperstone_xsr_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e116xsr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> e132n_device
|
||||
|
||||
class e132n_device : public hyperstone_device
|
||||
class e132_device : public hyperstone_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e132n_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
e132_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> e132t_device
|
||||
|
||||
class e132t_device : public hyperstone_device
|
||||
class e132x_device : public hyperstone_x_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e132t_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
e132x_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
};
|
||||
|
||||
|
||||
// ======================> e132xn_device
|
||||
|
||||
class e132xn_device : public hyperstone_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e132xn_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> e132xt_device
|
||||
|
||||
class e132xt_device : public hyperstone_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e132xt_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> e132xs_device
|
||||
|
||||
class e132xs_device : public hyperstone_device
|
||||
class e132xs_device : public hyperstone_xs_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e132xs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> e132xsr_device
|
||||
|
||||
class e132xsr_device : public hyperstone_device
|
||||
class e132xsr_device : public hyperstone_xsr_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
e132xsr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> gms30c2116_device
|
||||
|
||||
class gms30c2116_device : public hyperstone_device
|
||||
{
|
||||
public:
|
||||
@ -739,8 +706,6 @@ protected:
|
||||
};
|
||||
|
||||
|
||||
// ======================> gms30c2132_device
|
||||
|
||||
class gms30c2132_device : public hyperstone_device
|
||||
{
|
||||
public:
|
||||
@ -752,30 +717,34 @@ protected:
|
||||
};
|
||||
|
||||
|
||||
// ======================> gms30c2216_device
|
||||
|
||||
class gms30c2216_device : public hyperstone_device
|
||||
class gms30c2216_device : public hyperstone_x_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
gms30c2216_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
// ======================> gms30c2232_device
|
||||
|
||||
class gms30c2232_device : public hyperstone_device
|
||||
class gms30c2232_device : public hyperstone_x_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
gms30c2232_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
};
|
||||
|
||||
|
||||
DECLARE_DEVICE_TYPE(E116, e116_device)
|
||||
DECLARE_DEVICE_TYPE(E116X, e116x_device)
|
||||
DECLARE_DEVICE_TYPE(E116XS, e116xs_device)
|
||||
DECLARE_DEVICE_TYPE(E116XSR, e116xsr_device)
|
||||
DECLARE_DEVICE_TYPE(E132, e132_device)
|
||||
DECLARE_DEVICE_TYPE(E132X, e132x_device)
|
||||
DECLARE_DEVICE_TYPE(E132XS, e132xs_device)
|
||||
DECLARE_DEVICE_TYPE(E132XSR, e132xsr_device)
|
||||
DECLARE_DEVICE_TYPE(GMS30C2116, gms30c2116_device)
|
||||
DECLARE_DEVICE_TYPE(GMS30C2132, gms30c2132_device)
|
||||
DECLARE_DEVICE_TYPE(GMS30C2216, gms30c2216_device)
|
||||
DECLARE_DEVICE_TYPE(GMS30C2232, gms30c2232_device)
|
||||
|
||||
|
||||
#endif // MAME_CPU_E132XS_E132XS_H
|
||||
|
||||
@ -116,6 +116,13 @@ struct hyperstone_device::c_funcs
|
||||
|
||||
void hyperstone_device::execute_run_drc()
|
||||
{
|
||||
if (m_core->powerdown)
|
||||
{
|
||||
if (m_core->icount > 0)
|
||||
m_core->icount = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
// reset the cache if dirty
|
||||
if (m_cache_dirty)
|
||||
{
|
||||
@ -421,6 +428,7 @@ void hyperstone_device::static_generate_helpers(drcuml_block &block, uml::code_l
|
||||
// forward references
|
||||
alloc_handle(*m_drcuml, m_entry, "entry");
|
||||
alloc_handle(*m_drcuml, m_nocode, "nocode");
|
||||
alloc_handle(*m_drcuml, m_eat_all_cycles, "eat_all_cycles");
|
||||
alloc_handle(*m_drcuml, m_out_of_cycles, "out_of_cycles");
|
||||
alloc_handle(*m_drcuml, m_delay_taken[0], "delay_taken");
|
||||
alloc_handle(*m_drcuml, m_delay_taken[1], "delay_taken_s");
|
||||
@ -445,6 +453,9 @@ void hyperstone_device::static_generate_helpers(drcuml_block &block, uml::code_l
|
||||
UML_EXIT(block, EXECUTE_MISSING_CODE);
|
||||
|
||||
// out of cycles exception handler
|
||||
UML_HANDLE(block, *m_eat_all_cycles);
|
||||
UML_CMP(block, mem(&m_core->icount), 0);
|
||||
UML_MOVc(block, uml::COND_G, mem(&m_core->icount), 0);
|
||||
UML_HANDLE(block, *m_out_of_cycles);
|
||||
//save_fast_iregs(block);
|
||||
UML_EXIT(block, EXECUTE_OUT_OF_CYCLES);
|
||||
|
||||
@ -276,6 +276,8 @@ void hyperstone_device::generate_set_global_register_high(drcuml_block &block, c
|
||||
case MCR_REGISTER: // G27 Memory Control Register
|
||||
UML_MOV(block, mem(&m_core->global_regs[dst_code]), src);
|
||||
UML_CALLC(block, &c_funcs::update_memory_control, this);
|
||||
UML_TEST(block, mem(&m_core->powerdown), ~uint32_t(0));
|
||||
UML_CALLHc(block, uml::COND_NZ, *m_eat_all_cycles);
|
||||
break;
|
||||
default:
|
||||
throw emu_fatalerror("%s: invalid high global register G%u\n", dst_code);
|
||||
@ -677,7 +679,7 @@ void hyperstone_device::generate_trap_exception_or_int(drcuml_block &block, uml:
|
||||
template <hyperstone_device::reg_bank DstGlobal, hyperstone_device::reg_bank SrcGlobal, typename T>
|
||||
inline void hyperstone_device::generate_logic_op(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, T &&body)
|
||||
{
|
||||
// body takes operands in I0 and I1 and should update I0 and set Z flag
|
||||
// body takes operands in dst and src and should update dst and set Z flag
|
||||
// body must not clobber I2 or I3
|
||||
|
||||
UML_MOV(block, I7, mem(&m_core->clock_cycles_1));
|
||||
@ -691,38 +693,56 @@ inline void hyperstone_device::generate_logic_op(drcuml_block &block, compiler_s
|
||||
if (!SrcGlobal || !DstGlobal)
|
||||
UML_ROLAND(block, I3, I2, 32 - FP_SHIFT, 0x7f);
|
||||
|
||||
generate_load_operand(block, compiler, SrcGlobal, src_code, uml::I1, uml::I1);
|
||||
generate_load_operand(block, compiler, DstGlobal, dst_code, uml::I0, uml::I3);
|
||||
uml::parameter src = uml::I1;
|
||||
if (!SrcGlobal)
|
||||
generate_load_operand(block, compiler, SrcGlobal, src_code, src, src);
|
||||
else
|
||||
src = uml::mem(&m_core->global_regs[src_code]);
|
||||
|
||||
body();
|
||||
uml::parameter dst = uml::I0;
|
||||
if (!DstGlobal || (dst_code <= SR_REGISTER))
|
||||
generate_load_operand(block, compiler, DstGlobal, dst_code, dst, uml::I3);
|
||||
else
|
||||
dst = uml::mem(&m_core->global_regs[dst_code]);
|
||||
|
||||
body(dst, src);
|
||||
|
||||
UML_SETc(block, uml::COND_Z, I1);
|
||||
UML_ROLINS(block, I2, I1, Z_SHIFT, Z_MASK);
|
||||
UML_MOV(block, DRC_SR, I2);
|
||||
|
||||
generate_set_dst(block, compiler, desc, DstGlobal, dst_code, uml::I0, uml::I3, false);
|
||||
if (!DstGlobal || (dst_code <= SR_REGISTER))
|
||||
generate_set_dst(block, compiler, desc, DstGlobal, dst_code, dst, uml::I3, false);
|
||||
}
|
||||
|
||||
template <hyperstone_device::reg_bank DstGlobal, typename T>
|
||||
inline void hyperstone_device::generate_logic_op_imm(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint32_t dst_code, T &&body)
|
||||
{
|
||||
// clobbers I0, I1 and I3
|
||||
// body should update I0 and set Z flag
|
||||
// body should update dst and set Z flag
|
||||
// body must not clobber I2 or I3
|
||||
|
||||
UML_MOV(block, I2, DRC_SR);
|
||||
if (!DstGlobal)
|
||||
UML_ROLAND(block, I3, I2, 32 - FP_SHIFT, 0x7f);
|
||||
|
||||
generate_load_operand(block, compiler, DstGlobal, dst_code, uml::I0, uml::I3);
|
||||
if (!DstGlobal || (dst_code <= SR_REGISTER))
|
||||
{
|
||||
generate_load_operand(block, compiler, DstGlobal, dst_code, uml::I0, uml::I3);
|
||||
|
||||
body();
|
||||
body(uml::I0);
|
||||
}
|
||||
else
|
||||
{
|
||||
body(uml::mem(&m_core->global_regs[dst_code]));
|
||||
}
|
||||
|
||||
UML_SETc(block, uml::COND_Z, I1);
|
||||
UML_ROLINS(block, I2, I1, Z_SHIFT, Z_MASK);
|
||||
UML_MOV(block, DRC_SR, I2);
|
||||
|
||||
generate_set_dst(block, compiler, desc, DstGlobal, dst_code, uml::I0, uml::I3, false);
|
||||
if (!DstGlobal || (dst_code <= SR_REGISTER))
|
||||
generate_set_dst(block, compiler, desc, DstGlobal, dst_code, uml::I0, uml::I3, false);
|
||||
}
|
||||
|
||||
|
||||
@ -1747,7 +1767,10 @@ void hyperstone_device::generate_and(drcuml_block &block, compiler_state &compil
|
||||
block,
|
||||
compiler,
|
||||
desc,
|
||||
[&block] () { UML_AND(block, I0, I0, I1); });
|
||||
[&block] (uml::parameter dst, uml::parameter src)
|
||||
{
|
||||
UML_AND(block, dst, dst, src);
|
||||
});
|
||||
}
|
||||
|
||||
|
||||
@ -1758,7 +1781,11 @@ void hyperstone_device::generate_andn(drcuml_block &block, compiler_state &compi
|
||||
block,
|
||||
compiler,
|
||||
desc,
|
||||
[&block] () { UML_XOR(block, I1, I1, ~uint32_t(0)); UML_AND(block, I0, I0, I1); });
|
||||
[&block] (uml::parameter dst, uml::parameter src)
|
||||
{
|
||||
UML_XOR(block, I1, src, ~uint32_t(0));
|
||||
UML_AND(block, dst, dst, I1);
|
||||
});
|
||||
}
|
||||
|
||||
|
||||
@ -1769,7 +1796,10 @@ void hyperstone_device::generate_or(drcuml_block &block, compiler_state &compile
|
||||
block,
|
||||
compiler,
|
||||
desc,
|
||||
[&block] () { UML_OR(block, I0, I0, I1); });
|
||||
[&block] (uml::parameter dst, uml::parameter src)
|
||||
{
|
||||
UML_OR(block, dst, dst, src);
|
||||
});
|
||||
}
|
||||
|
||||
|
||||
@ -1780,7 +1810,10 @@ void hyperstone_device::generate_xor(drcuml_block &block, compiler_state &compil
|
||||
block,
|
||||
compiler,
|
||||
desc,
|
||||
[&block] () { UML_XOR(block, I0, I0, I1); });
|
||||
[&block] (uml::parameter dst, uml::parameter src)
|
||||
{
|
||||
UML_XOR(block, dst, dst, src);
|
||||
});
|
||||
}
|
||||
|
||||
|
||||
@ -2004,13 +2037,15 @@ void hyperstone_device::generate_cmpbi(drcuml_block &block, compiler_state &comp
|
||||
|
||||
const uint16_t op = desc->opptr.w[0];
|
||||
const uint32_t dst_code = (op & 0xf0) >> 4;
|
||||
|
||||
if (!DstGlobal)
|
||||
UML_ROLAND(block, I3, DRC_SR, 32 - FP_SHIFT, 0x7f);
|
||||
|
||||
generate_load_operand(block, compiler, DstGlobal, dst_code, uml::I0, uml::I3);
|
||||
|
||||
const uint32_t n = ((op & 0x100) >> 4) | (op & 0x0f);
|
||||
|
||||
UML_MOV(block, I2, DRC_SR);
|
||||
if (!DstGlobal)
|
||||
UML_ROLAND(block, I3, I2, 32 - FP_SHIFT, 0x7f);
|
||||
|
||||
if (!DstGlobal || !n)
|
||||
generate_load_operand(block, compiler, DstGlobal, dst_code, uml::I0, uml::I3);
|
||||
|
||||
if (n)
|
||||
{
|
||||
uint32_t src;
|
||||
@ -2021,9 +2056,12 @@ void hyperstone_device::generate_cmpbi(drcuml_block &block, compiler_state &comp
|
||||
else
|
||||
src = op & 0xf;
|
||||
|
||||
UML_TEST(block, I0, src);
|
||||
if (DstGlobal)
|
||||
UML_TEST(block, mem(&m_core->global_regs[dst_code]), src);
|
||||
else
|
||||
UML_TEST(block, I0, src);
|
||||
UML_SETc(block, uml::COND_Z, I1);
|
||||
UML_ROLINS(block, DRC_SR, I1, Z_SHIFT, Z_MASK);
|
||||
UML_ROLINS(block, I2, I1, Z_SHIFT, Z_MASK);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -2037,14 +2075,16 @@ void hyperstone_device::generate_cmpbi(drcuml_block &block, compiler_state &comp
|
||||
UML_JMPc(block, uml::COND_Z, or_mask);
|
||||
UML_TEST(block, I0, 0x000000ff);
|
||||
UML_JMPc(block, uml::COND_Z, or_mask);
|
||||
UML_AND(block, DRC_SR, DRC_SR, ~Z_MASK);
|
||||
UML_AND(block, I2, I2, ~Z_MASK);
|
||||
UML_JMP(block, done);
|
||||
|
||||
UML_LABEL(block, or_mask);
|
||||
UML_OR(block, DRC_SR, DRC_SR, Z_MASK);
|
||||
UML_OR(block, I2, I2, Z_MASK);
|
||||
|
||||
UML_LABEL(block, done);
|
||||
}
|
||||
|
||||
UML_MOV(block, DRC_SR, I2);
|
||||
}
|
||||
|
||||
|
||||
@ -2069,7 +2109,7 @@ void hyperstone_device::generate_andni(drcuml_block &block, compiler_state &comp
|
||||
compiler,
|
||||
desc,
|
||||
(op & 0xf0) >> 4,
|
||||
[&block, src] () { UML_AND(block, I0, I0, src); });
|
||||
[&block, src] (uml::parameter dst) { UML_AND(block, dst, dst, src); });
|
||||
}
|
||||
|
||||
|
||||
@ -2091,7 +2131,7 @@ void hyperstone_device::generate_ori(drcuml_block &block, compiler_state &compil
|
||||
compiler,
|
||||
desc,
|
||||
(op & 0xf0) >> 4,
|
||||
[&block, src] () { UML_OR(block, I0, I0, src); });
|
||||
[&block, src] (uml::parameter dst) { UML_OR(block, dst, dst, src); });
|
||||
}
|
||||
|
||||
|
||||
@ -2113,7 +2153,7 @@ void hyperstone_device::generate_xori(drcuml_block &block, compiler_state &compi
|
||||
compiler,
|
||||
desc,
|
||||
(op & 0xf0) >> 4,
|
||||
[&block, src] () { UML_XOR(block, I0, I0, src); });
|
||||
[&block, src] (uml::parameter dst) { UML_XOR(block, dst, dst, src); });
|
||||
}
|
||||
|
||||
|
||||
@ -2540,9 +2580,9 @@ void hyperstone_device::generate_shl(drcuml_block &block, compiler_state &compil
|
||||
UML_MOVc(block, uml::COND_NS, I5, 0);
|
||||
generate_update_nz(block, compiler, uml::I2);
|
||||
|
||||
UML_XOR(block, I4, I4, I5);
|
||||
UML_CMP(block, I4, I5);
|
||||
UML_MOV(block, I1, V_MASK);
|
||||
UML_MOVc(block, uml::COND_Z, I1, 0);
|
||||
UML_MOVc(block, uml::COND_E, I1, 0);
|
||||
UML_OR(block, I2, I2, I1);
|
||||
|
||||
UML_MOV(block, DRC_SR, I2);
|
||||
@ -2584,9 +2624,9 @@ void hyperstone_device::generate_shli(drcuml_block &block, compiler_state &compi
|
||||
|
||||
if (n)
|
||||
{
|
||||
UML_XOR(block, I4, I4, I5);
|
||||
UML_CMP(block, I4, I5);
|
||||
UML_MOV(block, I1, V_MASK);
|
||||
UML_MOVc(block, uml::COND_Z, I1, 0);
|
||||
UML_MOVc(block, uml::COND_E, I1, 0);
|
||||
UML_OR(block, I2, I2, I1);
|
||||
}
|
||||
|
||||
@ -2651,9 +2691,9 @@ void hyperstone_device::generate_rol(drcuml_block &block, compiler_state &compil
|
||||
|
||||
UML_AND(block, I1, I5, I0);
|
||||
UML_ROLINS(block, I2, I1, C_SHIFT, C_MASK);
|
||||
UML_XOR(block, I4, I4, I1);
|
||||
UML_CMP(block, I4, I1);
|
||||
UML_MOV(block, I1, V_MASK);
|
||||
UML_MOVc(block, uml::COND_Z, I1, 0);
|
||||
UML_MOVc(block, uml::COND_E, I1, 0);
|
||||
UML_OR(block, I2, I2, I1);
|
||||
|
||||
UML_MOV(block, DRC_SR, I2);
|
||||
|
||||
@ -691,7 +691,7 @@ INPUT_PORTS_END
|
||||
void eolith_state::eolith45(machine_config &config)
|
||||
{
|
||||
// TODO: turning off single instruction mode makes Raccoon World slow due to constant recompilation
|
||||
E132N(config, m_maincpu, 45'000'000).set_single_instruction_mode(true); /* 45 MHz */
|
||||
E132(config, m_maincpu, 45_MHz_XTAL).set_single_instruction_mode(true); // E1-32N (PQFP)
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &eolith_state::eolith_map);
|
||||
TIMER(config, "scantimer").configure_scanline(FUNC(eolith_state::eolith_speedup), "screen", 0, 1);
|
||||
|
||||
|
||||
@ -166,7 +166,7 @@ void eolith16_state::eolith16_palette(palette_device &palette) const
|
||||
|
||||
void eolith16_state::eolith16(machine_config &config)
|
||||
{
|
||||
E116T(config, m_maincpu, XTAL(60'000'000)); /* no internal multiplier */
|
||||
E116(config, m_maincpu, 60_MHz_XTAL); // E1-16T (TQFP), no internal multiplier
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &eolith16_state::eolith16_map);
|
||||
TIMER(config, "scantimer").configure_scanline(FUNC(eolith16_state::eolith_speedup), "screen", 0, 1);
|
||||
|
||||
|
||||
@ -241,7 +241,7 @@ INPUT_PORTS_END
|
||||
void mosaicf2_state::mosaicf2(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
E132XN(config, m_maincpu, XTAL(20'000'000)*4); /* 4x internal multiplier */
|
||||
E132X(config, m_maincpu, 20_MHz_XTAL*4); // E1-32XN (PQFP), 4x internal multiplier
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &mosaicf2_state::common_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &mosaicf2_state::mosaicf2_io);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(mosaicf2_state::irq0_line_hold));
|
||||
|
||||
@ -523,7 +523,7 @@ void dgpix_bmkey_state::machine_reset()
|
||||
|
||||
void dgpix_state::dgpix_base(machine_config &config)
|
||||
{
|
||||
E132XT(config, m_maincpu, 20000000*4); /* 4x internal multiplier */
|
||||
E132X(config, m_maincpu, 20'000'000*4); // E1-32XT (TQFP), 4x internal multiplier
|
||||
m_maincpu->set_addrmap(AS_IO, &dgpix_state::io_map);
|
||||
|
||||
/* video hardware */
|
||||
|
||||
@ -692,7 +692,7 @@ GFXDECODE_END
|
||||
|
||||
void limenko_state::limenko(machine_config &config)
|
||||
{
|
||||
E132XN(config, m_maincpu, 20000000*4); /* 4x internal multiplier */
|
||||
E132X(config, m_maincpu, 20'000'000*4); // E1-32XN (PQFP), 4x internal multiplier
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &limenko_state::limenko_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &limenko_state::limenko_io_map);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(limenko_state::irq0_line_hold));
|
||||
@ -731,12 +731,12 @@ void limenko_state::limenko(machine_config &config)
|
||||
|
||||
void limenko_state::spotty(machine_config &config)
|
||||
{
|
||||
GMS30C2232(config, m_maincpu, 20000000); /* 20 MHz, no internal multiplier */
|
||||
GMS30C2232(config, m_maincpu, 20'000'000*4); // 20 MHz, 4x internal multiplier
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &limenko_state::spotty_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &limenko_state::spotty_io_map);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(limenko_state::irq0_line_hold));
|
||||
|
||||
at89c4051_device &audiocpu(AT89C4051(config, "audiocpu", 4000000));
|
||||
at89c4051_device &audiocpu(AT89C4051(config, "audiocpu", 4'000'000));
|
||||
audiocpu.port_in_cb<1>().set(FUNC(limenko_state::audiocpu_p1_r));
|
||||
audiocpu.port_out_cb<1>().set(FUNC(limenko_state::audiocpu_p1_w));
|
||||
audiocpu.port_in_cb<3>().set(FUNC(limenko_state::audiocpu_p3_r));
|
||||
|
||||
@ -80,7 +80,7 @@ protected:
|
||||
|
||||
private:
|
||||
// devices
|
||||
required_device<e132xt_device> m_maincpu;
|
||||
required_device<e132x_device> m_maincpu;
|
||||
required_device<okim6295_device> m_oki;
|
||||
required_device<palette_device> m_palette;
|
||||
required_device<hopper_device> m_hopper;
|
||||
@ -409,7 +409,7 @@ following clocks are on the PCB
|
||||
void mjsenpu_state::mjsenpu(machine_config &config)
|
||||
{
|
||||
// basic machine hardware
|
||||
E132XT(config, m_maincpu, 27000000*2); // ?? Mhz
|
||||
E132X(config, m_maincpu, 27'000'000*2); // E1-32XT (TQFP), ?? Mhz
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &mjsenpu_state::main_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &mjsenpu_state::main_portmap);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(mjsenpu_state::irq0_line_hold));
|
||||
|
||||
@ -489,7 +489,7 @@ void pasha2_state::machine_reset()
|
||||
void pasha2_state::pasha2(machine_config &config)
|
||||
{
|
||||
// basic machine hardware
|
||||
E116XT(config, m_maincpu, 20_MHz_XTAL*4); // 4x internal multiplier
|
||||
E116X(config, m_maincpu, 20_MHz_XTAL*4); // E1-16XT (TQFP), 4x internal multiplier
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &pasha2_state::pasha2_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &pasha2_state::pasha2_io);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(pasha2_state::irq0_line_hold));
|
||||
@ -527,7 +527,7 @@ void pasha2_state::zdrum(machine_config &config)
|
||||
|
||||
m_maincpu->set_force_no_drc(true); // gets a bit further
|
||||
|
||||
e116xt_device &audiocpu(E116XT(config.replace(), "audiocpu", 45_MHz_XTAL)); // type unknown, but it does look like Hyperstone code
|
||||
e116x_device &audiocpu(E116X(config.replace(), "audiocpu", 45_MHz_XTAL)); // type unknown, but it does look like Hyperstone code
|
||||
audiocpu.set_addrmap(AS_PROGRAM, &pasha2_state::zdrum_audio_map);
|
||||
|
||||
// TODO: MP3 hw, also PCB should be stereo according to test mode
|
||||
|
||||
@ -1169,7 +1169,7 @@ GFXDECODE_END
|
||||
|
||||
void vamphalf_state::common(machine_config &config)
|
||||
{
|
||||
E116T(config, m_maincpu, 50_MHz_XTAL); // 50 MHz
|
||||
E116(config, m_maincpu, 50_MHz_XTAL); // E1-16T (TQFP), 50 MHz
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &vamphalf_state::common_map);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(vamphalf_state::irq1_line_hold));
|
||||
|
||||
@ -1327,7 +1327,7 @@ void vamphalf_state::mrdig(machine_config &config)
|
||||
void vamphalf_qdsp_state::wyvernwg(machine_config &config)
|
||||
{
|
||||
common(config);
|
||||
E132T(config.replace(), m_maincpu, 50_MHz_XTAL); // 50 MHz
|
||||
E132(config.replace(), m_maincpu, 50_MHz_XTAL); // E1-32T (TQFP), 50 MHz
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &vamphalf_qdsp_state::common_32bit_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &vamphalf_qdsp_state::wyvernwg_io);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(vamphalf_state::irq1_line_hold));
|
||||
@ -1338,7 +1338,7 @@ void vamphalf_qdsp_state::wyvernwg(machine_config &config)
|
||||
void vamphalf_nvram_state::finalgdr(machine_config &config)
|
||||
{
|
||||
common(config);
|
||||
E132T(config.replace(), m_maincpu, 50_MHz_XTAL); // 50 MHz
|
||||
E132(config.replace(), m_maincpu, 50_MHz_XTAL); // E1-32T (TQFP), 50 MHz
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &vamphalf_nvram_state::common_32bit_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &vamphalf_nvram_state::finalgdr_io);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(vamphalf_state::irq1_line_hold));
|
||||
@ -1351,7 +1351,7 @@ void vamphalf_nvram_state::finalgdr(machine_config &config)
|
||||
void vamphalf_nvram_state::mrkickera(machine_config &config)
|
||||
{
|
||||
common(config);
|
||||
E132T(config.replace(), m_maincpu, 50_MHz_XTAL); // 50 MHz
|
||||
E132(config.replace(), m_maincpu, 50_MHz_XTAL); // E1-32T (TQFP), 50 MHz
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &vamphalf_nvram_state::common_32bit_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &vamphalf_nvram_state::mrkickera_io);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(vamphalf_state::irq1_line_hold));
|
||||
@ -1363,7 +1363,7 @@ void vamphalf_nvram_state::mrkickera(machine_config &config)
|
||||
|
||||
void vamphalf_state::aoh(machine_config &config)
|
||||
{
|
||||
E132XN(config, m_maincpu, 20_MHz_XTAL * 4); // 4x internal multiplier
|
||||
E132X(config, m_maincpu, 20_MHz_XTAL * 4); // E1-32XN (PQFP), 4x internal multiplier
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &vamphalf_state::aoh_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &vamphalf_state::aoh_io);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(vamphalf_state::irq1_line_hold));
|
||||
@ -1406,7 +1406,7 @@ void vamphalf_state::boonggab(machine_config &config)
|
||||
void vamphalf_qdsp_state::yorijori(machine_config &config)
|
||||
{
|
||||
common(config);
|
||||
E132T(config.replace(), m_maincpu, 50_MHz_XTAL); // 50 MHz
|
||||
E132(config.replace(), m_maincpu, 50_MHz_XTAL); // E1-32T (TQFP), 50 MHz
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &vamphalf_qdsp_state::yorijori_32bit_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &vamphalf_qdsp_state::yorijori_io);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(vamphalf_state::irq2_line_hold));
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
// copyright-holders:
|
||||
|
||||
/*
|
||||
プチ☆ロット (Petite Lot) by Showa Giken (Shoken) - mechanical slot machine
|
||||
プチ☆ロット (Petit Lot) by Showa Giken (Shoken) - mechanical slot machine
|
||||
Flyer shows at least two game titles: Time Cross and Hyper Rush.
|
||||
Are those actually different ROMs or just different covers?
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user