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https://github.com/holub/mame
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m68kmmu: split m68881_ops() into subfunctions (#4185)
This commit is contained in:
dxl
R. Belmont
parent
769e13f265
commit
3c36b423ea
@ -8258,7 +8258,7 @@ M68KMAKE_OP(pmmu, 32, ., .)
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{
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if ((CPU_TYPE_IS_EC020_PLUS()) && (m_has_pmmu))
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{
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m68881_mmu_ops();
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m68851_mmu_ops();
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}
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else
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{
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@ -691,11 +691,259 @@ uint32_t pmmu_translate_addr(uint32_t addr_in)
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m68851_mmu_ops: COP 0 MMU opcode handling
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*/
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void m68881_mmu_ops()
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void m68851_pload(const uint32_t ea, const uint16_t modes)
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{
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uint32_t ltmp = DECODE_EA_32(ea);
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uint32_t ptmp;
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ptmp = ltmp;
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if (m_pmmu_enabled)
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{
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if (CPU_TYPE_IS_040_PLUS())
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{
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ptmp = pmmu_translate_addr_with_fc_040(ltmp, modes & 0x07, 0);
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}
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else
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{
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ptmp = pmmu_translate_addr_with_fc(ltmp, modes & 0x07, 0);
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}
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}
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MMULOG("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp);
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// FIXME: rw bit?
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pmmu_atc_add(ltmp, ptmp, modes & 0x07);
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}
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void m68851_ptest(const uint32_t ea, const uint16_t modes)
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{
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uint32_t v_addr = DECODE_EA_32(ea);
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uint32_t p_addr;
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uint32_t fc = modes & 0x1f;
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switch (fc >> 3) {
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case 0:
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fc = fc == 0 ? m_sfc : m_dfc;
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break;
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case 1:
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fc = REG_D()[fc &7] &7;
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break;
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case 2:
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fc &=7;
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break;
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}
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if (CPU_TYPE_IS_040_PLUS())
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{
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p_addr = pmmu_translate_addr_with_fc_040(v_addr, fc, 1);
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}
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else
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{
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p_addr = pmmu_translate_addr_with_fc(v_addr, fc, 1);
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}
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m_mmu_sr = m_mmu_tmp_sr;
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MMULOG("PMMU: pc=%08x sp=%08x va=%08x pa=%08x PTEST fc=%x level=%x mmu_sr=%04x\n",
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m_ppc, REG_A()[7], v_addr, p_addr, fc, (modes >> 10) & 0x07, m_mmu_sr);
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if (modes & 0x100)
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{
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int areg = (modes >> 5) & 7;
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WRITE_EA_32(0x08 | areg, p_addr);
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}
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}
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void m68851_pmove_get(uint32_t ea, uint16_t modes)
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{
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switch ((modes>>10) & 0x3f)
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{
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case 0x02: // transparent translation register 0
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WRITE_EA_32(ea, m_mmu_tt0);
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MMULOG("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m_ppc, m_mmu_tt0);
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break;
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case 0x03: // transparent translation register 1
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WRITE_EA_32(ea, m_mmu_tt1);
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MMULOG("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m_ppc, m_mmu_tt1);
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break;
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case 0x10: // translation control register
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WRITE_EA_32(ea, m_mmu_tc);
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MMULOG("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m_ppc, m_mmu_tc);
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break;
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case 0x12: // supervisor root pointer
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WRITE_EA_64(ea, (uint64_t)m_mmu_srp_limit<<32 | (uint64_t)m_mmu_srp_aptr);
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MMULOG("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", m_ppc, m_mmu_srp_limit, m_mmu_srp_aptr);
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break;
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case 0x13: // CPU root pointer
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WRITE_EA_64(ea, (uint64_t)m_mmu_crp_limit<<32 | (uint64_t)m_mmu_crp_aptr);
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MMULOG("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", m_ppc, m_mmu_crp_limit, m_mmu_crp_aptr);
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break;
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default:
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logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m_pc);
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break;
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}
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}
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void m68851_pmove_put(uint32_t ea, uint16_t modes)
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{
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uint64_t temp64;
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switch ((modes>>13) & 7)
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{
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case 0:
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{
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uint32_t temp = READ_EA_32(ea);
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if (((modes>>10) & 7) == 2)
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{
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MMULOG("WRITE TT0 = 0x%08x\n", m_mmu_tt0);
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m_mmu_tt0 = temp;
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}
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else if (((modes>>10) & 7) == 3)
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{
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MMULOG("WRITE TT1 = 0x%08x\n", m_mmu_tt1);
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m_mmu_tt1 = temp;
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}
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break;
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}
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case 1:
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logerror("680x0: unknown PMOVE case 1, PC %x\n", m_pc);
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break;
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case 2:
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switch ((modes>>10) & 7)
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{
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case 0: // translation control register
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m_mmu_tc = READ_EA_32(ea);
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MMULOG("PMMU: TC = %08x\n", m_mmu_tc);
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if (m_mmu_tc & 0x80000000)
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{
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int bits = 0;
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for(int shift = 20; shift >= 0; shift -= 4) {
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bits += (m_mmu_tc >> shift) & 0x0f;
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}
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if (bits != 32 || !((m_mmu_tc >> 23) & 1)) {
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logerror("MMU: TC invalid!\n");
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m_mmu_tc &= ~0x80000000;
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m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
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} else {
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m_pmmu_enabled = 1;
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}
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MMULOG("PMMU enabled\n");
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}
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else
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{
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m_pmmu_enabled = 0;
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MMULOG("PMMU disabled\n");
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}
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if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP with FD bit clear
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{
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pmmu_atc_flush();
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}
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break;
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case 2: // supervisor root pointer
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temp64 = READ_EA_64(ea);
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m_mmu_srp_limit = (temp64>>32) & 0xffffffff;
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m_mmu_srp_aptr = temp64 & 0xffffffff;
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MMULOG("PMMU: SRP limit = %08x aptr = %08x\n", m_mmu_srp_limit, m_mmu_srp_aptr);
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// SRP type 0 is not allowed
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if ((m_mmu_srp_limit & 3) == 0) {
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m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
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return;
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}
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if (!(modes & 0x100))
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{
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pmmu_atc_flush();
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}
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break;
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case 3: // CPU root pointer
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temp64 = READ_EA_64(ea);
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m_mmu_crp_limit = (temp64>>32) & 0xffffffff;
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m_mmu_crp_aptr = temp64 & 0xffffffff;
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MMULOG("PMMU: CRP limit = %08x aptr = %08x\n", m_mmu_crp_limit, m_mmu_crp_aptr);
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// CRP type 0 is not allowed
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if ((m_mmu_crp_limit & 3) == 0) {
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m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
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return;
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}
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if (!(modes & 0x100))
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{
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pmmu_atc_flush();
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}
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break;
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case 7: // MC68851 Access Control Register
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if (m_cpu_type == CPU_TYPE_020)
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{
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// DomainOS on Apollo DN3000 will only reset this to 0
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uint16_t mmu_ac = READ_EA_16(ea);
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if (mmu_ac != 0)
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{
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MMULOG("680x0 PMMU: pc=%x PMOVE to mmu_ac=%08x\n",
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m_ppc, mmu_ac);
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}
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break;
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}
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// fall through; unknown PMOVE mode unless MC68020 with MC68851
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default:
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logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m_pc);
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break;
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}
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break;
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case 3: // MMU status
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uint32_t temp = READ_EA_32(ea);
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logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m_pc);
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break;
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}
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}
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void m68851_pmove(uint32_t ea, uint16_t modes)
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{
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switch ((modes>>13) & 0x7)
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{
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case 0: // MC68030/040 form with FD bit
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case 2: // MC68851 form, FD never set
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if (modes & 0x200)
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{
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m68851_pmove_get(ea, modes);
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break;
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}
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else // top 3 bits of modes: 010 for this, 011 for status, 000 for transparent translation regs
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{
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m68851_pmove_put(ea, modes);
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break;
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}
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case 3: // MC68030 to/from status reg
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if (modes & 0x200)
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{
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WRITE_EA_16(ea, m_mmu_sr);
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}
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else
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{
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m_mmu_sr = READ_EA_16(ea);
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}
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break;
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default:
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logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, m_pc);
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break;
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}
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}
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void m68851_mmu_ops()
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{
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uint16_t modes;
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uint32_t ea = m_ir & 0x3f;
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uint64_t temp64;
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// catch the 2 "weird" encodings up front (PBcc)
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@ -723,25 +971,7 @@ void m68881_mmu_ops()
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if ((modes & 0xfde0) == 0x2000) // PLOAD
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{
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uint32_t ltmp = DECODE_EA_32(ea);
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uint32_t ptmp;
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ptmp = ltmp;
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if (m_pmmu_enabled)
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{
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if (CPU_TYPE_IS_040_PLUS())
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{
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ptmp = pmmu_translate_addr_with_fc_040(ltmp, modes & 0x07, 0);
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}
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else
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{
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ptmp = pmmu_translate_addr_with_fc(ltmp, modes & 0x07, 0);
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}
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}
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MMULOG("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp);
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// FIXME: rw bit?
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pmmu_atc_add(ltmp, ptmp, modes & 0x07);
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m68851_pload(ea, modes);
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return;
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}
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else if ((modes & 0xe200) == 0x2000) // PFLUSH
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@ -766,219 +996,12 @@ void m68881_mmu_ops()
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}
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else if ((modes & 0xe000) == 0x8000) // PTEST
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{
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uint32_t v_addr = DECODE_EA_32(ea);
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uint32_t p_addr;
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uint32_t fc = modes & 0x1f;
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switch (fc >> 3) {
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case 0:
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fc = fc == 0 ? m_sfc : m_dfc;
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break;
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case 1:
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fc = REG_D()[fc &7] &7;
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break;
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case 2:
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fc &=7;
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break;
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}
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if (CPU_TYPE_IS_040_PLUS())
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{
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p_addr = pmmu_translate_addr_with_fc_040(v_addr, fc, 1);
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}
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else
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{
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p_addr = pmmu_translate_addr_with_fc(v_addr, fc, 1);
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}
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m_mmu_sr = m_mmu_tmp_sr;
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MMULOG("PMMU: pc=%08x sp=%08x va=%08x pa=%08x PTEST fc=%x level=%x mmu_sr=%04x\n",
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m_ppc, REG_A()[7], v_addr, p_addr, fc, (modes >> 10) & 0x07, m_mmu_sr);
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if (modes & 0x100)
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{
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int areg = (modes >> 5) & 7;
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WRITE_EA_32(0x08 | areg, p_addr);
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}
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m68851_ptest(ea, modes);
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return;
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}
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else
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{
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switch ((modes>>13) & 0x7)
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{
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case 0: // MC68030/040 form with FD bit
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case 2: // MC68881 form, FD never set
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if (modes & 0x200)
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{
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switch ((modes>>10) & 0x3f)
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{
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case 0x02: // transparent translation register 0
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WRITE_EA_32(ea, m_mmu_tt0);
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MMULOG("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m_ppc, m_mmu_tt0);
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break;
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case 0x03: // transparent translation register 1
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WRITE_EA_32(ea, m_mmu_tt1);
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MMULOG("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m_ppc, m_mmu_tt1);
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break;
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case 0x10: // translation control register
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WRITE_EA_32(ea, m_mmu_tc);
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MMULOG("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m_ppc, m_mmu_tc);
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break;
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case 0x12: // supervisor root pointer
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WRITE_EA_64(ea, (uint64_t)m_mmu_srp_limit<<32 | (uint64_t)m_mmu_srp_aptr);
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MMULOG("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", m_ppc, m_mmu_srp_limit, m_mmu_srp_aptr);
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break;
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case 0x13: // CPU root pointer
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WRITE_EA_64(ea, (uint64_t)m_mmu_crp_limit<<32 | (uint64_t)m_mmu_crp_aptr);
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MMULOG("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", m_ppc, m_mmu_crp_limit, m_mmu_crp_aptr);
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break;
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default:
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logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m_pc);
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break;
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}
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}
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else // top 3 bits of modes: 010 for this, 011 for status, 000 for transparent translation regs
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{
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switch ((modes>>13) & 7)
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{
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case 0:
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{
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uint32_t temp = READ_EA_32(ea);
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if (((modes>>10) & 7) == 2)
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{
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m_mmu_tt0 = temp;
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}
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else if (((modes>>10) & 7) == 3)
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{
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m_mmu_tt1 = temp;
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}
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}
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break;
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case 1:
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logerror("680x0: unknown PMOVE case 1, PC %x\n", m_pc);
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break;
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case 2:
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switch ((modes>>10) & 7)
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{
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case 0: // translation control register
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m_mmu_tc = READ_EA_32(ea);
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MMULOG("PMMU: TC = %08x\n", m_mmu_tc);
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if (m_mmu_tc & 0x80000000)
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{
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int bits = 0;
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for(int shift = 20; shift >= 0; shift -= 4) {
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bits += (m_mmu_tc >> shift) & 0x0f;
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}
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if (bits != 32 || !((m_mmu_tc >> 23) & 1)) {
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logerror("MMU: TC invalid!\n");
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m_mmu_tc &= ~0x80000000;
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m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
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} else {
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m_pmmu_enabled = 1;
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}
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MMULOG("PMMU enabled\n");
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}
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else
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{
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m_pmmu_enabled = 0;
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MMULOG("PMMU disabled\n");
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}
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if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP with FD bit clear
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{
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pmmu_atc_flush();
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}
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break;
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case 2: // supervisor root pointer
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temp64 = READ_EA_64(ea);
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m_mmu_srp_limit = (temp64>>32) & 0xffffffff;
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m_mmu_srp_aptr = temp64 & 0xffffffff;
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MMULOG("PMMU: SRP limit = %08x aptr = %08x\n", m_mmu_srp_limit, m_mmu_srp_aptr);
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// SRP type 0 is not allowed
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if ((m_mmu_srp_limit & 3) == 0) {
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m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
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return;
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}
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if (!(modes & 0x100))
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{
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pmmu_atc_flush();
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}
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break;
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|
||||
case 3: // CPU root pointer
|
||||
temp64 = READ_EA_64(ea);
|
||||
m_mmu_crp_limit = (temp64>>32) & 0xffffffff;
|
||||
m_mmu_crp_aptr = temp64 & 0xffffffff;
|
||||
MMULOG("PMMU: CRP limit = %08x aptr = %08x\n", m_mmu_crp_limit, m_mmu_crp_aptr);
|
||||
// CRP type 0 is not allowed
|
||||
if ((m_mmu_crp_limit & 3) == 0) {
|
||||
m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (!(modes & 0x100))
|
||||
{
|
||||
pmmu_atc_flush();
|
||||
}
|
||||
break;
|
||||
|
||||
case 7: // MC68851 Access Control Register
|
||||
if (m_cpu_type == CPU_TYPE_020)
|
||||
{
|
||||
// DomainOS on Apollo DN3000 will only reset this to 0
|
||||
uint16_t mmu_ac = READ_EA_16(ea);
|
||||
if (mmu_ac != 0)
|
||||
{
|
||||
MMULOG("680x0 PMMU: pc=%x PMOVE to mmu_ac=%08x\n",
|
||||
m_ppc, mmu_ac);
|
||||
}
|
||||
break;
|
||||
}
|
||||
// fall through; unknown PMOVE mode unless MC68020 with MC68851
|
||||
|
||||
default:
|
||||
logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m_pc);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 3: // MMU status
|
||||
{
|
||||
uint32_t temp = READ_EA_32(ea);
|
||||
logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m_pc);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case 3: // MC68030 to/from status reg
|
||||
if (modes & 0x200)
|
||||
{
|
||||
WRITE_EA_16(ea, m_mmu_sr);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_mmu_sr = READ_EA_16(ea);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, m_pc);
|
||||
break;
|
||||
|
||||
}
|
||||
m68851_pmove(ea, modes);
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user