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m68kmmu: split m68881_ops() into subfunctions (#4185)

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dxl 2018-10-23 20:43:39 +02:00 committed by R. Belmont
parent 769e13f265
commit 3c36b423ea
2 changed files with 254 additions and 231 deletions
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2
src/devices/cpu/m68000/m68k_in.cpp
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@ -8258,7 +8258,7 @@ M68KMAKE_OP(pmmu, 32, ., .)
{ {
if ((CPU_TYPE_IS_EC020_PLUS()) && (m_has_pmmu)) if ((CPU_TYPE_IS_EC020_PLUS()) && (m_has_pmmu))
{ {
m68881_mmu_ops(); m68851_mmu_ops();
} }
else else
{ {

173
src/devices/cpu/m68000/m68kmmu.h
View File

@ -691,38 +691,8 @@ uint32_t pmmu_translate_addr(uint32_t addr_in)
m68851_mmu_ops: COP 0 MMU opcode handling m68851_mmu_ops: COP 0 MMU opcode handling
*/ */
void m68881_mmu_ops() void m68851_pload(const uint32_t ea, const uint16_t modes)
{ {
uint16_t modes;
uint32_t ea = m_ir & 0x3f;
uint64_t temp64;
// catch the 2 "weird" encodings up front (PBcc)
if ((m_ir & 0xffc0) == 0xf0c0)
{
logerror("680x0: unhandled PBcc\n");
return;
}
else if ((m_ir & 0xffc0) == 0xf080)
{
logerror("680x0: unhandled PBcc\n");
return;
}
else if ((m_ir & 0xffe0) == 0xf500)
{
MMULOG("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", m_ppc, m_ir, (m_ir >> 3) & 3, m_ir & 7);
pmmu_atc_flush();
}
else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
{
switch ((m_ir>>9) & 0x7)
{
case 0:
modes = OPER_I_16();
if ((modes & 0xfde0) == 0x2000) // PLOAD
{
uint32_t ltmp = DECODE_EA_32(ea); uint32_t ltmp = DECODE_EA_32(ea);
uint32_t ptmp; uint32_t ptmp;
@ -742,30 +712,10 @@ void m68881_mmu_ops()
MMULOG("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp); MMULOG("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp);
// FIXME: rw bit? // FIXME: rw bit?
pmmu_atc_add(ltmp, ptmp, modes & 0x07); pmmu_atc_add(ltmp, ptmp, modes & 0x07);
return; }
}
else if ((modes & 0xe200) == 0x2000) // PFLUSH void m68851_ptest(const uint32_t ea, const uint16_t modes)
{ {
pmmu_atc_flush();
return;
}
else if (modes == 0xa000) // PFLUSHR
{
pmmu_atc_flush();
return;
}
else if (modes == 0x2800) // PVALID (FORMAT 1)
{
logerror("680x0: unhandled PVALID1\n");
return;
}
else if ((modes & 0xfff8) == 0x2c00) // PVALID (FORMAT 2)
{
logerror("680x0: unhandled PVALID2\n");
return;
}
else if ((modes & 0xe000) == 0x8000) // PTEST
{
uint32_t v_addr = DECODE_EA_32(ea); uint32_t v_addr = DECODE_EA_32(ea);
uint32_t p_addr; uint32_t p_addr;
uint32_t fc = modes & 0x1f; uint32_t fc = modes & 0x1f;
@ -799,16 +749,10 @@ void m68881_mmu_ops()
int areg = (modes >> 5) & 7; int areg = (modes >> 5) & 7;
WRITE_EA_32(0x08 | areg, p_addr); WRITE_EA_32(0x08 | areg, p_addr);
} }
return; }
}
else void m68851_pmove_get(uint32_t ea, uint16_t modes)
{ {
switch ((modes>>13) & 0x7)
{
case 0: // MC68030/040 form with FD bit
case 2: // MC68881 form, FD never set
if (modes & 0x200)
{
switch ((modes>>10) & 0x3f) switch ((modes>>10) & 0x3f)
{ {
case 0x02: // transparent translation register 0 case 0x02: // transparent translation register 0
@ -838,10 +782,11 @@ void m68881_mmu_ops()
logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m_pc); logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m_pc);
break; break;
} }
}
} void m68851_pmove_put(uint32_t ea, uint16_t modes)
else // top 3 bits of modes: 010 for this, 011 for status, 000 for transparent translation regs {
{ uint64_t temp64;
switch ((modes>>13) & 7) switch ((modes>>13) & 7)
{ {
case 0: case 0:
@ -850,15 +795,16 @@ void m68881_mmu_ops()
if (((modes>>10) & 7) == 2) if (((modes>>10) & 7) == 2)
{ {
MMULOG("WRITE TT0 = 0x%08x\n", m_mmu_tt0);
m_mmu_tt0 = temp; m_mmu_tt0 = temp;
} }
else if (((modes>>10) & 7) == 3) else if (((modes>>10) & 7) == 3)
{ {
MMULOG("WRITE TT1 = 0x%08x\n", m_mmu_tt1);
m_mmu_tt1 = temp; m_mmu_tt1 = temp;
} }
}
break; break;
}
case 1: case 1:
logerror("680x0: unknown PMOVE case 1, PC %x\n", m_pc); logerror("680x0: unknown PMOVE case 1, PC %x\n", m_pc);
break; break;
@ -952,17 +898,30 @@ void m68881_mmu_ops()
break; break;
} }
break; break;
case 3: // MMU status case 3: // MMU status
{
uint32_t temp = READ_EA_32(ea); uint32_t temp = READ_EA_32(ea);
logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m_pc); logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m_pc);
}
break; break;
} }
} }
break;
void m68851_pmove(uint32_t ea, uint16_t modes)
{
switch ((modes>>13) & 0x7)
{
case 0: // MC68030/040 form with FD bit
case 2: // MC68851 form, FD never set
if (modes & 0x200)
{
m68851_pmove_get(ea, modes);
break;
}
else // top 3 bits of modes: 010 for this, 011 for status, 000 for transparent translation regs
{
m68851_pmove_put(ea, modes);
break;
}
case 3: // MC68030 to/from status reg case 3: // MC68030 to/from status reg
if (modes & 0x200) if (modes & 0x200)
{ {
@ -979,6 +938,70 @@ void m68881_mmu_ops()
break; break;
} }
}
void m68851_mmu_ops()
{
uint16_t modes;
uint32_t ea = m_ir & 0x3f;
// catch the 2 "weird" encodings up front (PBcc)
if ((m_ir & 0xffc0) == 0xf0c0)
{
logerror("680x0: unhandled PBcc\n");
return;
}
else if ((m_ir & 0xffc0) == 0xf080)
{
logerror("680x0: unhandled PBcc\n");
return;
}
else if ((m_ir & 0xffe0) == 0xf500)
{
MMULOG("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", m_ppc, m_ir, (m_ir >> 3) & 3, m_ir & 7);
pmmu_atc_flush();
}
else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
{
switch ((m_ir>>9) & 0x7)
{
case 0:
modes = OPER_I_16();
if ((modes & 0xfde0) == 0x2000) // PLOAD
{
m68851_pload(ea, modes);
return;
}
else if ((modes & 0xe200) == 0x2000) // PFLUSH
{
pmmu_atc_flush();
return;
}
else if (modes == 0xa000) // PFLUSHR
{
pmmu_atc_flush();
return;
}
else if (modes == 0x2800) // PVALID (FORMAT 1)
{
logerror("680x0: unhandled PVALID1\n");
return;
}
else if ((modes & 0xfff8) == 0x2c00) // PVALID (FORMAT 2)
{
logerror("680x0: unhandled PVALID2\n");
return;
}
else if ((modes & 0xe000) == 0x8000) // PTEST
{
m68851_ptest(ea, modes);
return;
}
else
{
m68851_pmove(ea, modes);
} }
break; break;