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https://github.com/holub/mame
synced 2025-04-25 09:50:04 +03:00
misc stuff..
looks like MegaPhoenix needs better handling of some flags rather than rand(), overclocking the 68k by stupid amounts allows all the graphics to copy, needs more investigation. I have however hooked up the rest of the player controls based on test mode.. It looks like the other port is multiplexed somehow, or is some kind of serial port. still don't really know where most of roms6/7 map, even after playing through a few rounds..
This commit is contained in:
David Haywood
parent
cb3b1aae36
commit
3c4b75fd97
@ -1,9 +1,28 @@
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/* Megaphoenix
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trivia: Test mode graphics are the same as Little Robin(?!)
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*/
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/*
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need to work out what rand() bits are
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- game is very timing sensitive, to get all the gfx to copy i'm having to OC the 68k x 16 and it still glitches (phoenix ship is broken, round 4 gfx don't copy properly)
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probably due to above or irq handling
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- where should roms 6/7 map, they contain the 68k vectors, but the game expects RAM at 0, and it doesn't seem to read any of the other data from those roms.. they contain
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a cross hatch pattern amongst other things?
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'SYS' port - is it a serial port from an IO / protection chip? one bit has multiple meanings.
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- sound..
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/
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--
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Chips of note
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Main board:
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@ -96,20 +115,21 @@ WRITE16_MEMBER(megaphx_state::tms_host_w)
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static ADDRESS_MAP_START( megaphx_68k_map, AS_PROGRAM, 16, megaphx_state )
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// AM_RANGE(0x000000, 0x0000ff) AM_ROM
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AM_RANGE(0x000000, 0x00ffff) AM_RAM AM_SHARE("mainram") // we copy the vectors from roms 6+7 to ram here, but where do the rest of those roms map?
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AM_RANGE(0x000000, 0x0013ff) AM_RAM AM_SHARE("mainram") // maps over part of the rom??
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AM_RANGE(0x000000, 0x03ffff) AM_ROM AM_REGION("roms67", 0x00000) // or the rom doesn't map here? it contains the service mode grid amongst other things..
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AM_RANGE(0x040000, 0x040007) AM_READWRITE(tms_host_r, tms_host_w)
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AM_RANGE(0x050000, 0x050001) AM_WRITENOP
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AM_RANGE(0x050002, 0x050003) AM_READ_PORT("P3")
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AM_RANGE(0x050000, 0x050001) AM_WRITENOP // z80 comms?
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AM_RANGE(0x050002, 0x050003) AM_READ_PORT("P3") // z80 comms?
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AM_RANGE(0x060000, 0x060007) AM_DEVREADWRITE8("ppi8255_0", i8255_device, read, write, 0x00ff)
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AM_RANGE(0x800000, 0x83ffff) AM_ROM AM_REGION("roms01", 0x00000)
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AM_RANGE(0x840000, 0x87ffff) AM_ROM AM_REGION("roms23", 0x00000)
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AM_RANGE(0x880000, 0x8bffff) AM_ROM AM_REGION("roms45", 0x00000)
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AM_RANGE(0x800000, 0x83ffff) AM_ROM AM_REGION("roms01", 0x00000) // code + bg gfx are in here
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AM_RANGE(0x840000, 0x87ffff) AM_ROM AM_REGION("roms23", 0x00000) // bg gfx are in here
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AM_RANGE(0x880000, 0x8bffff) AM_ROM AM_REGION("roms45", 0x00000) // bg gfx + title screen in here
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ADDRESS_MAP_END
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@ -138,6 +158,7 @@ ADDRESS_MAP_END
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static ADDRESS_MAP_START( sound_io, AS_IO, 8, megaphx_state )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x00, 0x07) AM_RAM
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AM_RANGE(0x20, 0x23) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
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AM_RANGE(0x31, 0x31) AM_READNOP
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ADDRESS_MAP_END
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@ -204,48 +225,32 @@ static const tms34010_config tms_config_megaphx =
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static INPUT_PORTS_START( megaphx )
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PORT_START("P0")
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PORT_DIPNAME( 0x0001, 0x0001, "0" )
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_START("P0") // verified in test mode
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) // shield
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) // unused ? (in test mode)
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PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1) // test mode
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PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1) // test mode
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
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PORT_START("P1")
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PORT_DIPNAME( 0x0001, 0x0001, "2" )
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_START("P1") // verified in test mode
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) // shield
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) // unused ? (in test mode)
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PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) // test mode
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PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) // test mode
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
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PORT_START("P2")
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PORT_START("SYS") // some kind of serial port, or multiplexed port?
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PORT_DIPNAME( 0x0001, 0x0001, "4" )
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0002, 0x0000, DEF_STR( Unknown ) ) // must be 'on' to boot, but is also p2 start? multiplexed?
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PORT_DIPNAME( 0x0002, 0x0000, DEF_STR( Unknown ) ) // must be 'on' to boot, but is also p1 and p2 start in test mode? multiplexed?
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PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
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@ -265,7 +270,7 @@ static INPUT_PORTS_START( megaphx )
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PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_START("P3")
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PORT_START("P3") // not dips according to service mode.. maybe comms with Z80?
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PORT_DIPNAME( 0x0001, 0x0001,"X")
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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@ -330,7 +335,7 @@ static I8255A_INTERFACE( ppi8255_intf_0 )
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DEVCB_NULL, /* Port A write */
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DEVCB_INPUT_PORT("P1"), /* Port B read */
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DEVCB_NULL, /* Port B write */
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DEVCB_INPUT_PORT("P2"), /* Port C read */
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DEVCB_INPUT_PORT("SYS"), /* Port C read */
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DEVCB_NULL /* Port C write */
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};
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@ -359,11 +364,19 @@ static Z80CTC_INTERFACE( z80ctc_intf )
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DEVCB_DEVICE_LINE_MEMBER("ctc", megaphx_state, z80ctc_to2) // ZC/TO2 callback
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};
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// just for debug.. so we can see what is in each of the roms
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static GFXLAYOUT_RAW( megaphxlay, 336, 1, 336*8, 336*8 )
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static GFXDECODE_START( megaphx )
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GFXDECODE_ENTRY( "roms01", 0, megaphxlay, 0x0000, 1 )
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GFXDECODE_ENTRY( "roms23", 0, megaphxlay, 0x0000, 1 )
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GFXDECODE_ENTRY( "roms45", 0, megaphxlay, 0x0000, 1 )
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GFXDECODE_ENTRY( "roms67", 0, megaphxlay, 0x0000, 1 )
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GFXDECODE_END
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static MACHINE_CONFIG_START( megaphx, megaphx_state )
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MCFG_CPU_ADD("maincpu", M68000, 8000000) // ?? can't read xtal due to reflections, CPU is an 8Mhz part
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MCFG_CPU_ADD("maincpu", M68000, 8000000*16) // ?? can't read xtal due to reflections, CPU is an 8Mhz part // CLEARLY the 'rand' flags have more meaning (but don't seem to be vblank) I shouldn't have to do a *16 on the 68k clock just to get all the gfx!
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MCFG_CPU_PROGRAM_MAP(megaphx_68k_map)
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// MCFG_CPU_VBLANK_INT_DRIVER("screen", megaphx_state, irq6_line_hold)
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@ -384,10 +397,12 @@ static MACHINE_CONFIG_START( megaphx, megaphx_state )
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// MCFG_NVRAM_ADD_0FILL("nvram")
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_RAW_PARAMS(XTAL_40MHz/12, 424, 0, 320, 262, 0, 240)
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MCFG_SCREEN_RAW_PARAMS(XTAL_40MHz/12, 424, 0, 338-1, 262, 0, 246-1)
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MCFG_SCREEN_UPDATE_DEVICE("tms", tms34010_device, tms340x0_rgb32)
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MCFG_PALETTE_LENGTH(256)
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MCFG_GFXDECODE_ADD("gfxdecode", megaphx)
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MCFG_RAMDAC_ADD("ramdac", ramdac_intf, ramdac_map)
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@ -396,8 +411,8 @@ MACHINE_CONFIG_END
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DRIVER_INIT_MEMBER(megaphx_state,megaphx)
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{
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UINT16 *src = (UINT16*)memregion( "roms67" )->base();
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// copy vector table?
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memcpy(m_mainram, src, 0x10000);
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// copy vector table? - it must be writable because the game write the irq vector..
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memcpy(m_mainram, src, 0x80);
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}
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