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fix comments to have actually CORRECT resolution calculations listed. oops.
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@ -113,9 +113,23 @@ Someone on the MW forums has this iirc, but it isn't dumped yet - LN
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**** Notes from schematics (applies to all drivers):
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**** Notes from schematics (applies to all drivers):
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Framebuffer is six tms4416 16384*4 chips; chips are arranged as three
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Framebuffer is six tms4416 16384*4 chips; chips are arranged as three
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planes of 16384*8 pixels per plane, one plane per color channel.
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planes of 16384*8 bits per plane, one plane per color channel.
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Screen resolution is 54x256, if I(LN) am properly understanding the
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Screen resolution is probably either 212x256 (two bits per plane, per
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schematics on page 6.
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pixel) or 424x256 (one bit per plane per pixel), depending on the pals
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installed. See schematics on page 6. The counters at U137 and U139
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compare against binary 0b110101 (53) in comparitor at U138, and as soon
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as it hits that, HDONE is pulled high on the next MCLR clock.
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This means there will be 53 (0-52) counts in the X counter before HDONE;
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as each count refers to one 8 bit address, and the addressed 4416 rams
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have between all of them 24 bits of output (8 per plane), the minimum
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horizontal displayed resolution is 53x256 (8 bits per color per pixel),
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and maximum is 8 times that. With proper pals (and proper mixing
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resistors or other PWM fun) it should be possible to get:
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53x256 8,8,8 RGB
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106x256 4,4,4 RGB
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212x256 2,2,2 RGB <- this seems the most likely to me (LN)
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424x256 1,1,1 RGB
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* The socket at U50 and the 3 pin connector J3 is for an
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* The socket at U50 and the 3 pin connector J3 is for an
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undumped intel 8050 MCU used for rs232 serial communication,
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undumped intel 8050 MCU used for rs232 serial communication,
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