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Add internal clock divider for Z180 family and adjust CPU clocks in many drivers to compensate

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This commit is contained in:
AJR 2019-10-02 18:44:41 -04:00
parent 72f1be6bca
commit 3ce8352f78
21 changed files with 41 additions and 36 deletions
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16
src/devices/cpu/z180/z180.cpp
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@ -21,14 +21,18 @@
Z180 Info:
Known clock speeds (from ZiLOG): 6, 8, 10, 20 & 33MHz
Known clock speeds (from ZiLOG): 6 (actually ~6.15), 8, 10, 20 & 33MHz
Much like the 80186/188, the operating frequency is generated from the
XTAL/EXTAL clock by an internal divide-by-2 circuit. The maximum frequency of
the XTAL input is therefore twice the speed rating for the specific part.
ZiLOG Z180 codes:
Speed: 10 = 10MHZ
20 = 20MHz
33 = 33MHz
Package: P = 60-Pin Plastic DIP
Package: P = 64-Pin Plastic SDIP
V = 68-Pin PLCC
F = 80-Pin QFP
Temp: S = 0C to +70C
@ -78,10 +82,10 @@ Hitachi HD647180 series:
/* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128) */
/****************************************************************************/
DEFINE_DEVICE_TYPE(Z80180, z80180_device, "z80180", "Zilog Z80180") // equivalent to Hitachi HD64180
DEFINE_DEVICE_TYPE(HD64180RP, hd64180rp_device, "hd64180rp", "Hitachi HD64180RP") // DIP version identical to Zilog Z80180xxPSC
DEFINE_DEVICE_TYPE(Z8S180, z8s180_device, "z8s180", "Zilog Z8S180")
DEFINE_DEVICE_TYPE(Z80182, z80182_device, "z80182", "Zilog Z80182")
DEFINE_DEVICE_TYPE(Z80180, z80180_device, "z80180", "Zilog Z80180") // equivalent to Hitachi HD64180R or HD64180Z
DEFINE_DEVICE_TYPE(HD64180RP, hd64180rp_device, "hd64180rp", "Hitachi HD64180RP") // DIP64 version, identical to Zilog Z80180xxPSC
DEFINE_DEVICE_TYPE(Z8S180, z8s180_device, "z8s180", "Zilog Z8S180") // enhanced Z80180
DEFINE_DEVICE_TYPE(Z80182, z80182_device, "z80182", "Zilog Z80182") // further enhanced Z8S180
z180_device::z180_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool extended_io, address_map_constructor internal_map)

2
src/devices/cpu/z180/z180.h
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@ -119,6 +119,8 @@ protected:
// device_execute_interface overrides
virtual uint32_t execute_min_cycles() const override { return 1; }
virtual uint32_t execute_max_cycles() const override { return 16; }
virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const override { return (clocks + 2 - 1) / 2; }
virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const override { return (cycles * 2); }
virtual uint32_t execute_input_lines() const override { return 5; }
virtual uint32_t execute_default_irq_vector(int inputnum) const override { return 0xff; }
virtual bool execute_input_edge_triggered(int inputnum) const override { return inputnum == INPUT_LINE_NMI; }

2
src/mame/drivers/20pacgal.cpp
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@ -102,7 +102,7 @@ Graphics: CY37256P160-83AC x 2 (Ultra37000 CPLD family - 160 pin TQFP, 256 Macro
*************************************/
#define MASTER_CLOCK (XTAL(73'728'000))
#define MAIN_CPU_CLOCK (MASTER_CLOCK / 4) /* divider is either 3 or 4 */
#define MAIN_CPU_CLOCK (MASTER_CLOCK / 2)
#define NAMCO_AUDIO_CLOCK (MASTER_CLOCK / 4 / 6 / 32)

2
src/mame/drivers/atronic.cpp
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@ -466,7 +466,7 @@ void atronic_state::ramdac_map(address_map &map)
void atronic_state::atronic(machine_config &config)
{
/* basic machine hardware */
Z80180(config, m_maincpu, 6000000);
Z80180(config, m_maincpu, 18.432_MHz_XTAL);
m_maincpu->set_addrmap(AS_PROGRAM, &atronic_state::atronic_map);
m_maincpu->set_addrmap(AS_IO, &atronic_state::atronic_portmap);
m_maincpu->set_vblank_int("screen", FUNC(atronic_state::irq0_line_hold));

2
src/mame/drivers/cabaret.cpp
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@ -369,7 +369,7 @@ INTERRUPT_GEN_MEMBER(cabaret_state::cabaret_interrupt)
void cabaret_state::cabaret(machine_config &config)
{
/* basic machine hardware */
Z80180(config, m_maincpu, XTAL(12'000'000) / 2);
Z80180(config, m_maincpu, XTAL(12'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &cabaret_state::cabaret_map);
m_maincpu->set_addrmap(AS_IO, &cabaret_state::cabaret_portmap);
m_maincpu->set_vblank_int("screen", FUNC(cabaret_state::cabaret_interrupt));

6
src/mame/drivers/chsuper.cpp
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@ -367,7 +367,7 @@ void chsuper_state::ramdac_map(address_map &map)
void chsuper_state::chsuper(machine_config &config)
{
/* basic machine hardware */
Z80180(config, m_maincpu, XTAL(12'000'000) / 4); /* HD64180RP8, 8 MHz? */
Z80180(config, m_maincpu, 16_MHz_XTAL); // Z8018006VSC (but can actually take 8 MHz?)
m_maincpu->set_addrmap(AS_PROGRAM, &chsuper_state::chsuper_prg_map);
m_maincpu->set_addrmap(AS_IO, &chsuper_state::chsuper_portmap);
m_maincpu->set_vblank_int("screen", FUNC(chsuper_state::irq0_line_hold));
@ -386,13 +386,13 @@ void chsuper_state::chsuper(machine_config &config)
GFXDECODE(config, m_gfxdecode, m_palette, gfx_chsuper);
PALETTE(config, m_palette).set_entries(0x100);
ramdac_device &ramdac(RAMDAC(config, "ramdac", 0, m_palette));
ramdac_device &ramdac(RAMDAC(config, "ramdac", 0, m_palette)); // ADV476KP50
ramdac.set_addrmap(0, &chsuper_state::ramdac_map);
/* sound hardware */
SPEAKER(config, "speaker").front_center();
DAC_8BIT_R2R(config, "dac", 0).add_route(ALL_OUTPUTS, "speaker", 0.25); // unknown DAC
DAC_8BIT_R2R(config, "dac", 0).add_route(ALL_OUTPUTS, "speaker", 0.25); // 74HC273 latch + R2R network (unknown values)
voltage_regulator_device &vref(VOLTAGE_REGULATOR(config, "vref"));
vref.add_route(0, "dac", 1.0, DAC_VREF_POS_INPUT);
vref.add_route(0, "dac", -1.0, DAC_VREF_NEG_INPUT);

2
src/mame/drivers/hawk.cpp
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@ -103,7 +103,7 @@ void hawk_state::hawk_palette(palette_device &palette) const
void hawk_state::hawk(machine_config &config)
{
/* basic machine hardware */
Z80180(config, m_maincpu, 12.288_MHz_XTAL / 2); /* HD64B180R0F */
Z80180(config, m_maincpu, 12.288_MHz_XTAL); /* HD64B180R0F */
m_maincpu->set_addrmap(AS_PROGRAM, &hawk_state::hawk_mem);
m_maincpu->set_addrmap(AS_IO, &hawk_state::hawk_io);

2
src/mame/drivers/igs009.cpp
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@ -832,7 +832,7 @@ WRITE_LINE_MEMBER(igs009_state::vblank_irq)
void igs009_state::jingbell(machine_config &config)
{
/* basic machine hardware */
HD64180RP(config, m_maincpu, XTAL(12'000'000) / 2); /* HD64180RP8, 8 MHz? */
HD64180RP(config, m_maincpu, XTAL(12'000'000)); /* HD64180RP8, 8 MHz? */
m_maincpu->set_addrmap(AS_PROGRAM, &igs009_state::jingbell_map);
m_maincpu->set_addrmap(AS_IO, &igs009_state::jingbell_portmap);

6
src/mame/drivers/igs017.cpp
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@ -3497,7 +3497,7 @@ MACHINE_RESET_MEMBER(igs017_state,iqblocka)
void igs017_state::iqblocka(machine_config &config)
{
HD64180RP(config, m_maincpu, XTAL(16'000'000) / 2);
HD64180RP(config, m_maincpu, XTAL(16'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &igs017_state::iqblocka_map);
m_maincpu->set_addrmap(AS_IO, &igs017_state::iqblocka_io);
TIMER(config, "scantimer").configure_scanline(FUNC(igs017_state::iqblocka_interrupt), "screen", 0, 1);
@ -3836,7 +3836,7 @@ void igs017_state::mgdha(machine_config &config)
void igs017_state::tjsb(machine_config &config)
{
HD64180RP(config, m_maincpu, XTAL(16'000'000) / 2);
HD64180RP(config, m_maincpu, XTAL(16'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &igs017_state::tjsb_map);
m_maincpu->set_addrmap(AS_IO, &igs017_state::tjsb_io);
TIMER(config, "scantimer").configure_scanline(FUNC(igs017_state::iqblocka_interrupt), "screen", 0, 1);
@ -3874,7 +3874,7 @@ void igs017_state::tjsb(machine_config &config)
void igs017_state::spkrform(machine_config &config)
{
HD64180RP(config, m_maincpu, XTAL(16'000'000) / 2);
HD64180RP(config, m_maincpu, XTAL(16'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &igs017_state::spkrform_map);
m_maincpu->set_addrmap(AS_IO, &igs017_state::spkrform_io);
TIMER(config, "scantimer").configure_scanline(FUNC(igs017_state::iqblocka_interrupt), "screen", 0, 1);

1
src/mame/drivers/iqblock.cpp
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@ -53,7 +53,6 @@ Grndtour:
#include "includes/iqblock.h"
#include "cpu/z80/z80.h"
#include "cpu/z180/z180.h"
#include "machine/i8255.h"
#include "sound/ym2413.h"
#include "emupal.h"

4
src/mame/drivers/luckgrln.cpp
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@ -863,13 +863,13 @@ INTERRUPT_GEN_MEMBER(luckgrln_state::irq)
void luckgrln_state::luckgrln(machine_config &config)
{
HD647180X(config, m_maincpu, 8000000);
HD647180X(config, m_maincpu, 16000000);
m_maincpu->set_addrmap(AS_PROGRAM, &luckgrln_state::mainmap);
m_maincpu->set_addrmap(AS_IO, &luckgrln_state::luckgrln_io);
m_maincpu->set_vblank_int("screen", FUNC(luckgrln_state::irq));
m_maincpu->out_pa_callback().set(FUNC(luckgrln_state::output_w));
hd6845s_device &crtc(HD6845S(config, "crtc", 6000000/4)); /* HD6845SP; unknown clock, hand tuned to get ~60 fps */
hd6845s_device &crtc(HD6845S(config, "crtc", 12_MHz_XTAL / 8)); /* HD6845SP; unknown clock, hand tuned to get ~60 fps */
crtc.set_screen("screen");
crtc.set_show_border_area(false);
crtc.set_char_width(8);

2
src/mame/drivers/luckybal.cpp
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@ -568,7 +568,7 @@ INPUT_PORTS_END
void luckybal_state::luckybal(machine_config &config)
{
/* basic machine hardware */
Z80180(config, m_maincpu, CPU_CLOCK / 2);
Z80180(config, m_maincpu, CPU_CLOCK);
m_maincpu->set_addrmap(AS_PROGRAM, &luckybal_state::main_map);
m_maincpu->set_addrmap(AS_IO, &luckybal_state::main_io);

4
src/mame/drivers/mastboy.cpp
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@ -140,7 +140,7 @@
Timing
- HD647180 runs at 12.000 / 2 MHz
- HD647180 runs at 12.000 / 2 MHz (divider is internal)
- SAA1099 PSG runs at 6.000 MHz
- Display pixel clock is 6.000 MHz
- Oki MSM5205 has a 384 KHz oscillator, this is the standard setup
@ -805,7 +805,7 @@ void mastboy_state::machine_reset()
void mastboy_state::mastboy(machine_config &config)
{
HD647180X(config, m_maincpu, 12000000/2); /* HD647180X0CP6-1M1R */
HD647180X(config, m_maincpu, 24_MHz_XTAL / 2); /* HD647180X0CP6-1M1R */
m_maincpu->set_addrmap(AS_PROGRAM, &mastboy_state::mastboy_map);
m_maincpu->set_addrmap(AS_IO, &mastboy_state::mastboy_io_map);

2
src/mame/drivers/mosaic.cpp
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@ -287,7 +287,7 @@ void mosaic_state::machine_reset()
void mosaic_state::mosaic(machine_config &config)
{
/* basic machine hardware */
HD64180RP(config, m_maincpu, XTAL(12'288'000)/2); /* 6.144MHz - Verified */
HD64180RP(config, m_maincpu, XTAL(12'288'000)); /* 6.144MHz - Verified */
m_maincpu->set_addrmap(AS_PROGRAM, &mosaic_state::mosaic_map);
m_maincpu->set_addrmap(AS_IO, &mosaic_state::mosaic_io_map);
m_maincpu->set_vblank_int("screen", FUNC(mosaic_state::irq0_line_hold));

2
src/mame/drivers/prof180x.cpp
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@ -222,7 +222,7 @@ void prof180x_state::machine_reset()
void prof180x_state::prof180x(machine_config &config)
{
/* basic machine hardware */
z180_device &maincpu(HD64180RP(config, HD64180_TAG, 18.432_MHz_XTAL / 2));
z180_device &maincpu(HD64180RP(config, HD64180_TAG, 18.432_MHz_XTAL));
maincpu.set_addrmap(AS_PROGRAM, &prof180x_state::prof180x_mem);
maincpu.set_addrmap(AS_IO, &prof180x_state::prof180x_io);

2
src/mame/drivers/sfcbox.cpp
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@ -469,7 +469,7 @@ void sfcbox_state::sfcbox(machine_config &config)
config.m_perfect_cpu_quantum = subtag("maincpu");
/* sfcbox hardware */
Z80180(config, m_bios, XTAL(12'000'000) / 2); /* HD64180RF6X */
Z80180(config, m_bios, XTAL(12'000'000)); /* HD64180RF6X */
m_bios->set_addrmap(AS_PROGRAM, &sfcbox_state::sfcbox_map);
m_bios->set_addrmap(AS_IO, &sfcbox_state::sfcbox_io);

2
src/mame/drivers/spoker.cpp
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@ -612,7 +612,7 @@ void spoker_state::machine_reset()
void spoker_state::spoker(machine_config &config)
{
/* basic machine hardware */
HD64180RP(config, m_maincpu, XTAL(12'000'000) / 2); /* HD64180RP8, 8 MHz? */
HD64180RP(config, m_maincpu, XTAL(12'000'000)); /* HD64180RP8, 8 MHz? */
m_maincpu->set_addrmap(AS_PROGRAM, &spoker_state::spoker_map);
m_maincpu->set_addrmap(AS_IO, &spoker_state::spoker_portmap);
m_maincpu->set_vblank_int("screen", FUNC(spoker_state::nmi_line_assert));

10
src/mame/drivers/subsino.cpp
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@ -2690,7 +2690,7 @@ GFXDECODE_END
void subsino_state::victor21(machine_config &config)
{
/* basic machine hardware */
HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */
HD647180X(config, m_maincpu, XTAL(12'000'000)); /* Unknown clock */
m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::victor21_map);
m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap);
@ -2739,7 +2739,7 @@ void subsino_state::victor5(machine_config &config)
void subsino_state::crsbingo(machine_config &config)
{
/* basic machine hardware */
HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown CPU and clock */
HD647180X(config, m_maincpu, XTAL(12'000'000)); /* Unknown CPU and clock */
m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::crsbingo_map);
m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap);
@ -2770,7 +2770,7 @@ void subsino_state::crsbingo(machine_config &config)
void subsino_state::srider(machine_config &config)
{
/* basic machine hardware */
HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */
HD647180X(config, m_maincpu, XTAL(12'000'000)); /* Unknown clock */
m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::srider_map);
m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap);
@ -2821,7 +2821,7 @@ void subsino_state::sharkpy(machine_config &config)
void subsino_state::tisub(machine_config &config)
{
/* basic machine hardware */
HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown CPU and clock */
HD647180X(config, m_maincpu, XTAL(12'000'000)); /* Unknown CPU and clock */
m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::tisub_map);
m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap);
@ -2861,7 +2861,7 @@ void subsino_state::tisub(machine_config &config)
void subsino_state::stbsub(machine_config &config)
{
/* basic machine hardware */
HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */
HD647180X(config, m_maincpu, XTAL(12'000'000)); /* Unknown clock */
m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::stbsub_map);
m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap);

2
src/mame/drivers/subsino2.cpp
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@ -2928,7 +2928,7 @@ void subsino2_state::humlan(machine_config &config)
void subsino2_state::mtrain(machine_config &config)
{
Z80180(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */
Z80180(config, m_maincpu, XTAL(12'000'000)); /* Unknown clock */
m_maincpu->set_addrmap(AS_PROGRAM, &subsino2_state::mtrain_map);
m_maincpu->set_addrmap(AS_IO, &subsino2_state::mtrain_io);

2
src/mame/drivers/tim011.cpp
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@ -135,7 +135,7 @@ static const floppy_format_type tim011_floppy_formats[] = {
void tim011_state::tim011(machine_config &config)
{
/* basic machine hardware */
HD64180RP(config, m_maincpu, XTAL(12'288'000) / 2); // location U17 HD64180
HD64180RP(config, m_maincpu, XTAL(12'288'000)); // location U17 HD64180
m_maincpu->set_addrmap(AS_PROGRAM, &tim011_state::tim011_mem);
m_maincpu->set_addrmap(AS_IO, &tim011_state::tim011_io);
m_maincpu->set_vblank_int("screen", FUNC(tim011_state::irq0_line_hold));

4
src/mame/drivers/toaplan1.cpp
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@ -2103,7 +2103,7 @@ void toaplan1_samesame_state::samesame(machine_config &config)
M68000(config, m_maincpu, XTAL(10'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &toaplan1_samesame_state::main_map);
hd647180x_device &audiocpu(HD647180X(config, m_audiocpu, XTAL(28'000'000) / 8)); /* HD647180XOFS6 CPU */
hd647180x_device &audiocpu(HD647180X(config, m_audiocpu, XTAL(28'000'000) / 4)); /* HD647180XOFS6 CPU */
// 16k byte ROM and 512 byte RAM are internal
audiocpu.set_addrmap(AS_IO, &toaplan1_samesame_state::hd647180_io_map);
audiocpu.in_pd_callback().set(FUNC(toaplan1_samesame_state::cmdavailable_r));
@ -2200,7 +2200,7 @@ void toaplan1_state::vimana(machine_config &config)
M68000(config, m_maincpu, XTAL(10'000'000)); /* verified on pcb */
m_maincpu->set_addrmap(AS_PROGRAM, &toaplan1_state::vimana_main_map);
hd647180x_device &audiocpu(HD647180X(config, m_audiocpu, XTAL(28'000'000) / 8)); /* HD647180XOFS6 CPU */
hd647180x_device &audiocpu(HD647180X(config, m_audiocpu, XTAL(28'000'000) / 4)); /* HD647180XOFS6 CPU */
audiocpu.set_addrmap(AS_PROGRAM, &toaplan1_state::vimana_hd647180_mem_map);
audiocpu.set_addrmap(AS_IO, &toaplan1_state::vimana_hd647180_io_map);
audiocpu.in_pa_callback().set(FUNC(toaplan1_state::vimana_dswb_invert_r)); // note these inputs seem to be inverted, unlike the DSWA ones.