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https://github.com/holub/mame
synced 2025-06-06 21:03:47 +03:00
Separate TLCS-90 external IRQ line state from internal request register (fixes tenkai slowdowns)
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82985bbd9e
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@ -1268,9 +1268,20 @@ void tlcs90_device::leave_halt()
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}
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}
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}
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}
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void tlcs90_device::take_interrupt(tlcs90_e_irq irq)
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void tlcs90_device::raise_irq(int irq)
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{
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m_irq_state |= 1 << irq;
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}
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void tlcs90_device::clear_irq(int irq)
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{
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{
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m_irq_state &= ~(1 << irq);
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m_irq_state &= ~(1 << irq);
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}
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void tlcs90_device::take_interrupt(tlcs90_e_irq irq)
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{
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if (irq != INT0 || (m_p8cr & 1) == 1)
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clear_irq(irq);
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leave_halt();
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leave_halt();
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@ -1296,7 +1307,7 @@ void tlcs90_device::check_interrupts()
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{
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{
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mask = (1 << irq);
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mask = (1 << irq);
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if(irq >= INT0) mask &= m_irq_mask;
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if(irq >= INT0) mask &= m_irq_mask;
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if ( m_irq_state & mask )
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if (m_irq_state & mask)
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{
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{
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take_interrupt( irq );
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take_interrupt( irq );
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return;
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return;
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@ -1324,16 +1335,18 @@ void tlcs90_device::execute_set_input(int inputnum, int state)
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void tlcs90_device::set_irq_line(int irq, int state)
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void tlcs90_device::set_irq_line(int irq, int state)
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{
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{
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if ( ((m_irq_state >> irq)&1) == state ) return;
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if ( ((m_irq_line_state >> irq)&1) == state ) return;
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if (state)
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if (state)
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{
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{
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m_irq_state |= 1 << irq;
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raise_irq(irq);
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check_interrupts();
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m_irq_line_state |= 1 << irq;
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}
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}
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else
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else
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{
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{
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m_irq_state &= ~(1 << irq);
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if (irq == INT0 && (m_p8cr & 1) == 0)
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clear_irq(irq);
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m_irq_line_state &= ~(1 << irq);
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}
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}
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}
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}
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@ -2458,12 +2471,12 @@ TIMER_CALLBACK_MEMBER( tlcs90_device::t90_timer_callback )
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break;
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break;
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case 0x01: // 16bit, only can happen for i=0,2
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case 0x01: // 16bit, only can happen for i=0,2
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m_timer_value[i+1] = 0;
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m_timer_value[i+1] = 0;
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set_irq_line(INTT0 + i+1, 1);
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raise_irq(INTT0 + i+1);
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break;
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break;
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}
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}
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// regular handling
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// regular handling
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m_timer_value[i] = 0;
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m_timer_value[i] = 0;
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set_irq_line(INTT0 + i, 1);
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raise_irq(INTT0 + i);
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}
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}
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}
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}
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@ -2478,12 +2491,12 @@ TIMER_CALLBACK_MEMBER( tlcs90_device::t90_timer4_callback )
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if ( m_timer4_value == m_treg_16bit[0] )
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if ( m_timer4_value == m_treg_16bit[0] )
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{
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{
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// logerror("CPU Timer 4 matches TREG4\n");
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// logerror("CPU Timer 4 matches TREG4\n");
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set_irq_line(INTT4, 1);
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raise_irq(INTT4);
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}
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}
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if ( m_timer4_value == m_treg_16bit[1] )
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if ( m_timer4_value == m_treg_16bit[1] )
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{
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{
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// logerror("CPU Timer 4 matches TREG5\n");
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// logerror("CPU Timer 4 matches TREG5\n");
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set_irq_line(INTT5, 1);
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raise_irq(INTT5);
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if (m_t4mod & 0x04)
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if (m_t4mod & 0x04)
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m_timer4_value = 0;
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m_timer4_value = 0;
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}
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}
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@ -2606,7 +2619,7 @@ WRITE8_MEMBER( tlcs90_device::t90_internal_registers_w )
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case T90_IRFH:
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case T90_IRFH:
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if (data >= int(INTSWI) + 2 && data < int(INTMAX) + 2)
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if (data >= int(INTSWI) + 2 && data < int(INTMAX) + 2)
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m_irq_state &= ~(1 << (data - 2));
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clear_irq(data - 2);
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break;
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break;
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case T90_P3:
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case T90_P3:
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@ -2730,6 +2743,7 @@ void tlcs90_device::device_start()
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save_item(NAME(m_halt));
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save_item(NAME(m_halt));
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save_item(NAME(m_after_EI));
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save_item(NAME(m_after_EI));
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save_item(NAME(m_irq_state));
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save_item(NAME(m_irq_state));
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save_item(NAME(m_irq_line_state));
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save_item(NAME(m_irq_mask));
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save_item(NAME(m_irq_mask));
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save_item(NAME(m_extra_cycles));
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save_item(NAME(m_extra_cycles));
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@ -2790,7 +2804,7 @@ void tlcs90_device::device_start()
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m_prvpc.d = m_pc.d = m_sp.d = m_af.d = m_bc.d = m_de.d = m_hl.d = m_ix.d = m_iy.d = 0;
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m_prvpc.d = m_pc.d = m_sp.d = m_af.d = m_bc.d = m_de.d = m_hl.d = m_ix.d = m_iy.d = 0;
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m_af2.d = m_bc2.d = m_de2.d = m_hl2.d = 0;
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m_af2.d = m_bc2.d = m_de2.d = m_hl2.d = 0;
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m_halt = m_after_EI = 0;
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m_halt = m_after_EI = 0;
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m_irq_state = m_irq_mask = 0;
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m_irq_state = m_irq_line_state = m_irq_mask = 0;
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m_extra_cycles = 0;
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m_extra_cycles = 0;
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m_ixbase = m_iybase = 0;
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m_ixbase = m_iybase = 0;
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m_timer_value[0] = m_timer_value[1] = m_timer_value[2] = m_timer_value[3] = 0;
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m_timer_value[0] = m_timer_value[1] = m_timer_value[2] = m_timer_value[3] = 0;
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@ -143,7 +143,7 @@ private:
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PAIR m_prvpc,m_pc,m_sp,m_af,m_bc,m_de,m_hl,m_ix,m_iy;
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PAIR m_prvpc,m_pc,m_sp,m_af,m_bc,m_de,m_hl,m_ix,m_iy;
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PAIR m_af2,m_bc2,m_de2,m_hl2;
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PAIR m_af2,m_bc2,m_de2,m_hl2;
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uint8_t m_halt, m_after_EI;
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uint8_t m_halt, m_after_EI;
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uint16_t m_irq_state, m_irq_mask;
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uint16_t m_irq_state, m_irq_line_state, m_irq_mask;
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address_space *m_program;
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address_space *m_program;
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int m_icount;
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int m_icount;
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int m_extra_cycles; // extra cycles for interrupts
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int m_extra_cycles; // extra cycles for interrupts
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@ -209,6 +209,8 @@ private:
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inline void Push( uint16_t rr );
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inline void Push( uint16_t rr );
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inline void Pop( uint16_t rr );
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inline void Pop( uint16_t rr );
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inline void leave_halt();
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inline void leave_halt();
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inline void raise_irq(int irq);
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inline void clear_irq(int irq);
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void take_interrupt(tlcs90_e_irq irq);
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void take_interrupt(tlcs90_e_irq irq);
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void check_interrupts();
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void check_interrupts();
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inline void Cyc();
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inline void Cyc();
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@ -75,9 +75,6 @@ TODO:
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- neruton / majxtal7: girls are behind the background in demo mode.
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- neruton / majxtal7: girls are behind the background in demo mode.
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- tenkai: Interrupts are not quite right; "RAM ERROR" at startup and music slows
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down while dealing tiles in attract mode.
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*********************************************************************************************************************/
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*********************************************************************************************************************/
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#include "emu.h"
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#include "emu.h"
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@ -4823,18 +4820,21 @@ MACHINE_CONFIG_END
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void dynax_state::tenkai_update_irq()
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void dynax_state::tenkai_update_irq()
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{
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{
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m_maincpu->set_input_line(INPUT_LINE_IRQ0, m_blitter_irq);
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if (m_blitter_irq_mask)
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m_maincpu->set_input_line(INPUT_LINE_IRQ0, m_blitter_irq);
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}
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}
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WRITE_LINE_MEMBER(dynax_state::tenkai_blitter_ack_w)
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WRITE_LINE_MEMBER(dynax_state::tenkai_blitter_ack_w)
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{
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{
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m_blitter_irq_mask = state;
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m_blitter_irq_mask = state;
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// this must be acknowledged somewhere else
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if (!m_blitter_irq_mask)
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if (!m_blitter_irq_mask)
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{
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m_blitter_irq = 0;
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m_blitter_irq = 0;
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m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
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tenkai_update_irq();
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}
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else
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tenkai_update_irq();
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}
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}
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@ -4924,7 +4924,6 @@ MACHINE_CONFIG_START(dynax_state::gekisha)
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MCFG_CPU_ADD("maincpu",TMP90841, XTAL(10'000'000) ) // ?
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MCFG_CPU_ADD("maincpu",TMP90841, XTAL(10'000'000) ) // ?
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MCFG_CPU_PROGRAM_MAP(gekisha_map)
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MCFG_CPU_PROGRAM_MAP(gekisha_map)
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MCFG_TLCS90_PORT_P4_WRITE_CB(WRITE8(dynax_state, gekisha_p4_w))
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MCFG_TLCS90_PORT_P4_WRITE_CB(WRITE8(dynax_state, gekisha_p4_w))
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MCFG_CPU_VBLANK_INT_DRIVER("screen", dynax_state, irq0_line_hold)
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MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
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MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
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MCFG_DEVICE_PROGRAM_MAP(gekisha_banked_map)
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MCFG_DEVICE_PROGRAM_MAP(gekisha_banked_map)
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@ -4955,6 +4954,7 @@ MACHINE_CONFIG_START(dynax_state::gekisha)
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MCFG_SCREEN_VISIBLE_AREA(2, 256-1, 16, 256-1)
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MCFG_SCREEN_VISIBLE_AREA(2, 256-1, 16, 256-1)
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MCFG_SCREEN_UPDATE_DRIVER(dynax_state, screen_update_mjdialq2)
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MCFG_SCREEN_UPDATE_DRIVER(dynax_state, screen_update_mjdialq2)
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MCFG_SCREEN_PALETTE("palette")
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MCFG_SCREEN_PALETTE("palette")
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MCFG_SCREEN_VBLANK_CALLBACK(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_PALETTE_ADD("palette", 512)
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MCFG_PALETTE_ADD("palette", 512)
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MCFG_PALETTE_INIT_OWNER(dynax_state,sprtmtch) // static palette
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MCFG_PALETTE_INIT_OWNER(dynax_state,sprtmtch) // static palette
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