mirror of
https://github.com/holub/mame
synced 2025-04-24 17:30:55 +03:00
misc progress (nw)
This commit is contained in:
David Haywood
parent
4603e5e51a
commit
3d7aa213b4
@ -36,6 +36,8 @@
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#include "cpu/m68000/m68000.h"
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#include "cpu/z80/z80.h"
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#include "video/ramdac.h"
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#include "machine/i8255.h"
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class megaphx_state : public driver_device
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{
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@ -56,24 +58,23 @@ public:
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DECLARE_MACHINE_RESET(megaphx);
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DECLARE_READ16_MEMBER(megaphx_60004_r);
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DECLARE_READ16_MEMBER(megaphx_50002_r);
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DECLARE_CUSTOM_INPUT_MEMBER(megaphx_rand_r);
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DECLARE_READ16_MEMBER(tms_host_r);
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DECLARE_WRITE16_MEMBER(tms_host_w);
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};
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READ16_MEMBER(megaphx_state::megaphx_60004_r)
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CUSTOM_INPUT_MEMBER(megaphx_state::megaphx_rand_r)
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{
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return rand();
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}
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READ16_MEMBER(megaphx_state::megaphx_50002_r)
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{
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return rand();
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}
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READ16_MEMBER(megaphx_state::tms_host_r)
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{
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@ -90,31 +91,34 @@ WRITE16_MEMBER(megaphx_state::tms_host_w)
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static ADDRESS_MAP_START( megaphx_68k_map, AS_PROGRAM, 16, megaphx_state )
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// AM_RANGE(0x000000, 0x0000ff) AM_ROM
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AM_RANGE(0x000000, 0x00ffff) AM_RAM AM_SHARE("mainram")
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AM_RANGE(0x000000, 0x00ffff) AM_RAM AM_SHARE("mainram") // we copy the vectors from roms 6+7 to ram here, but where do the rest of those roms map?
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AM_RANGE(0x040000, 0x040007) AM_READWRITE(tms_host_r, tms_host_w)
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AM_RANGE(0x050002, 0x050003) AM_READ(megaphx_50002_r)
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// AM_RANGE(0x050000, 0x050001) AM_WRITENOP
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AM_RANGE(0x050002, 0x050003) AM_READ_PORT("P3")
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AM_RANGE(0x060004, 0x060005) AM_READ(megaphx_60004_r)
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AM_RANGE(0x060006, 0x060007) AM_WRITENOP
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AM_RANGE(0x060000, 0x060007) AM_DEVREADWRITE8("ppi8255_0", i8255_device, read, write, 0x00ff)
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AM_RANGE(0x800000, 0x8fffff) AM_ROM
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AM_RANGE(0x800000, 0x83ffff) AM_ROM AM_REGION("roms01", 0x00000)
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AM_RANGE(0x840000, 0x87ffff) AM_ROM AM_REGION("roms23", 0x00000)
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AM_RANGE(0x880000, 0x8bffff) AM_ROM AM_REGION("roms45", 0x00000)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( megaphx_tms_map, AS_PROGRAM, 16, megaphx_state )
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AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_SHARE("vram") // vram?
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AM_RANGE(0x00100000, 0x002fffff) AM_RAM // vram?
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AM_RANGE(0x00300000, 0x003fffff) AM_RAM
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AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_SHARE("vram") // vram?
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// AM_RANGE(0x00100000, 0x002fffff) AM_RAM // vram?
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// AM_RANGE(0x00300000, 0x003fffff) AM_RAM
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// AM_RANGE(0x04000000, 0x040000ff) AM_WRITENOP
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AM_RANGE(0x04000000, 0x0400000f) AM_DEVWRITE8("ramdac",ramdac_device,index_w,0x00ff)
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AM_RANGE(0x04000010, 0x0400001f) AM_DEVREADWRITE8("ramdac",ramdac_device,pal_r,pal_w,0x00ff)
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AM_RANGE(0x04000030, 0x0400003f) AM_DEVWRITE8("ramdac",ramdac_device,index_r_w,0x00ff)
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AM_RANGE(0x04000090, 0x0400009f) AM_WRITENOP
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AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, tms34010_io_register_w)
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AM_RANGE(0xffc00000, 0xffffffff) AM_RAM
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@ -155,10 +159,14 @@ static void megaphx_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int sc
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static void megaphx_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
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{
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megaphx_state *state = space.machine().driver_data<megaphx_state>();
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memcpy(shiftreg, &state->m_vram[TOWORD(address)/* & ~TOWORD(0x1fff)*/], TOBYTE(0x2000));
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}
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static void megaphx_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
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{
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megaphx_state *state = space.machine().driver_data<megaphx_state>();
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memcpy(&state->m_vram[TOWORD(address)/* & ~TOWORD(0x1fff)*/], shiftreg, TOBYTE(0x2000));
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}
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MACHINE_RESET_MEMBER(megaphx_state,megaphx)
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@ -190,6 +198,115 @@ static const tms34010_config tms_config_megaphx =
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static INPUT_PORTS_START( megaphx )
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PORT_START("P0")
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PORT_DIPNAME( 0x0001, 0x0001, "0" )
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
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PORT_START("P1")
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PORT_DIPNAME( 0x0001, 0x0001, "2" )
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
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PORT_START("P2")
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PORT_DIPNAME( 0x0001, 0x0001, "4" )
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0002, 0x0000, DEF_STR( Unknown ) ) // must be 'on' to boot, but is also p2 start? multiplexed?
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PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, megaphx_state,megaphx_rand_r, NULL)
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PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_START("P3")
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PORT_DIPNAME( 0x0001, 0x0001,"X")
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, megaphx_state,megaphx_rand_r, NULL)
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PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0100, 0x0100, "Y" )
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PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0200, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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INPUT_PORTS_END
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static ADDRESS_MAP_START( ramdac_map, AS_0, 8, megaphx_state )
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@ -201,6 +318,17 @@ static RAMDAC_INTERFACE( ramdac_intf )
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1
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};
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static I8255A_INTERFACE( ppi8255_intf_0 )
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{
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DEVCB_INPUT_PORT("P0"), /* Port A read */
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DEVCB_NULL, /* Port A write */
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DEVCB_INPUT_PORT("P1"), /* Port B read */
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DEVCB_NULL, /* Port B write */
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DEVCB_INPUT_PORT("P2"), /* Port C read */
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DEVCB_NULL /* Port C write */
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};
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static MACHINE_CONFIG_START( megaphx, megaphx_state )
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@ -217,6 +345,8 @@ static MACHINE_CONFIG_START( megaphx, megaphx_state )
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MCFG_CPU_PROGRAM_MAP(sound_map)
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MCFG_CPU_IO_MAP(sound_io)
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MCFG_I8255A_ADD( "ppi8255_0", ppi8255_intf_0 )
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MCFG_MACHINE_RESET_OVERRIDE(megaphx_state,megaphx)
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@ -234,23 +364,28 @@ MACHINE_CONFIG_END
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DRIVER_INIT_MEMBER(megaphx_state,megaphx)
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{
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UINT16 *src = (UINT16*)memregion( "maincpu" )->base();
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UINT16 *src = (UINT16*)memregion( "roms67" )->base();
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// copy vector table?
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memcpy(m_mainram, src, 0x100);
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}
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ROM_START( megaphx )
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ROM_REGION( 0x1000000, "maincpu", 0 )
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ROM_REGION16_BE( 0x40000, "roms67", 0 )
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ROM_LOAD16_BYTE( "mph6.u32", 0x000001, 0x20000, CRC(b99703d4) SHA1(393b6869e71d4c61060e66e0e9e36a1e6ca345d1) )
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ROM_LOAD16_BYTE( "mph7.u21", 0x000000, 0x20000, CRC(f11e7449) SHA1(1017142d10011d68e49d3ccdb1ac4e815c03b17a) )
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ROM_LOAD16_BYTE( "mph0.u38", 0x800001, 0x20000, CRC(b63dd20f) SHA1(c8ce5985a6ba49428d66a49d9d623ccdfce422c2) )
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ROM_LOAD16_BYTE( "mph1.u27", 0x800000, 0x20000, CRC(4dcbf44b) SHA1(a8fa49ecd033f1aeb323e0032ddcf5f8f9463ac0) )
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ROM_LOAD16_BYTE( "mph2.u37", 0x840001, 0x20000, CRC(a0f69c27) SHA1(d0c5c241d94a1f03f51e7e517e2f9dec6abcf75a) )
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ROM_LOAD16_BYTE( "mph3.u26", 0x840000, 0x20000, CRC(4db84cc5) SHA1(dd74acd4b32c7e7553554ac0f9ba13503358e869) )
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ROM_LOAD16_BYTE( "mph4.u36", 0x880001, 0x20000, CRC(c8e0725e) SHA1(b3af315b9a94a692e81e0dbfd4035036c2af4f50) )
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ROM_LOAD16_BYTE( "mph5.u25", 0x880000, 0x20000, CRC(c95ccb69) SHA1(9d14cbfafd943f6ff461a7f373170a35e36eb695) )
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ROM_REGION16_BE( 0x40000, "roms01", 0 )
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ROM_LOAD16_BYTE( "mph0.u38", 0x000001, 0x20000, CRC(b63dd20f) SHA1(c8ce5985a6ba49428d66a49d9d623ccdfce422c2) )
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ROM_LOAD16_BYTE( "mph1.u27", 0x000000, 0x20000, CRC(4dcbf44b) SHA1(a8fa49ecd033f1aeb323e0032ddcf5f8f9463ac0) )
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ROM_REGION16_BE( 0x40000, "roms23", 0 )
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ROM_LOAD16_BYTE( "mph2.u37", 0x000001, 0x20000, CRC(a0f69c27) SHA1(d0c5c241d94a1f03f51e7e517e2f9dec6abcf75a) )
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ROM_LOAD16_BYTE( "mph3.u26", 0x000000, 0x20000, CRC(4db84cc5) SHA1(dd74acd4b32c7e7553554ac0f9ba13503358e869) )
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ROM_REGION16_BE( 0x40000, "roms45", 0 )
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ROM_LOAD16_BYTE( "mph4.u36", 0x000001, 0x20000, CRC(c8e0725e) SHA1(b3af315b9a94a692e81e0dbfd4035036c2af4f50) )
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ROM_LOAD16_BYTE( "mph5.u25", 0x000000, 0x20000, CRC(c95ccb69) SHA1(9d14cbfafd943f6ff461a7f373170a35e36eb695) )
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ROM_REGION( 0x200000, "user2", 0 )
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ROM_LOAD( "sonido_mph1.u39", 0x000000, 0x20000, CRC(f5e65557) SHA1(5ae759c2bcef96fbda42f088c02b6dec208030f3) )
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