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alto2: replace decoded MIR bit fields

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Instead of using a number of UINT8 with the decoded bit fields of the
MIR (micro instruction register), add inline functions to extract the
bits from m_mir. That ought to be faster, because there are fewer memory
accesses in cases where bit fields are not actually used by an instruction.
This commit is contained in:
jbu 2016-08-03 23:25:45 +02:00
parent 434c885e47
commit 3e1996ec5a
5 changed files with 53 additions and 65 deletions
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4
src/devices/cpu/alto2/a2emu.cpp
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@ -365,7 +365,7 @@ void alto2_cpu_device::f2_late_busodd()
void alto2_cpu_device::f2_late_magic()
{
int XC;
switch (m_d_f1) {
switch (f1()) {
case f1_l_lsh_1: // <-L MLSH 1
XC = (m_t >> 15) & 1;
m_shifter = (m_l << 1) | XC;
@ -441,7 +441,7 @@ void alto2_cpu_device::f2_late_load_dns()
UINT8 DSKIP;
UINT8 SHZERO;
switch (m_d_f1) {
switch (f1()) {
case f1_l_rsh_1: // <-L RSH 1
NEWCARRY = m_l & 1;
m_shifter = ((m_l >> 1) | (XC << 15)) & 0177777;

16
src/devices/cpu/alto2/a2ether.cpp
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@ -863,7 +863,7 @@ void alto2_cpu_device::update_sysclk(int sysclk)
* Q' OCMD'
*/
s0 = m_eth.ff_35a;
s1 = (m_d_f1 == f1_emu_startf && sysclk) ? JKFF_CLK : JKFF_0;
s1 = (f1() == f1_emu_startf && sysclk) ? JKFF_CLK : JKFF_0;
if (X_BIT(m_bus,16,15))
s1 |= JKFF_J;
s1 |= JKFF_K;
@ -885,7 +885,7 @@ void alto2_cpu_device::update_sysclk(int sysclk)
* Q' ICMD'
*/
s0 = m_eth.ff_35b;
s1 = (m_d_f1 == f1_emu_startf && sysclk) ? JKFF_CLK : JKFF_0;
s1 = (f1() == f1_emu_startf && sysclk) ? JKFF_CLK : JKFF_0;
if (X_BIT(m_bus,16,14))
s1 |= JKFF_J;
s1 |= JKFF_K;
@ -905,7 +905,7 @@ void alto2_cpu_device::update_sysclk(int sysclk)
*/
s0 = m_eth.ff_10a;
s1 = sysclk ? JKFF_CLK : JKFF_0;
if (m_d_f2 != f2_ether_eisfct)
if (f2() != f2_ether_eisfct)
s1 |= JKFF_K;
s1 |= JKFF_C;
m_eth.ff_10a = update_jkff(s0, s1, "10a IBUSY ");
@ -931,15 +931,15 @@ void alto2_cpu_device::update_sysclk(int sysclk)
UINT8 RR;
UINT8 WLL0;
if (m_eth.ff_10a & JKFF_Q) {
WLLOAD = ~(sysclk & (m_d_f2 == f2_ether_eodfct)) & 1;
WLLOAD = ~(sysclk & (f2() == f2_ether_eodfct)) & 1;
RDCNT0 = m_eth.ff_52b & JKFF_Q ? 1 : 0;
RR = m_eth.ff_52b & JKFF_Q0 ? 1 : 0;
WLL0 = ~(sysclk & (m_d_f2 == f2_ether_eodfct)) & 1;
WLL0 = ~(sysclk & (f2() == f2_ether_eodfct)) & 1;
} else {
// ISRFULL
WLLOAD = (m_eth.serin >> 1) & 1;
RDCNT0 = ~(sysclk & (m_d_bs == bs_ether_eidfct)) & 1;
RR = m_d_bs == bs_ether_eidfct || m_d_f1 == f1_ether_eilfct;
RDCNT0 = ~(sysclk & (bs() == bs_ether_eidfct)) & 1;
RR = bs() == bs_ether_eidfct || f1() == f1_ether_eilfct;
WLL0 = m_eth.ff_77b & JKFF_Q0 ? 1 : 0;
}
// TODO: use the signals
@ -960,7 +960,7 @@ void alto2_cpu_device::update_sysclk(int sysclk)
*/
s0 = m_eth.ff_10b;
s1 = sysclk ? JKFF_CLK : JKFF_0;
if (m_d_f2 != f2_ether_eosfct)
if (f2() != f2_ether_eosfct)
s1 |= JKFF_K;
m_eth.ff_10b = update_jkff(s0, s1, "10b OBUSY ");

14
src/devices/cpu/alto2/a2ram.cpp
View File

@ -153,13 +153,13 @@ void alto2_cpu_device::bs_early_read_sreg()
{
UINT16 r;
if (m_d_rsel) {
if (rsel()) {
UINT8 bank = m_s_reg_bank[m_task];
r = m_s[bank][m_d_rsel];
LOG((this,LOG_RAM,2," <-S%02o; bus &= S[%o][%02o] (%#o)\n", m_d_rsel, bank, m_d_rsel, r));
r = m_s[bank][rsel()];
LOG((this,LOG_RAM,2," <-S%02o; bus &= S[%o][%02o] (%#o)\n", rsel(), bank, rsel(), r));
} else {
r = m_m;
LOG((this,LOG_RAM,2," <-S%02o; bus &= M (%#o)\n", m_d_rsel, r));
LOG((this,LOG_RAM,2," <-S%02o; bus &= M (%#o)\n", rsel(), r));
}
m_bus &= r;
}
@ -170,7 +170,7 @@ void alto2_cpu_device::bs_early_read_sreg()
void alto2_cpu_device::bs_early_load_sreg()
{
int r = 0; /* ??? */
LOG((this,LOG_RAM,2," S%02o<- BUS &= garbage (%#o)\n", m_d_rsel, r));
LOG((this,LOG_RAM,2," S%02o<- BUS &= garbage (%#o)\n", rsel(), r));
m_bus &= r;
}
@ -180,8 +180,8 @@ void alto2_cpu_device::bs_early_load_sreg()
void alto2_cpu_device::bs_late_load_sreg()
{
UINT8 bank = m_s_reg_bank[m_task];
m_s[bank][m_d_rsel] = m_m;
LOG((this,LOG_RAM,2," S%02o<- S[%o][%02o] := %#o\n", m_d_rsel, bank, m_d_rsel, m_m));
m_s[bank][rsel()] = m_m;
LOG((this,LOG_RAM,2," S%02o<- S[%o][%02o] := %#o\n", rsel(), bank, rsel(), m_m));
}
/**

68
src/devices/cpu/alto2/alto2cpu.cpp
View File

@ -135,13 +135,6 @@ alto2_cpu_device::alto2_cpu_device(const machine_config& mconfig, const char* ta
m_mpc(0),
m_mir(0),
m_rsel(0),
m_d_rsel(0),
m_d_aluf(0),
m_d_bs(0),
m_d_f1(0),
m_d_f2(0),
m_d_loadt(0),
m_d_loadl(0),
m_next(0),
m_next2(0),
m_bus(0),
@ -1293,42 +1286,42 @@ void alto2_cpu_device::watch_write(UINT32 addr, UINT32 data)
void alto2_cpu_device::fn_bs_bad_0()
{
fatal(9,"fatal: bad early bus source pointer for task %s, mpc:%05o bs:%s\n",
task_name(m_task), m_mpc, bs_name(m_d_bs));
task_name(m_task), m_mpc, bs_name(bs()));
}
/** @brief fatal exit on unitialized latching phase BUS source */
void alto2_cpu_device::fn_bs_bad_1()
{
fatal(9,"fatal: bad late bus source pointer for task %s, mpc:%05o bs: %s\n",
task_name(m_task), m_mpc, bs_name(m_d_bs));
task_name(m_task), m_mpc, bs_name(bs()));
}
/** @brief fatal exit on unitialized dynamic phase F1 function */
void alto2_cpu_device::fn_f1_bad_0()
{
fatal(9,"fatal: bad early f1 function pointer for task %s, mpc:%05o f1: %s\n",
task_name(m_task), m_mpc, f1_name(m_d_f1));
task_name(m_task), m_mpc, f1_name(f1()));
}
/** @brief fatal exit on unitialized latching phase F1 function */
void alto2_cpu_device::fn_f1_bad_1()
{
fatal(9,"fatal: bad late f1 function pointer for task %s, mpc:%05o f1: %s\n",
task_name(m_task), m_mpc, f1_name(m_d_f1));
task_name(m_task), m_mpc, f1_name(f1()));
}
/** @brief fatal exit on unitialized dynamic phase F2 function */
void alto2_cpu_device::fn_f2_bad_0()
{
fatal(9,"fatal: bad early f2 function pointer for task %s, mpc:%05o f2: %s\n",
task_name(m_task), m_mpc, f2_name(m_d_f2));
task_name(m_task), m_mpc, f2_name(f2()));
}
/** @brief fatal exit on unitialized latching phase F2 function */
void alto2_cpu_device::fn_f2_bad_1()
{
fatal(9,"fatal: bad late f2 function pointer for task %s, mpc:%05o f2: %s\n",
task_name(m_task), m_mpc, f2_name(m_d_f2));
task_name(m_task), m_mpc, f2_name(f2()));
}
#if ALTO2_DEBUG
@ -1463,7 +1456,7 @@ void alto2_cpu_device::bs_early_load_r()
*/
void alto2_cpu_device::bs_late_load_r()
{
if (m_d_f2 != f2_emu_load_dns) {
if (f2() != f2_emu_load_dns) {
m_r[m_rsel] = m_shifter;
LOG((this,LOG_CPU,2," R%02o<-; %s = SHIFTER (%#o)\n", m_rsel, r_name(m_rsel), m_shifter));
}
@ -1513,7 +1506,7 @@ void alto2_cpu_device::f1_late_load_mar()
{
UINT8 bank = m_bank_reg[m_task];
UINT32 msb;
if (m_d_f2 == f2_load_md) {
if (f2() == f2_load_md) {
msb = GET_BANK_EXTENDED(bank) << 16;
LOG((this,LOG_CPU,7, " XMAR %#o\n", msb | m_alu));
} else {
@ -1892,7 +1885,7 @@ void alto2_cpu_device::f2_late_load_md()
#if ALTO2_DEBUG
UINT16 mar = m_mem.mar;
#endif
if (m_d_f1 == f1_load_mar) {
if (f1() == f1_load_mar) {
/* part of an XMAR */
LOG((this,LOG_CPU,2, " XMAR %#o (%#o)\n", mar, m_bus));
} else {
@ -2291,24 +2284,17 @@ void alto2_cpu_device::execute_run()
m_mpc = m_next; // next instruction's micro program counter
m_mir = RD_UCODE(m_mpc); // fetch the micro code
// extract the bit fields
m_d_rsel = m_rsel = X_RDBITS(m_mir, 32, DRSEL0, DRSEL4);
m_d_aluf = X_RDBITS(m_mir, 32, DALUF0, DALUF3);
m_d_bs = X_RDBITS(m_mir, 32, DBS0, DBS2);
m_d_f1 = X_RDBITS(m_mir, 32, DF1_0, DF1_3);
m_d_f2 = X_RDBITS(m_mir, 32, DF2_0, DF2_3);
m_d_loadt = X_BIT(m_mir, 32, DLOADT);
m_d_loadl = X_BIT(m_mir, 32, DLOADL);
m_rsel = rsel();
debugger_instruction_hook(this, m_mpc);
m_cycle++;
if (m_d_f1 == f1_load_mar && check_mem_load_mar_stall(m_rsel)) {
if (f1() == f1_load_mar && check_mem_load_mar_stall(m_rsel)) {
LOG((this,LOG_CPU,3, " MAR<- stall\n"));
continue;
}
if (m_d_f2 == f2_load_md && check_mem_write_stall()) {
if (f2() == f2_load_md && check_mem_write_stall()) {
LOG((this,LOG_CPU,3, " MD<- stall\n"));
continue;
}
@ -2317,17 +2303,17 @@ void alto2_cpu_device::execute_run()
* or f2 == f2_const. These functions use the MIR BS field to
* provide a part of the address to the constant ROM instead.
*/
do_bs = !(m_d_f1 == f1_const || m_d_f2 == f2_const);
if (do_bs && m_d_bs == bs_read_md && check_mem_read_stall()) {
do_bs = !(f1() == f1_const || f2() == f2_const);
if (do_bs && bs() == bs_read_md && check_mem_read_stall()) {
LOG((this,LOG_CPU,3, " <-MD stall\n"));
continue;
}
// now read the next instruction field from the MIR and modify it
m_next = X_RDBITS(m_mir, 32, NEXT0, NEXT9) | m_next2;
m_next = next() | m_next2;
// prefetch the next instruction's next field as next2
m_next2 = X_RDBITS(RD_UCODE(m_next), 32, NEXT0, NEXT9) | (m_next2 & ~ALTO2_UCODE_PAGE_MASK);
LOG((this,LOG_CPU,2,"%s-%04o: %011o r:%02o aluf:%02o bs:%02o f1:%02o f2:%02o t:%o l:%o next:%05o next2:%05o\n",
task_name(m_task), m_mpc, m_mir, m_rsel, m_d_aluf, m_d_bs, m_d_f1, m_d_f2, m_d_loadt, m_d_loadl, m_next, m_next2));
task_name(m_task), m_mpc, m_mir, m_rsel, aluf(), bs(), f1(), f2(), loadt(), loadl(), m_next, m_next2));
// BUS is all ones at the start of each cycle
m_bus = 0177777;
@ -2336,8 +2322,8 @@ void alto2_cpu_device::execute_run()
rdram();
// The constant memory is gated to the bus by F1 == f1_const, F2 == f2_const, or BS >= 4
if (!do_bs || m_d_bs >= bs_task_4) {
UINT32 addr = 8 * m_rsel + m_d_bs;
if (!do_bs || bs() >= bs_task_4) {
UINT32 addr = 8 * m_rsel + bs();
// FIXME: is the format of m_const_data endian safe?
UINT16 data = m_const_data[2*addr] | (m_const_data[2*addr+1] << 8);
m_bus &= data;
@ -2349,14 +2335,14 @@ void alto2_cpu_device::execute_run()
* because the emulator task F2 acsource or acdest may
* change the m_rsel
*/
((*this).*m_f2[0][m_task][m_d_f2])();
((*this).*m_f2[0][m_task][f2()])();
// early BS function can be done now
if (do_bs)
((*this).*m_bs[0][m_task][m_d_bs])();
((*this).*m_bs[0][m_task][bs()])();
// early F1 function
((*this).*m_f1[0][m_task][m_d_f1])();
((*this).*m_f1[0][m_task][f1()])();
/**
* The ALU a10 PROM address lines are
@ -2367,7 +2353,7 @@ void alto2_cpu_device::execute_run()
*
* B1 and B3-B7 are inverted on loading the PROM
*/
UINT8 a10 = m_alu_a10[(m_emu.skip << 4) | m_d_aluf];
UINT8 a10 = m_alu_a10[(m_emu.skip << 4) | aluf()];
UINT32 alu = alu_74181(m_bus, m_t, a10);
m_aluc0 = (alu >> 16) & 1;
flags = a10 & (TSELECT | ALUM);
@ -2381,17 +2367,17 @@ void alto2_cpu_device::execute_run()
m_shifter = m_l;
// late F1 function call now
((*this).*m_f1[1][m_task][m_d_f1])();
((*this).*m_f1[1][m_task][f1()])();
// late F2 function call now
((*this).*m_f2[1][m_task][m_d_f2])();
((*this).*m_f2[1][m_task][f2()])();
// late BS function call now, if no constant was put on the bus
if (do_bs)
((*this).*m_bs[1][m_task][m_d_bs])();
((*this).*m_bs[1][m_task][bs()])();
// update T register, if LOADT is set
if (m_d_loadt) {
if (loadt()) {
m_cram_addr = m_alu; // latch CRAM address
if (flags & TSELECT) {
m_t = m_alu; // T source is ALU
@ -2403,7 +2389,7 @@ void alto2_cpu_device::execute_run()
}
// update L register and LALUC0 if LOADL is set
if (m_d_loadl) {
if (loadl()) {
m_l = m_alu; // load L from ALU
if (flags & ALUM) {
m_laluc0 = 0; // logic operation - put 0 into latched carry

16
src/devices/cpu/alto2/alto2cpu.h
View File

@ -549,6 +549,15 @@ private:
UINT16 m_mpc; //!< micro program counter
UINT32 m_mir; //!< micro instruction register
inline UINT32 rsel() const { return X_RDBITS(m_mir, 32, DRSEL0, DRSEL4); }
inline UINT32 aluf() const { return X_RDBITS(m_mir, 32, DALUF0, DALUF3); }
inline UINT32 bs() const { return X_RDBITS(m_mir, 32, DBS0, DBS2); }
inline UINT32 f1() const { return X_RDBITS(m_mir, 32, DF1_0, DF1_3); }
inline UINT32 f2() const { return X_RDBITS(m_mir, 32, DF2_0, DF2_3); }
inline UINT32 loadt() const { return X_BIT(m_mir, 32, DLOADT); }
inline UINT32 loadl() const { return X_BIT(m_mir, 32, DLOADL); }
inline UINT32 next() const { return X_RDBITS(m_mir, 32, NEXT0, NEXT9); }
/**
* \brief current micro instruction's register selection
* The emulator F2s ACSOURCE and ACDEST modify this.
@ -556,13 +565,6 @@ private:
* even when the emulator modifies this.
*/
UINT8 m_rsel;
UINT8 m_d_rsel; //!< decoded RSEL[0-4]
UINT8 m_d_aluf; //!< decoded ALUF[0-3] function
UINT8 m_d_bs; //!< decoded BS[0-2] bus source
UINT8 m_d_f1; //!< decoded F1[0-3] function
UINT8 m_d_f2; //!< decoded F2[0-3] function
UINT8 m_d_loadt; //!< decoded LOADT flag
UINT8 m_d_loadl; //!< decoded LOADL flag
UINT16 m_next; //!< current micro instruction's next
UINT16 m_next2; //!< next micro instruction's next
UINT16 m_r[ALTO2_REGS]; //!< R register file