mirror of
https://github.com/holub/mame
synced 2025-07-04 17:38:08 +03:00
Updated Naomi driver, now boots and shows some test menus (press F2 to get into test, use 9 to navigate). Also hooked up ROM board PIO and skeleton for DMA.
Please co-credit Samuele Zannoli and ElSemi.
This commit is contained in:
R. Belmont
parent
b6a4ebd248
commit
3e433a79ee
@ -3,7 +3,7 @@
|
||||
Sega Naomi
|
||||
+ Related Systems (possibly to be split at a later date)
|
||||
|
||||
Skeleton Driver
|
||||
Driver by Samuele Zannoli, R. Belmont, and ElSemi.
|
||||
|
||||
Sega Naomi is Dreamcast based Arcade hardware.
|
||||
|
||||
@ -445,13 +445,128 @@ Naomi 2 / GD-ROM | | |
|
||||
/* MD2 MD1 MD0 MD6 MD4 MD3 MD5 MD7 MD8 */
|
||||
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CPU_CLOCK };
|
||||
|
||||
static UINT64 *dc_sound_ram;
|
||||
static UINT32 *dc_sound_ram;
|
||||
extern UINT64 *dc_texture_ram;
|
||||
static UINT32 rom_offset, dma_offset;
|
||||
|
||||
static INTERRUPT_GEN( naomi_vblank )
|
||||
{
|
||||
dc_vblank();
|
||||
}
|
||||
|
||||
READ64_HANDLER( naomi_arm_r )
|
||||
{
|
||||
return *((UINT64 *)dc_sound_ram+offset);
|
||||
}
|
||||
|
||||
WRITE64_HANDLER( naomi_arm_w )
|
||||
{
|
||||
COMBINE_DATA((UINT64 *)dc_sound_ram + offset);
|
||||
}
|
||||
|
||||
READ64_HANDLER( naomi_unknown1_r )
|
||||
{
|
||||
if ((offset * 8) == 0xc0) // trick so that it does not "wait for multiboard sync"
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE64_HANDLER( naomi_unknown1_w )
|
||||
{
|
||||
}
|
||||
|
||||
READ32_HANDLER( dc_aica_arm_r )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE32_HANDLER( dc_aica_arm_w )
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
Naomi ROM board info from ElSemi:
|
||||
|
||||
NAOMI_ROM_OFFSETH = 0x5f7000,
|
||||
NAOMI_ROM_OFFSETL = 0x5f7004,
|
||||
NAOMI_ROM_DATA = 0x5f7008,
|
||||
NAOMI_DMA_OFFSETH = 0x5f700C,
|
||||
NAOMI_DMA_OFFSETL = 0x5f7010,
|
||||
NAOMI_DMA_COUNT = 0x5f7014,
|
||||
NAOMI_COMM_OFFSET = 0x5F7050,
|
||||
NAOMI_COMM_DATA = 0x5F7054,
|
||||
NAOMI_BOARDID_WRITE = 0x5F7078,
|
||||
NAOMI_BOARDID_READ = 0x5F707C,
|
||||
each port is 16 bit wide, to access the rom in PIO mode, just set an offset in ROM_OFFSETH/L and read from ROM_DATA, each access reads 2 bytes and increases the offset by 2.
|
||||
|
||||
the BOARDID regs access the password protected eeprom in the game board. the main board eeprom is read through port 0x1F800030
|
||||
|
||||
To access the board using DMA, use the DMA_OFFSETL/H. DMA_COUNT is in units of 0x20 bytes. Then trigger a GDROM DMA request.
|
||||
*/
|
||||
|
||||
// NOTE: all accesses are 16 or 32 bits wide but only 16 bits are valid
|
||||
|
||||
READ64_HANDLER( naomi_rom_board_r )
|
||||
{
|
||||
UINT8 *ROM = (UINT8 *)memory_region(REGION_USER1);
|
||||
|
||||
// ROM_DATA
|
||||
if ((offset == 1) && ((mem_mask & 0xffff) == 0))
|
||||
{
|
||||
UINT64 ret;
|
||||
|
||||
ret = (UINT64)(ROM[rom_offset] | (ROM[rom_offset+1]<<8));
|
||||
|
||||
rom_offset += 2;
|
||||
|
||||
return ret;
|
||||
}
|
||||
else
|
||||
{
|
||||
mame_printf_verbose("ROM: read mask %llx @ %x (PC=%x)\n", mem_mask, offset, activecpu_get_pc());
|
||||
}
|
||||
|
||||
return U64(0xffffffffffffffff);
|
||||
}
|
||||
|
||||
WRITE64_HANDLER( naomi_rom_board_w )
|
||||
{
|
||||
if ((offset == 1) && ((mem_mask & U64(0xffff)) == 0))
|
||||
{
|
||||
// DMA_OFFSETH
|
||||
dma_offset &= 0xffff;
|
||||
dma_offset |= (data & 0x1fff)<<16;
|
||||
}
|
||||
else if ((offset == 1) && ((mem_mask & U64(0xffff00000000)) == 0))
|
||||
{
|
||||
// DMA_OFFSETL
|
||||
dma_offset &= 0xffff0000;
|
||||
dma_offset |= (data & 0xffff);
|
||||
}
|
||||
else if ((offset == 0) && ((mem_mask & U64(0xffff)) == 0))
|
||||
{
|
||||
// ROM_OFFSETH
|
||||
rom_offset &= 0xffff;
|
||||
rom_offset |= (data & 0x1fff)<<16;
|
||||
}
|
||||
else if ((offset == 0) && ((mem_mask & U64(0xffff00000000)) == 0))
|
||||
{
|
||||
// ROM_OFFSETL
|
||||
rom_offset &= 0xffff0000;
|
||||
rom_offset |= (data & 0xffff);
|
||||
}
|
||||
else
|
||||
{
|
||||
mame_printf_verbose("ROM: write %llx to %x, mask %llx (PC=%x)\n", data, offset, mem_mask, activecpu_get_pc());
|
||||
}
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( naomi_map, ADDRESS_SPACE_PROGRAM, 64 )
|
||||
AM_RANGE(0x00000000, 0x001fffff) AM_ROM // BIOS
|
||||
AM_RANGE(0x00000000, 0x001fffff) AM_ROM // BIOS
|
||||
AM_RANGE(0x00200000, 0x00207fff) AM_RAM // bios uses it (battery backed ram ?)
|
||||
AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE( dc_sysctrl_r, dc_sysctrl_w )
|
||||
AM_RANGE(0x005f6c00, 0x005f6cff) AM_READWRITE( dc_maple_r, dc_maple_w )
|
||||
AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE( dc_gdrom_r, dc_gdrom_w )
|
||||
AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE( naomi_rom_board_r, naomi_rom_board_w )
|
||||
AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE( dc_g1_ctrl_r, dc_g1_ctrl_w )
|
||||
AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE( dc_g2_ctrl_r, dc_g2_ctrl_w )
|
||||
AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE( pvr_ctrl_r, pvr_ctrl_w )
|
||||
@ -459,22 +574,33 @@ static ADDRESS_MAP_START( naomi_map, ADDRESS_SPACE_PROGRAM, 64 )
|
||||
AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE( dc_modem_r, dc_modem_w )
|
||||
AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE( dc_aica_reg_r, dc_aica_reg_w )
|
||||
AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE( dc_rtc_r, dc_rtc_w )
|
||||
AM_RANGE(0x00800000, 0x009fffff) AM_RAM AM_BASE( &dc_sound_ram ) // sound RAM
|
||||
AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE(2) // texture memory
|
||||
AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE(2) // mirror of texture RAM
|
||||
AM_RANGE(0x00800000, 0x009fffff) AM_READWRITE( naomi_arm_r, naomi_arm_w ) // sound RAM
|
||||
AM_RANGE(0x0103ff00, 0x0103ffff) AM_READWRITE( naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
|
||||
AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE(2) AM_BASE( &dc_texture_ram ) // texture memory
|
||||
AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE(2) // mirror of texture RAM
|
||||
AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_SHARE(1)
|
||||
AM_RANGE(0x0d000000, 0x0dffffff) AM_RAM AM_SHARE(1) // mirror of main RAM
|
||||
AM_RANGE(0x0d000000, 0x0dffffff) AM_RAM AM_SHARE(1) // mirror of main RAM
|
||||
AM_RANGE(0x10000000, 0x107fffff) AM_WRITE( ta_fifo_poly_w )
|
||||
AM_RANGE(0x10800000, 0x10ffffff) AM_WRITE( ta_fifo_yuv_w )
|
||||
AM_RANGE(0x11000000, 0x11ffffff) AM_RAM AM_SHARE(2) // another mirror of texture memory
|
||||
AM_RANGE(0x11000000, 0x11ffffff) AM_RAM AM_SHARE(2) // another mirror of texture memory
|
||||
AM_RANGE(0xa0000000, 0xa01fffff) AM_ROM AM_REGION(REGION_CPU1, 0)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
READ32_HANDLER( test1 )
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( dc_audio_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
AM_RANGE(0x00000000, 0x001fffff) AM_RAM /* shared with SH-4 */
|
||||
AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_BASE( &dc_sound_ram ) /* shared with SH-4 */
|
||||
AM_RANGE(0x00200000, 0x002000ff) AM_READ( test1 ) // for bug (?) in sound bios
|
||||
AM_RANGE(0x00800000, 0x00807fff) AM_READWRITE( dc_aica_arm_r, dc_aica_arm_w ) /* shared with SH-4 */
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static INPUT_PORTS_START( naomi )
|
||||
PORT_START
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Service")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F2)
|
||||
INPUT_PORTS_END
|
||||
|
||||
static MACHINE_DRIVER_START( naomi )
|
||||
@ -482,6 +608,7 @@ static MACHINE_DRIVER_START( naomi )
|
||||
MDRV_CPU_ADD_TAG("main", SH4, CPU_CLOCK) // SH4!!!
|
||||
MDRV_CPU_CONFIG(sh4cpu_config)
|
||||
MDRV_CPU_PROGRAM_MAP(naomi_map,0)
|
||||
MDRV_CPU_VBLANK_INT(naomi_vblank,479)
|
||||
|
||||
MDRV_CPU_ADD_TAG("sound", ARM7, 45000000)
|
||||
MDRV_CPU_PROGRAM_MAP(dc_audio_map, 0)
|
||||
@ -494,8 +621,8 @@ static MACHINE_DRIVER_START( naomi )
|
||||
/* video hardware */
|
||||
MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
|
||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
|
||||
MDRV_SCREEN_SIZE(16*8, 16*8)
|
||||
MDRV_SCREEN_VISIBLE_AREA(0, 16*8-1, 0, 16*8-1)
|
||||
MDRV_SCREEN_SIZE(640, 480)
|
||||
MDRV_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
|
||||
MDRV_PALETTE_LENGTH(0x1000)
|
||||
|
||||
MDRV_VIDEO_START(dc)
|
||||
@ -539,16 +666,22 @@ MACHINE_DRIVER_END
|
||||
ROM_START( naomi )
|
||||
ROM_REGION( 0x200000, REGION_CPU1, 0)
|
||||
NAOMI_BIOS
|
||||
|
||||
ROM_REGION( 0x8400000, REGION_USER1, ROMREGION_ERASE)
|
||||
ROM_END
|
||||
|
||||
ROM_START( naomi2 )
|
||||
ROM_REGION( 0x200000, REGION_CPU1, 0)
|
||||
NAOMI2_BIOS
|
||||
|
||||
ROM_REGION( 0x8400000, REGION_USER1, ROMREGION_ERASE)
|
||||
ROM_END
|
||||
|
||||
ROM_START( awbios )
|
||||
ROM_REGION( 0x200000, REGION_CPU1, 0)
|
||||
AW_BIOS
|
||||
|
||||
ROM_REGION( 0x8400000, REGION_USER1, ROMREGION_ERASE)
|
||||
ROM_END
|
||||
|
||||
/* Info above each set is automatically generated from the IC22 rom and may not be accurate */
|
||||
@ -661,7 +794,7 @@ IC4 64M 2E60 4CBF MPR23423.4
|
||||
IC5 64M BB81 7E26 MPR23424.5
|
||||
IC6 64M B3A8 F2EA MPR23425.6
|
||||
IC7 64M 05C5 A084 MPR23426.7
|
||||
IC8 64M 9E13 7535 MPR23427.8
|
||||
IC8 64M 9E13 7535 MPR23427.8
|
||||
|
||||
Serial: BCHE-01A0803
|
||||
|
||||
@ -671,18 +804,21 @@ ROM_START( csmash )
|
||||
ROM_REGION( 0x200000, REGION_CPU1, 0)
|
||||
NAOMI_BIOS
|
||||
|
||||
ROM_REGION( 0x400000, REGION_USER1, 0)
|
||||
ROM_REGION( 0x4800000, REGION_USER1, ROMREGION_ERASE00)
|
||||
ROM_LOAD("epr23428a.22", 0x0000000, 0x400000, CRC(d628dbce) SHA1(91ec1296ead572a64c37f8ac2c1a96742f19d50b) )
|
||||
ROM_RELOAD( 0x400000, 0x400000)
|
||||
ROM_LOAD("mpr23420.1", 0x0800000, 0x0800000, CRC(9d5991f2) SHA1(c75871db314b01935d1daaacf1a762e73e5fd411) )
|
||||
ROM_LOAD("mpr23421.2", 0x1000000, 0x0800000, CRC(6c351db3) SHA1(cdd601321a38fc34152517abdc473b73a4c6f630) )
|
||||
ROM_LOAD("mpr23422.3", 0x1800000, 0x0800000, CRC(a1d4bd29) SHA1(6c446fd1819f55412351f15cf57b769c0c56c1db) )
|
||||
ROM_LOAD("mpr23423.4", 0x2000000, 0x0800000, CRC(08cbf373) SHA1(0d9a593f5cc5d632d85d7253c135eef2e8e01598) )
|
||||
ROM_LOAD("mpr23424.5", 0x2800000, 0x0800000, CRC(f4404000) SHA1(e49d941e47e63bb7f3fddc3c3d2c1653611914ee) )
|
||||
ROM_LOAD("mpr23425.6", 0x3000000, 0x0800000, CRC(47f51da2) SHA1(af5ecd460114caed3a00157ffd3a2df0fbf348c0) )
|
||||
ROM_LOAD("mpr23426.7", 0x3800000, 0x0800000, CRC(7f91b13f) SHA1(2d534f77291ebfedc011bf0e803a1b9243fb477f) )
|
||||
ROM_LOAD("mpr23427.8", 0x4000000, 0x0800000, CRC(5851d525) SHA1(1cb1073542d75a3bcc0d363ed31d49bcaf1fd494) )
|
||||
|
||||
ROM_REGION(0x200000, REGION_USER2, 0)
|
||||
ROM_LOAD16_WORD_SWAP("epr-21577.bin", 0x000000, 0x200000, CRC(cf36e97b) SHA1(b085305982e7572e58b03a9d35f17ae319c3bbc6) )
|
||||
|
||||
ROM_REGION( 0x8000000, REGION_USER2, 0)
|
||||
ROM_LOAD("mpr23420.1", 0x0000000, 0x0800000, CRC(9d5991f2) SHA1(c75871db314b01935d1daaacf1a762e73e5fd411) )
|
||||
ROM_LOAD("mpr23421.2", 0x0800000, 0x0800000, CRC(6c351db3) SHA1(cdd601321a38fc34152517abdc473b73a4c6f630) )
|
||||
ROM_LOAD("mpr23422.3", 0x1000000, 0x0800000, CRC(a1d4bd29) SHA1(6c446fd1819f55412351f15cf57b769c0c56c1db) )
|
||||
ROM_LOAD("mpr23423.4", 0x1800000, 0x0800000, CRC(08cbf373) SHA1(0d9a593f5cc5d632d85d7253c135eef2e8e01598) )
|
||||
ROM_LOAD("mpr23424.5", 0x2000000, 0x0800000, CRC(f4404000) SHA1(e49d941e47e63bb7f3fddc3c3d2c1653611914ee) )
|
||||
ROM_LOAD("mpr23425.6", 0x2800000, 0x0800000, CRC(47f51da2) SHA1(af5ecd460114caed3a00157ffd3a2df0fbf348c0) )
|
||||
ROM_LOAD("mpr23426.7", 0x3000000, 0x0800000, CRC(7f91b13f) SHA1(2d534f77291ebfedc011bf0e803a1b9243fb477f) )
|
||||
ROM_LOAD("mpr23427.8", 0x3800000, 0x0800000, CRC(5851d525) SHA1(1cb1073542d75a3bcc0d363ed31d49bcaf1fd494) )
|
||||
ROM_END
|
||||
|
||||
/*
|
||||
@ -1482,50 +1618,46 @@ ROM_START( vs2_2k )
|
||||
ROM_REGION( 0x200000, REGION_CPU1, 0)
|
||||
NAOMI_BIOS
|
||||
|
||||
ROM_REGION( 0x400000, REGION_USER1, 0)
|
||||
ROM_REGION( 0x8000000, REGION_USER1, 0)
|
||||
ROM_LOAD("epr21929c.22", 0x0000000, 0x0400000, CRC(b5e609f4) SHA1(92b98bad94268a80f6e4506b812d01c0a7850161) )
|
||||
|
||||
ROM_REGION( 0x7400000, REGION_USER2, 0)
|
||||
ROM_LOAD("mpr21914.u1", 0x0000000, 0x0800000, CRC(f91ef69b) SHA1(4ed23091efad7ddf1878a0bfcdcbba3cf151af84) )
|
||||
ROM_LOAD("mpr21915.u2", 0x0800000, 0x0800000, CRC(40128a67) SHA1(9d191c4ec33465f29bbc09491dde62f354a9ab15) )
|
||||
ROM_LOAD("mpr21916.u3", 0x1000000, 0x0800000, CRC(19708b3c) SHA1(7d1ef995ce870ffcb68f420a571efb084f5bfcf2) )
|
||||
ROM_LOAD("mpr21917.u4", 0x1800000, 0x0800000, CRC(b082379b) SHA1(42f585279da1de7e613e42b76e1b81986c48e6ea) )
|
||||
ROM_LOAD("mpr21918.u5", 0x2000000, 0x0800000, CRC(a3bc1a47) SHA1(0e5043ab6e118feb59f68c84c095cf5b1dba7d09) )
|
||||
ROM_LOAD("mpr21919.u6", 0x2800000, 0x0800000, CRC(b1dfada7) SHA1(b4c906bc96b615975f6319a1fdbd5b990e7e4124) )
|
||||
ROM_LOAD("mpr21920.u7", 0x3000000, 0x0800000, CRC(1c189e28) SHA1(93400de2cb803357fa17ae7e1a5297177f9bcfa1) )
|
||||
ROM_LOAD("mpr21921.u8", 0x3800000, 0x0800000, CRC(55bcb652) SHA1(4de2e7e584dd4999dc8e405837a18a904dfee0bf) )
|
||||
ROM_LOAD("mpr21922.u9", 0x4000000, 0x0800000, CRC(2ecda3ff) SHA1(54afc77a01470662d580f5676b4e8dc4d04f63f8) )
|
||||
ROM_LOAD("mpr21923.u10",0x4800000, 0x0800000, CRC(a5cd42ad) SHA1(59f62e995d45311b1592434d1ffa42c261fa8ba1) )
|
||||
ROM_LOAD("mpr21924.u11",0x5000000, 0x0800000, CRC(cc1a4ed9) SHA1(0e3aaeaa55f1d145fb4877b6d187a3ee78cf214e) )
|
||||
ROM_LOAD("mpr21925.u12",0x5800000, 0x0800000, CRC(9452c5fb) SHA1(5a04f96d83cca6248f513de0c6240fc671bcadf9) )
|
||||
ROM_LOAD("mpr21926.u13",0x6000000, 0x0800000, CRC(d6346491) SHA1(830971cbc14cab022a09ad4c6e11ee49c550e308) )
|
||||
ROM_LOAD("mpr21927.u14",0x6800000, 0x0800000, CRC(a1901e1e) SHA1(2281f91ac696cc14886bcdf4b0685ce2f5bb8117) )
|
||||
ROM_LOAD("mpr21928.u15",0x7000000, 0x0400000, CRC(d127d9a5) SHA1(78c95357344ea15469b84fa8b1332e76521892cd) )
|
||||
ROM_LOAD("mpr21914.u1", 0x0800000, 0x0800000, CRC(f91ef69b) SHA1(4ed23091efad7ddf1878a0bfcdcbba3cf151af84) )
|
||||
ROM_LOAD("mpr21915.u2", 0x1000000, 0x0800000, CRC(40128a67) SHA1(9d191c4ec33465f29bbc09491dde62f354a9ab15) )
|
||||
ROM_LOAD("mpr21916.u3", 0x1800000, 0x0800000, CRC(19708b3c) SHA1(7d1ef995ce870ffcb68f420a571efb084f5bfcf2) )
|
||||
ROM_LOAD("mpr21917.u4", 0x2000000, 0x0800000, CRC(b082379b) SHA1(42f585279da1de7e613e42b76e1b81986c48e6ea) )
|
||||
ROM_LOAD("mpr21918.u5", 0x2800000, 0x0800000, CRC(a3bc1a47) SHA1(0e5043ab6e118feb59f68c84c095cf5b1dba7d09) )
|
||||
ROM_LOAD("mpr21919.u6", 0x3000000, 0x0800000, CRC(b1dfada7) SHA1(b4c906bc96b615975f6319a1fdbd5b990e7e4124) )
|
||||
ROM_LOAD("mpr21920.u7", 0x3800000, 0x0800000, CRC(1c189e28) SHA1(93400de2cb803357fa17ae7e1a5297177f9bcfa1) )
|
||||
ROM_LOAD("mpr21921.u8", 0x4000000, 0x0800000, CRC(55bcb652) SHA1(4de2e7e584dd4999dc8e405837a18a904dfee0bf) )
|
||||
ROM_LOAD("mpr21922.u9", 0x4800000, 0x0800000, CRC(2ecda3ff) SHA1(54afc77a01470662d580f5676b4e8dc4d04f63f8) )
|
||||
ROM_LOAD("mpr21923.u10",0x5000000, 0x0800000, CRC(a5cd42ad) SHA1(59f62e995d45311b1592434d1ffa42c261fa8ba1) )
|
||||
ROM_LOAD("mpr21924.u11",0x5800000, 0x0800000, CRC(cc1a4ed9) SHA1(0e3aaeaa55f1d145fb4877b6d187a3ee78cf214e) )
|
||||
ROM_LOAD("mpr21925.u12",0x6000000, 0x0800000, CRC(9452c5fb) SHA1(5a04f96d83cca6248f513de0c6240fc671bcadf9) )
|
||||
ROM_LOAD("mpr21926.u13",0x6800000, 0x0800000, CRC(d6346491) SHA1(830971cbc14cab022a09ad4c6e11ee49c550e308) )
|
||||
ROM_LOAD("mpr21927.u14",0x7000000, 0x0800000, CRC(a1901e1e) SHA1(2281f91ac696cc14886bcdf4b0685ce2f5bb8117) )
|
||||
ROM_LOAD("mpr21928.u15",0x7800000, 0x0400000, CRC(d127d9a5) SHA1(78c95357344ea15469b84fa8b1332e76521892cd) )
|
||||
ROM_END
|
||||
|
||||
ROM_START( vs2_2ka )
|
||||
ROM_REGION( 0x200000, REGION_CPU1, 0)
|
||||
NAOMI_BIOS
|
||||
|
||||
ROM_REGION( 0x400000, REGION_USER1, 0)
|
||||
ROM_REGION( 0x8000000, REGION_USER1, 0)
|
||||
ROM_LOAD("u22", 0x0000000, 0x0400000, CRC(831af08a) SHA1(af4c74623be823fd061765cede354c6a9722fd10) )
|
||||
|
||||
ROM_REGION( 0x7400000, REGION_USER2, 0)
|
||||
ROM_LOAD("mpr21914.u1", 0x0000000, 0x0800000, CRC(f91ef69b) SHA1(4ed23091efad7ddf1878a0bfcdcbba3cf151af84) )
|
||||
ROM_LOAD("mpr21915.u2", 0x0800000, 0x0800000, CRC(40128a67) SHA1(9d191c4ec33465f29bbc09491dde62f354a9ab15) )
|
||||
ROM_LOAD("mpr21916.u3", 0x1000000, 0x0800000, CRC(19708b3c) SHA1(7d1ef995ce870ffcb68f420a571efb084f5bfcf2) )
|
||||
ROM_LOAD("mpr21917.u4", 0x1800000, 0x0800000, CRC(b082379b) SHA1(42f585279da1de7e613e42b76e1b81986c48e6ea) )
|
||||
ROM_LOAD("mpr21918.u5", 0x2000000, 0x0800000, CRC(a3bc1a47) SHA1(0e5043ab6e118feb59f68c84c095cf5b1dba7d09) )
|
||||
ROM_LOAD("mpr21919.u6", 0x2800000, 0x0800000, CRC(b1dfada7) SHA1(b4c906bc96b615975f6319a1fdbd5b990e7e4124) )
|
||||
ROM_LOAD("mpr21920.u7", 0x3000000, 0x0800000, CRC(1c189e28) SHA1(93400de2cb803357fa17ae7e1a5297177f9bcfa1) )
|
||||
ROM_LOAD("mpr21921.u8", 0x3800000, 0x0800000, CRC(55bcb652) SHA1(4de2e7e584dd4999dc8e405837a18a904dfee0bf) )
|
||||
ROM_LOAD("mpr21922.u9", 0x4000000, 0x0800000, CRC(2ecda3ff) SHA1(54afc77a01470662d580f5676b4e8dc4d04f63f8) )
|
||||
ROM_LOAD("mpr21923.u10",0x4800000, 0x0800000, CRC(a5cd42ad) SHA1(59f62e995d45311b1592434d1ffa42c261fa8ba1) )
|
||||
ROM_LOAD("mpr21924.u11",0x5000000, 0x0800000, CRC(cc1a4ed9) SHA1(0e3aaeaa55f1d145fb4877b6d187a3ee78cf214e) )
|
||||
ROM_LOAD("mpr21925.u12",0x5800000, 0x0800000, CRC(9452c5fb) SHA1(5a04f96d83cca6248f513de0c6240fc671bcadf9) )
|
||||
ROM_LOAD("mpr21926.u13",0x6000000, 0x0800000, CRC(d6346491) SHA1(830971cbc14cab022a09ad4c6e11ee49c550e308) )
|
||||
ROM_LOAD("mpr21927.u14",0x6800000, 0x0800000, CRC(a1901e1e) SHA1(2281f91ac696cc14886bcdf4b0685ce2f5bb8117) )
|
||||
ROM_LOAD("mpr21928.u15",0x7000000, 0x0400000, CRC(d127d9a5) SHA1(78c95357344ea15469b84fa8b1332e76521892cd) )
|
||||
ROM_LOAD("mpr21914.u1", 0x0800000, 0x0800000, CRC(f91ef69b) SHA1(4ed23091efad7ddf1878a0bfcdcbba3cf151af84) )
|
||||
ROM_LOAD("mpr21915.u2", 0x1000000, 0x0800000, CRC(40128a67) SHA1(9d191c4ec33465f29bbc09491dde62f354a9ab15) )
|
||||
ROM_LOAD("mpr21916.u3", 0x1800000, 0x0800000, CRC(19708b3c) SHA1(7d1ef995ce870ffcb68f420a571efb084f5bfcf2) )
|
||||
ROM_LOAD("mpr21917.u4", 0x2000000, 0x0800000, CRC(b082379b) SHA1(42f585279da1de7e613e42b76e1b81986c48e6ea) )
|
||||
ROM_LOAD("mpr21918.u5", 0x2800000, 0x0800000, CRC(a3bc1a47) SHA1(0e5043ab6e118feb59f68c84c095cf5b1dba7d09) )
|
||||
ROM_LOAD("mpr21919.u6", 0x3000000, 0x0800000, CRC(b1dfada7) SHA1(b4c906bc96b615975f6319a1fdbd5b990e7e4124) )
|
||||
ROM_LOAD("mpr21920.u7", 0x3800000, 0x0800000, CRC(1c189e28) SHA1(93400de2cb803357fa17ae7e1a5297177f9bcfa1) )
|
||||
ROM_LOAD("mpr21921.u8", 0x4000000, 0x0800000, CRC(55bcb652) SHA1(4de2e7e584dd4999dc8e405837a18a904dfee0bf) )
|
||||
ROM_LOAD("mpr21922.u9", 0x4800000, 0x0800000, CRC(2ecda3ff) SHA1(54afc77a01470662d580f5676b4e8dc4d04f63f8) )
|
||||
ROM_LOAD("mpr21923.u10",0x5000000, 0x0800000, CRC(a5cd42ad) SHA1(59f62e995d45311b1592434d1ffa42c261fa8ba1) )
|
||||
ROM_LOAD("mpr21924.u11",0x5800000, 0x0800000, CRC(cc1a4ed9) SHA1(0e3aaeaa55f1d145fb4877b6d187a3ee78cf214e) )
|
||||
ROM_LOAD("mpr21925.u12",0x6000000, 0x0800000, CRC(9452c5fb) SHA1(5a04f96d83cca6248f513de0c6240fc671bcadf9) )
|
||||
ROM_LOAD("mpr21926.u13",0x6800000, 0x0800000, CRC(d6346491) SHA1(830971cbc14cab022a09ad4c6e11ee49c550e308) )
|
||||
ROM_LOAD("mpr21927.u14",0x7000000, 0x0800000, CRC(a1901e1e) SHA1(2281f91ac696cc14886bcdf4b0685ce2f5bb8117) )
|
||||
ROM_LOAD("mpr21928.u15",0x7800000, 0x0400000, CRC(d127d9a5) SHA1(78c95357344ea15469b84fa8b1332e76521892cd) )
|
||||
ROM_END
|
||||
|
||||
/*
|
||||
|
||||
@ -30,6 +30,37 @@ MACHINE_RESET( dc );
|
||||
|
||||
void dc_vblank( void );
|
||||
|
||||
int compute_interrupt_level(void);
|
||||
void update_interrupt_status(void);
|
||||
|
||||
extern UINT32 sysctrl_regs[0x200/4];
|
||||
|
||||
/*address*/
|
||||
#define SB_C2DSTAT ((0x005F6800-0x005F6800)/4)
|
||||
#define SB_C2DLEN ((0x005F6804-0x005F6800)/4)
|
||||
#define SB_C2DST ((0x005F6808-0x005F6800)/4)
|
||||
#define SB_SBREV ((0x005F689c-0x005F6800)/4)
|
||||
#define SB_ISTNRM ((0x005F6900-0x005F6800)/4)
|
||||
#define SB_ISTEXT ((0x005F6904-0x005F6800)/4)
|
||||
#define SB_ISTERR ((0x005F6908-0x005F6800)/4)
|
||||
#define SB_IML2NRM ((0x005F6910-0x005F6800)/4)
|
||||
#define SB_IML2EXT ((0x005F6914-0x005F6800)/4)
|
||||
#define SB_IML2ERR ((0x005F6918-0x005F6800)/4)
|
||||
#define SB_IML4NRM ((0x005F6920-0x005F6800)/4)
|
||||
#define SB_IML4EXT ((0x005F6924-0x005F6800)/4)
|
||||
#define SB_IML4ERR ((0x005F6928-0x005F6800)/4)
|
||||
#define SB_IML6NRM ((0x005F6930-0x005F6800)/4)
|
||||
#define SB_IML6EXT ((0x005F6934-0x005F6800)/4)
|
||||
#define SB_IML6ERR ((0x005F6938-0x005F6800)/4)
|
||||
|
||||
|
||||
/*address*/
|
||||
#define SB_MDSTAR ((0x005F6C04-0x005F6C00)/4)
|
||||
#define SB_MDST ((0x005F6C18-0x005F6C00)/4)
|
||||
#define SB_MDTSEL ((0x005F6C10-0x005F6C00)/4)
|
||||
#define SB_MSYS ((0x005F6C80-0x005F6C00)/4)
|
||||
|
||||
|
||||
/*----------- defined in video/dc.c -----------*/
|
||||
|
||||
READ64_HANDLER( pvr_ctrl_r );
|
||||
@ -41,4 +72,15 @@ WRITE64_HANDLER( ta_fifo_yuv_w );
|
||||
VIDEO_START(dc);
|
||||
VIDEO_UPDATE(dc);
|
||||
|
||||
/*address*/
|
||||
#define PVRID ((0x005F8000-0x005F8000)/4)
|
||||
#define REVISION ((0x005F8004-0x005F8000)/4)
|
||||
#define SOFTRESET ((0x005F8008-0x005F8000)/4)
|
||||
#define STARTRENDER ((0x005F8014-0x005F8000)/4)
|
||||
#define VO_BORDER_COL ((0x005F8040-0x005F8000)/4)
|
||||
#define VO_CONTROL ((0x005F80E8-0x005F8000)/4)
|
||||
#define SPG_STATUS ((0x005F810c-0x005F8000)/4)
|
||||
#define TA_LIST_INIT ((0x005F8144-0x005F8000)/4)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
#include "mamecore.h"
|
||||
#include "driver.h"
|
||||
#include "dc.h"
|
||||
#include "cpu/sh4/sh4.h"
|
||||
|
||||
#define DEBUG_REGISTERS (1)
|
||||
|
||||
@ -115,8 +116,15 @@ enum
|
||||
MAPLE_STATUS = 0x21,
|
||||
};
|
||||
|
||||
static UINT32 sysctrl_regs[0x200/4];
|
||||
UINT32 sysctrl_regs[0x200/4];
|
||||
static UINT32 maple_regs[0x100/4];
|
||||
static UINT32 dc_rtcregister[4];
|
||||
|
||||
static UINT32 maple0x82answer[]=
|
||||
{
|
||||
0x07200083,0x2d353133,0x39343136,0x20202020,0x59504f43,0x48474952,0x45532054,0x45204147,
|
||||
0x05200083,0x5245544e,0x53495250,0x43205345,0x544c2c4f,0x20202e44,0x38393931,0x5c525043
|
||||
};
|
||||
|
||||
// register decode helper
|
||||
|
||||
@ -126,6 +134,12 @@ INLINE int decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
|
||||
|
||||
*shift = 0;
|
||||
|
||||
// non 32-bit accesses have not yet been seen here, we need to know when they are
|
||||
if ((mem_mask != U64(0x00000000ffffffff)) && (mem_mask != U64(0xffffffff00000000)))
|
||||
{
|
||||
assert_always(0, "Wrong mask!\n");
|
||||
}
|
||||
|
||||
if (mem_mask == U64(0x00000000ffffffff))
|
||||
{
|
||||
reg++;
|
||||
@ -135,7 +149,62 @@ INLINE int decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
|
||||
return reg;
|
||||
}
|
||||
|
||||
// I/O functions
|
||||
int compute_interrupt_level(void)
|
||||
{
|
||||
UINT32 ln,lx,le;
|
||||
|
||||
ln=sysctrl_regs[SB_ISTNRM] & sysctrl_regs[SB_IML6NRM];
|
||||
lx=sysctrl_regs[SB_ISTEXT] & sysctrl_regs[SB_IML6EXT];
|
||||
le=sysctrl_regs[SB_ISTERR] & sysctrl_regs[SB_IML6ERR];
|
||||
if (ln | lx | le)
|
||||
{
|
||||
return 6;
|
||||
}
|
||||
|
||||
ln=sysctrl_regs[SB_ISTNRM] & sysctrl_regs[SB_IML4NRM];
|
||||
lx=sysctrl_regs[SB_ISTEXT] & sysctrl_regs[SB_IML4EXT];
|
||||
le=sysctrl_regs[SB_ISTERR] & sysctrl_regs[SB_IML4ERR];
|
||||
if (ln | lx | le)
|
||||
{
|
||||
return 4;
|
||||
}
|
||||
|
||||
ln=sysctrl_regs[SB_ISTNRM] & sysctrl_regs[SB_IML2NRM];
|
||||
lx=sysctrl_regs[SB_ISTEXT] & sysctrl_regs[SB_IML2EXT];
|
||||
le=sysctrl_regs[SB_ISTERR] & sysctrl_regs[SB_IML2ERR];
|
||||
if (ln | lx | le)
|
||||
{
|
||||
return 2;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void update_interrupt_status(void)
|
||||
{
|
||||
int level;
|
||||
|
||||
if (sysctrl_regs[SB_ISTERR])
|
||||
{
|
||||
sysctrl_regs[SB_ISTNRM] |= 0x80000000;
|
||||
}
|
||||
else
|
||||
{
|
||||
sysctrl_regs[SB_ISTNRM] &= 0x7fffffff;
|
||||
}
|
||||
|
||||
if (sysctrl_regs[SB_ISTEXT])
|
||||
{
|
||||
sysctrl_regs[SB_ISTNRM] |= 0x40000000;
|
||||
}
|
||||
else
|
||||
{
|
||||
sysctrl_regs[SB_ISTNRM] &= 0xbfffffff;
|
||||
}
|
||||
|
||||
level=compute_interrupt_level();
|
||||
cpunum_set_info_int(0,CPUINFO_INT_SH4_IRLn_INPUT,15-level);
|
||||
}
|
||||
|
||||
READ64_HANDLER( dc_sysctrl_r )
|
||||
{
|
||||
@ -145,7 +214,10 @@ READ64_HANDLER( dc_sysctrl_r )
|
||||
reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
|
||||
#if DEBUG_SYSCTRL
|
||||
mame_printf_verbose("SYSCTRL: read %x @ %x (reg %x: %s), mask %llx (PC=%x)\n", sysctrl_regs[reg], offset, reg, sysctrl_names[reg], mem_mask, activecpu_get_pc());
|
||||
if ((reg != 0x40) && (reg != 0x42)) // filter out IRQ status reads
|
||||
{
|
||||
mame_printf_verbose("SYSCTRL: read %x @ %x (reg %x: %s), mask %llx (PC=%x)\n", sysctrl_regs[reg], offset, reg, sysctrl_names[reg], mem_mask, activecpu_get_pc());
|
||||
}
|
||||
#endif
|
||||
|
||||
return (UINT64)sysctrl_regs[reg] << shift;
|
||||
@ -155,14 +227,49 @@ WRITE64_HANDLER( dc_sysctrl_w )
|
||||
{
|
||||
int reg;
|
||||
UINT64 shift;
|
||||
UINT32 old,dat;
|
||||
struct sh4_ddt_dma ddtdata;
|
||||
|
||||
reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
dat = (UINT32)(data >> shift);
|
||||
old = sysctrl_regs[reg];
|
||||
sysctrl_regs[reg] = dat; // 5f6800+off*4=dat
|
||||
switch (reg)
|
||||
{
|
||||
case SB_C2DST:
|
||||
ddtdata.destination=sysctrl_regs[SB_C2DSTAT];
|
||||
ddtdata.length=sysctrl_regs[SB_C2DLEN];
|
||||
ddtdata.size=1;
|
||||
ddtdata.direction=0;
|
||||
ddtdata.channel=2;
|
||||
ddtdata.mode=25; //011001
|
||||
cpunum_set_info_ptr(0,CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
|
||||
sysctrl_regs[SB_C2DSTAT]=sysctrl_regs[SB_C2DSTAT]+ddtdata.length;
|
||||
sysctrl_regs[SB_C2DLEN]=0;
|
||||
sysctrl_regs[SB_C2DST]=0;
|
||||
sysctrl_regs[SB_ISTNRM] |= (1 << 19);
|
||||
break;
|
||||
|
||||
case SB_ISTNRM:
|
||||
sysctrl_regs[SB_ISTNRM] = old & ~(dat | 0xC0000000); // bits 31,30 ro
|
||||
break;
|
||||
|
||||
case SB_ISTEXT:
|
||||
sysctrl_regs[SB_ISTEXT] = old;
|
||||
break;
|
||||
|
||||
case SB_ISTERR:
|
||||
sysctrl_regs[SB_ISTERR] = old & ~dat;
|
||||
break;
|
||||
}
|
||||
update_interrupt_status();
|
||||
|
||||
#if DEBUG_SYSCTRL
|
||||
mame_printf_verbose("SYSCTRL: write %llx to %x (reg %x: %s), mask %llx\n", data>>shift, offset, reg, sysctrl_names[reg], mem_mask);
|
||||
if ((reg != 0x40) && (reg != 0x42)) // filter out IRQ acks
|
||||
{
|
||||
mame_printf_verbose("SYSCTRL: write %llx to %x (reg %x: %s), mask %llx\n", data>>shift, offset, reg, sysctrl_names[reg], mem_mask);
|
||||
}
|
||||
#endif
|
||||
|
||||
sysctrl_regs[reg] |= data >> shift;
|
||||
}
|
||||
|
||||
READ64_HANDLER( dc_maple_r )
|
||||
@ -179,23 +286,220 @@ WRITE64_HANDLER( dc_maple_w )
|
||||
{
|
||||
int reg;
|
||||
UINT64 shift;
|
||||
UINT32 old,dat;
|
||||
struct sh4_ddt_dma ddtdata;
|
||||
UINT32 buff[512];
|
||||
UINT32 endflag,port,pattern,length,command,dap,sap,destination;
|
||||
int chk;
|
||||
int a;
|
||||
|
||||
reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
dat = (UINT32)(data >> shift);
|
||||
old = maple_regs[reg];
|
||||
|
||||
#if DEBUG_MAPLE
|
||||
mame_printf_verbose("MAPLE: write %llx to %x (reg %x: %s), mask %llx\n", data >> shift, offset, reg, maple_names[reg], mem_mask);
|
||||
#endif
|
||||
|
||||
maple_regs[reg] |= data >> shift;
|
||||
maple_regs[reg] = dat; // 5f6c00+reg*4=dat
|
||||
switch (reg)
|
||||
{
|
||||
case SB_MDST:
|
||||
maple_regs[reg] = old;
|
||||
if (!(old & 1) && (dat & 1)) // 0 -> 1
|
||||
{
|
||||
if (!(maple_regs[SB_MDTSEL] & 1))
|
||||
{
|
||||
maple_regs[reg] = 1;
|
||||
dat=maple_regs[SB_MDSTAR];
|
||||
while (1) // do transfers
|
||||
{
|
||||
ddtdata.source=dat;
|
||||
ddtdata.length=3;
|
||||
ddtdata.size=4;
|
||||
ddtdata.buffer=buff;
|
||||
ddtdata.direction=0;
|
||||
ddtdata.channel= -1;
|
||||
ddtdata.mode= -1;
|
||||
cpunum_set_info_ptr(0, CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA, &ddtdata);
|
||||
|
||||
maple_regs[reg] = 0;
|
||||
endflag=buff[0] & 0x80000000;
|
||||
port=(buff[0] >> 16) & 3;
|
||||
pattern=(buff[0] >> 8) & 7;
|
||||
length=buff[0] & 255;
|
||||
destination=buff[1];
|
||||
command=buff[2] & 255;
|
||||
dap=(buff[2] >> 8) & 255;
|
||||
sap=(buff[2] >> 16) & 255;
|
||||
buff[0]=0;
|
||||
ddtdata.size=4;
|
||||
|
||||
if (pattern == 0)
|
||||
{
|
||||
switch (command)
|
||||
{
|
||||
case 1:
|
||||
ddtdata.length=1;
|
||||
break;
|
||||
case 3:
|
||||
ddtdata.length=1;
|
||||
break;
|
||||
case 0x80: // compute checksum
|
||||
ddtdata.length=length;
|
||||
ddtdata.direction=0;
|
||||
ddtdata.channel= -1;
|
||||
ddtdata.mode=-1;
|
||||
cpunum_set_info_ptr(0,CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
|
||||
chk=0;
|
||||
for (a=1;a < length;a++)
|
||||
{
|
||||
chk=chk+(signed char)(buff[a] & 255);
|
||||
chk=chk+(signed char)((buff[a] >> 8) & 255);
|
||||
chk=chk+(signed char)((buff[a] >> 16) & 255);
|
||||
chk=chk+(signed char)((buff[a] >> 24) & 255);
|
||||
}
|
||||
chk=chk+(buff[0] & 255);
|
||||
chk=chk+((buff[0] >> 8) & 255);
|
||||
chk=chk+((buff[0] >> 16) & 255);
|
||||
chk=chk+((buff[0] >> 24) & 255);
|
||||
buff[1]=chk;
|
||||
ddtdata.length=2;
|
||||
break;
|
||||
case 0x82: // get license string
|
||||
for (a=0;a < 16;a++)
|
||||
{
|
||||
buff[a]=maple0x82answer[a];
|
||||
}
|
||||
ddtdata.length=16;
|
||||
break;
|
||||
case 0x86:
|
||||
ddtdata.length=length;
|
||||
ddtdata.direction=0;
|
||||
ddtdata.channel= -1;
|
||||
ddtdata.mode=-1;
|
||||
cpunum_set_info_ptr(0,CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
|
||||
|
||||
if ((buff[0] & 0xff) == 3)
|
||||
{
|
||||
buff[1]=0x14131211;
|
||||
for (a=0;a < 31;a++)
|
||||
{
|
||||
buff[2+a]=buff[1+a]+0x04040404;
|
||||
}
|
||||
buff[1]=0x1413b1b9; // put checksum
|
||||
buff[5]=0x8ab82221; // put checksum
|
||||
ddtdata.length=0x84/4;
|
||||
}
|
||||
else if (((buff[0] & 0xff) == 0x31) || ((buff[0] & 0xff) == 0xb) || ((buff[0] & 0xff) == 0x1))
|
||||
{
|
||||
ddtdata.length=1;
|
||||
}
|
||||
else if ((buff[0] & 0xff) == 0x17) // send command into jvs serial bus !!!
|
||||
{
|
||||
// 17,*c295407 (77),*c295404,*c295405,*c295406,0,ff,2,f0,d9, 0
|
||||
// 17,*c295407 (77),*c295404,*c295405,*c295406,0,ff,2,f1,01, 0
|
||||
// 17,*c295407 (77),*c295404,*c295405,*c295406,0,01,1,10, 01,0
|
||||
switch (buff[2] & 0xff) // jvs command
|
||||
{
|
||||
case 0xf0:
|
||||
case 0xf1:
|
||||
case 0x10:
|
||||
break;
|
||||
}
|
||||
buff[1]=0xe4e3e2e1;
|
||||
ddtdata.length=2;
|
||||
}
|
||||
else if ((buff[0] & 0xff) == 0x15)
|
||||
{
|
||||
// 15,0,0,0
|
||||
buff[1]=0xA4A3A2A1;
|
||||
for (a=0;a < 7;a++)
|
||||
{
|
||||
buff[2+a]=buff[1+a]+0x04040404;
|
||||
}
|
||||
buff[1]=buff[1] | 0x0c000000;
|
||||
buff[2]=buff[2] & 0xFFCFFFFF;
|
||||
|
||||
a=readinputport(0); // mettere qui tasti
|
||||
buff[2]=buff[2] | (a << 20);
|
||||
*(((unsigned char *)buff)+0x18)=0;
|
||||
*(((unsigned char *)buff)+0x1d)=1;
|
||||
*(((unsigned char *)buff)+0x16)=0x8e;
|
||||
ddtdata.length=9;
|
||||
}
|
||||
else if ((buff[0] & 0xff) == 0x21)
|
||||
{
|
||||
// 21,*c295407 (77),*c295404,*c295405,*c295406,0,1,0
|
||||
ddtdata.length=1;
|
||||
}
|
||||
else //0x27
|
||||
{
|
||||
ddtdata.length=1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
ddtdata.destination=destination;
|
||||
ddtdata.buffer=buff;
|
||||
ddtdata.direction=1;
|
||||
cpunum_set_info_ptr(0,CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
|
||||
|
||||
if (endflag)
|
||||
{
|
||||
break;
|
||||
}
|
||||
// skip fixed packet header
|
||||
dat += 8;
|
||||
// skip transfer data
|
||||
dat += ((command & 0xff) + 1) * 4;
|
||||
} // do transfers
|
||||
maple_regs[reg] = 0;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
#if DEBUG_MAPLE
|
||||
mame_printf_verbose("MAPLE: write %llx to %x, mask %llx\n", data, offset, mem_mask);
|
||||
#endif
|
||||
}
|
||||
|
||||
READ64_HANDLER( dc_gdrom_r )
|
||||
{
|
||||
UINT32 off;
|
||||
|
||||
if ((int)mem_mask & 1)
|
||||
{
|
||||
off=(offset << 1) | 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
off=offset << 1;
|
||||
}
|
||||
|
||||
if (off*4 == 0x4c)
|
||||
return -1;
|
||||
if (off*4 == 8)
|
||||
return 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE64_HANDLER( dc_gdrom_w )
|
||||
{
|
||||
UINT32 dat,off;
|
||||
|
||||
if ((int)mem_mask & 1)
|
||||
{
|
||||
dat=(UINT32)(data >> 32);
|
||||
off=(offset << 1) | 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
dat=(UINT32)data;
|
||||
off=offset << 1;
|
||||
}
|
||||
|
||||
mame_printf_verbose("GDROM: write %llx to %x, mask %llx\n", data, offset, mem_mask);
|
||||
}
|
||||
|
||||
@ -236,18 +540,43 @@ READ64_HANDLER( dc_rtc_r )
|
||||
|
||||
WRITE64_HANDLER( dc_rtc_w )
|
||||
{
|
||||
UINT32 dat,off;
|
||||
UINT32 old;
|
||||
|
||||
if ((int)mem_mask & 1) {
|
||||
dat=(UINT32)(data >> 32);
|
||||
off=(offset << 1) | 1;
|
||||
} else {
|
||||
dat=(UINT32)data;
|
||||
off=offset << 1;
|
||||
}
|
||||
old = dc_rtcregister[off];
|
||||
dc_rtcregister[off] = dat & 0xFFFF; // 5f6c00+off*4=dat
|
||||
/* switch (off)
|
||||
{
|
||||
case RTC1:
|
||||
if (dc_rtcregister[RTC3])
|
||||
dc_rtcregister[RTC3] = 0;
|
||||
else
|
||||
dc_rtcregister[off] = old;
|
||||
break;
|
||||
case RTC2:
|
||||
if (dc_rtcregister[RTC3] == 0)
|
||||
dc_rtcregister[off] = old;
|
||||
break;
|
||||
case RTC3:
|
||||
dc_rtcregister[RTC3] &= 1;
|
||||
break;
|
||||
}*/
|
||||
mame_printf_verbose("RTC: write %llx to %x, mask %llx\n", data, offset, mem_mask);
|
||||
}
|
||||
|
||||
READ64_HANDLER( dc_aica_reg_r )
|
||||
/*static void dc_rtc_increment(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE64_HANDLER( dc_aica_reg_w )
|
||||
{
|
||||
mame_printf_verbose("AICA REG: write %llx to %x, mask %llx\n", data, offset, mem_mask);
|
||||
}
|
||||
dc_rtcregister[RTC2] = (dc_rtcregister[RTC2] + 1) & 0xFFFF;
|
||||
if (dc_rtcregister[RTC2] == 0)
|
||||
dc_rtcregister[RTC1] = (dc_rtcregister[RTC1] + 1) & 0xFFFF;
|
||||
}*/
|
||||
|
||||
MACHINE_RESET( dc )
|
||||
{
|
||||
@ -256,55 +585,43 @@ MACHINE_RESET( dc )
|
||||
|
||||
memset(sysctrl_regs, 0, sizeof(sysctrl_regs));
|
||||
memset(maple_regs, 0, sizeof(maple_regs));
|
||||
memset(dc_rtcregister, 0, sizeof(dc_rtcregister));
|
||||
|
||||
sysctrl_regs[0x27] = 0x00000008; // Naomi BIOS requires at least this version
|
||||
sysctrl_regs[SB_SBREV] = 0x0b;
|
||||
}
|
||||
|
||||
// called at vblank
|
||||
void dc_vblank( void )
|
||||
READ64_HANDLER( dc_aica_reg_r )
|
||||
{
|
||||
// is system control set for automatic polling on VBL?
|
||||
if ((maple_regs[MAPLE_SYSCTRL] & 0xffff0000) == 0x3a980000)
|
||||
{
|
||||
// is enabled?
|
||||
if (maple_regs[MAPLE_DMAENABLE] == 1)
|
||||
{
|
||||
// is started?
|
||||
if (maple_regs[MAPLE_DMASTART] == 1)
|
||||
{
|
||||
UINT32 cmd, dest, addr = maple_regs[MAPLE_DMACMD];
|
||||
int reg;
|
||||
UINT64 shift;
|
||||
|
||||
// process the command list
|
||||
// first word: bit 31 set = last command in list, 16-17 = port, 8-10 = pattern, 0-7 = xfer length
|
||||
// second word: destination address
|
||||
// third word: what to send to port A
|
||||
cmd = 0;
|
||||
while (!(cmd & 0x80000000))
|
||||
{
|
||||
// read command word
|
||||
cmd = program_read_dword(addr);
|
||||
reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
|
||||
dest = program_read_dword(addr+4);
|
||||
|
||||
// just indicate "no connection" for now
|
||||
program_write_dword(dest, 0);
|
||||
program_write_dword(dest+4, 0xffffffff);
|
||||
|
||||
// skip fixed packet header
|
||||
addr += 8;
|
||||
// skip transfer data
|
||||
addr += ((cmd & 0xff) + 1) * 4;
|
||||
}
|
||||
|
||||
|
||||
#if DEBUG_MAPLE
|
||||
mame_printf_verbose("MAPLE: automatic read, table @ %x\n", addr);
|
||||
#endif
|
||||
|
||||
// indicate transfer completed
|
||||
maple_regs[MAPLE_DMASTART] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
// logerror("dc_aica_reg_r: Unmapped read %08x\n", 0x700000+reg*4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE64_HANDLER( dc_aica_reg_w )
|
||||
{
|
||||
int reg;
|
||||
UINT64 shift;
|
||||
UINT32 dat;
|
||||
|
||||
reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
dat = (UINT32)(data >> shift);
|
||||
|
||||
if (reg == (0x2c00/4))
|
||||
{
|
||||
if (dat & 1)
|
||||
{
|
||||
/* halt the ARM7 */
|
||||
cpunum_set_input_line(1, INPUT_LINE_RESET, ASSERT_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* it's alive ! */
|
||||
cpunum_set_input_line(1, INPUT_LINE_RESET, CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
mame_printf_verbose("AICA REG: write %llx to %x, mask %llx\n", data, offset, mem_mask);
|
||||
}
|
||||
|
||||
@ -5,37 +5,50 @@
|
||||
|
||||
#include "driver.h"
|
||||
#include "dc.h"
|
||||
#include "cpu/sh4/sh4.h"
|
||||
|
||||
#define DEBUG_PVRCTRL (1)
|
||||
#define DEBUG_PVRTA (1)
|
||||
#define DEBUG_FIFO_POLY (0)
|
||||
#define DEBUG_PVRCTRL (0)
|
||||
#define DEBUG_PVRTA (0)
|
||||
#define DEBUG_PVRTA_REGS (0)
|
||||
#define DEBUG_PVRDLIST (0)
|
||||
|
||||
static UINT32 pvrctrl_regs[0x100/4];
|
||||
static UINT32 pvrta_regs[0x2000/4];
|
||||
|
||||
VIDEO_START(dc)
|
||||
UINT64 *dc_texture_ram;
|
||||
static UINT32 tafifo_buff[32];
|
||||
static int tafifo_pos, tafifo_mask, tafifo_vertexwords, tafifo_listtype;
|
||||
static int start_render_received;
|
||||
|
||||
struct testsprites
|
||||
{
|
||||
memset(pvrctrl_regs, 0, sizeof(pvrctrl_regs));
|
||||
memset(pvrta_regs, 0, sizeof(pvrta_regs));
|
||||
int positionx, positiony;
|
||||
int sizex, sizey;
|
||||
UINT32 textureaddress;
|
||||
float u, v, du, dv;
|
||||
int texturemode;
|
||||
int texturesizex, texturesizey, texturesizes, texturepf;
|
||||
} showsprites[2048];
|
||||
|
||||
pvrta_regs[0] = 0x17fd11db; // vendor and device ID of HOLLY chip
|
||||
pvrta_regs[1] = 1; // chip revision
|
||||
}
|
||||
|
||||
VIDEO_UPDATE(dc)
|
||||
{
|
||||
dc_vblank();
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int testsprites_size, toerasesprites;
|
||||
static UINT32 dilated0[11][1024];
|
||||
static UINT32 dilated1[11][1024];
|
||||
static int dilatechose[64];
|
||||
|
||||
// register decode helper
|
||||
|
||||
INLINE int decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
|
||||
{
|
||||
int reg = offset * 2;
|
||||
|
||||
*shift = 0;
|
||||
|
||||
// non 32-bit accesses have not yet been seen here, we need to know when they are
|
||||
if ((mem_mask != U64(0x00000000ffffffff)) && (mem_mask != U64(0xffffffff00000000)))
|
||||
{
|
||||
assert_always(0, "Wrong mask!\n");
|
||||
}
|
||||
|
||||
if (mem_mask == U64(0x00000000ffffffff))
|
||||
{
|
||||
reg++;
|
||||
@ -80,10 +93,16 @@ READ64_HANDLER( pvr_ta_r )
|
||||
|
||||
reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
|
||||
switch (reg)
|
||||
{
|
||||
case SPG_STATUS:
|
||||
pvrta_regs[reg] = (video_screen_get_vblank(0) << 13) | (video_screen_get_hblank(0) << 12) | (video_screen_get_vpos(0) & 0x3ff);
|
||||
break;
|
||||
}
|
||||
|
||||
#if DEBUG_PVRTA
|
||||
mame_printf_verbose("PVRTA: read %x @ %x (reg %x), mask %llx (PC=%x)\n", pvrta_regs[reg], offset, reg, mem_mask, activecpu_get_pc());
|
||||
#endif
|
||||
|
||||
return (UINT64)pvrta_regs[reg] << shift;
|
||||
}
|
||||
|
||||
@ -91,23 +110,410 @@ WRITE64_HANDLER( pvr_ta_w )
|
||||
{
|
||||
int reg;
|
||||
UINT64 shift;
|
||||
UINT32 old,dat;
|
||||
|
||||
reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
dat = (UINT32)(data >> shift);
|
||||
old = pvrta_regs[reg];
|
||||
pvrta_regs[reg] = dat; // 5f8000+reg*4=dat
|
||||
switch (reg)
|
||||
{
|
||||
case SOFTRESET:
|
||||
#if DEBUG_PVRTA_REGS
|
||||
if (dat & 1)
|
||||
{
|
||||
mame_printf_verbose("pvr_ta_w: TA soft reset\n");
|
||||
}
|
||||
if (dat & 2)
|
||||
{
|
||||
mame_printf_verbose("pvr_ta_w: Core Pipeline soft reset\n");
|
||||
}
|
||||
if (dat & 4)
|
||||
{
|
||||
mame_printf_verbose("pvr_ta_w: sdram I/F soft reset\n");
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
case STARTRENDER:
|
||||
start_render_received=1;
|
||||
break;
|
||||
case TA_LIST_INIT:
|
||||
tafifo_pos=0;
|
||||
tafifo_mask=7;
|
||||
tafifo_vertexwords=8;
|
||||
tafifo_listtype= -1;
|
||||
toerasesprites=1;
|
||||
break;
|
||||
}
|
||||
|
||||
#if DEBUG_PVRTA
|
||||
mame_printf_verbose("PVRTA: write %llx to %x (reg %x %x), mask %llx\n", data>>shift, offset, reg, (reg*4)+0x8000, mem_mask);
|
||||
#endif
|
||||
|
||||
pvrta_regs[reg] |= data >> shift;
|
||||
}
|
||||
|
||||
|
||||
WRITE64_HANDLER( ta_fifo_poly_w )
|
||||
{
|
||||
mame_printf_verbose("Poly FIFO: write %llx to %x, mask %llx\n", data, offset, mem_mask);
|
||||
UINT32 a;
|
||||
static UINT32 paracontrol,paratype,endofstrip,listtype;
|
||||
static UINT32 groupcontrol,groupen,striplen,userclip;
|
||||
static UINT32 objcontrol,shadow,volume,coltype,texture,offfset,gouraud,uv16bit;
|
||||
static UINT32 textureusize,texturevsize,texturesizes,textureaddress,scanorder,pixelformat;
|
||||
static UINT32 srcalphainstr,dstalphainstr,srcselect,dstselect,fogcontrol,colorclamp,usealpha;
|
||||
static UINT32 ignoretexalpha,flipuv,clampuv,filtermode,sstexture,mmdadjust,tsinstruction;
|
||||
static UINT32 depthcomparemode,cullingmode,zwritedisable,cachebypass,dcalcctrl,volumeinstruction,mipmapped,vqcompressed,strideselect;
|
||||
|
||||
if (!mem_mask) // 64 bit
|
||||
{
|
||||
tafifo_buff[tafifo_pos]=(UINT32)data;
|
||||
tafifo_buff[tafifo_pos+1]=(UINT32)(data >> 32);
|
||||
#if DEBUG_FIFO_POLY
|
||||
mame_printf_debug("ta_fifo_poly_w: Unmapped write64 %08x = %llx -> %08x %08x\n", 0x10000000+offset*8, data, tafifo_buff[tafifo_pos], tafifo_buff[tafifo_pos+1]);
|
||||
#endif
|
||||
tafifo_pos += 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
logerror("ta_fifo_poly_w: Only 64 bit writes supported!\n");
|
||||
}
|
||||
|
||||
tafifo_pos &= tafifo_mask;
|
||||
if (tafifo_pos == 0)
|
||||
{
|
||||
paracontrol=(tafifo_buff[0] >> 24) & 0xff;
|
||||
|
||||
// 0 end of list
|
||||
// 1 user tile clip
|
||||
// 2 object list set
|
||||
// 3 reserved
|
||||
// 4 polygon/modifier volume
|
||||
// 5 sprite
|
||||
// 6 reserved
|
||||
// 7 vertex
|
||||
paratype=(paracontrol >> 5) & 7;
|
||||
endofstrip=(paracontrol >> 4) & 1;
|
||||
listtype=(paracontrol >> 0) & 7;
|
||||
groupcontrol=(tafifo_buff[0] >> 16) & 0xff;
|
||||
groupen=(groupcontrol >> 7) & 1;
|
||||
striplen=(groupcontrol >> 2) & 3;
|
||||
userclip=(groupcontrol >> 0) & 3;
|
||||
objcontrol=(tafifo_buff[0] >> 0) & 0xffff;
|
||||
shadow=(objcontrol >> 7) & 1;
|
||||
volume=(objcontrol >> 6) & 1;
|
||||
coltype=(objcontrol >> 4) & 3;
|
||||
texture=(objcontrol >> 3) & 1;
|
||||
offfset=(objcontrol >> 2) & 1;
|
||||
gouraud=(objcontrol >> 1) & 1;
|
||||
uv16bit=(objcontrol >> 0) & 1;
|
||||
|
||||
if (toerasesprites == 1)
|
||||
{
|
||||
toerasesprites=0;
|
||||
testsprites_size=0;
|
||||
}
|
||||
|
||||
// check if we need 8 words more
|
||||
if (tafifo_mask == 7)
|
||||
{
|
||||
if ((paratype == 4) && (((coltype >= 2) && (offfset == 1)) || ((coltype >= 2) && (volume == 1))))
|
||||
{
|
||||
tafifo_mask = 15;
|
||||
tafifo_pos = 8;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((paratype == 7) && (tafifo_vertexwords == 16))
|
||||
{
|
||||
tafifo_mask = 15;
|
||||
tafifo_pos = 8;
|
||||
return;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tafifo_mask = 7;
|
||||
}
|
||||
|
||||
// now we heve all the needed words
|
||||
// interpret their meaning
|
||||
if (tafifo_buff[0] == 0)
|
||||
{
|
||||
a=0; // 6-10 0-3
|
||||
switch (tafifo_listtype)
|
||||
{
|
||||
case 0:
|
||||
a = 1 << 7;
|
||||
break;
|
||||
case 1:
|
||||
a = 1 << 8;
|
||||
break;
|
||||
case 2:
|
||||
a = 1 << 9;
|
||||
break;
|
||||
case 3:
|
||||
a = 1 << 10;
|
||||
break;
|
||||
case 4:
|
||||
a = 1 << 21;
|
||||
break;
|
||||
break;
|
||||
}
|
||||
sysctrl_regs[SB_ISTNRM] |= a;
|
||||
update_interrupt_status();
|
||||
tafifo_listtype= -1;
|
||||
}
|
||||
else
|
||||
{
|
||||
#if DEBUG_PVRDLIST
|
||||
mame_printf_verbose("Para Type %d End of Strip %d List Type %d\n", paratype, endofstrip, listtype);
|
||||
#endif
|
||||
|
||||
if (((paratype == 4) && (texture == 1)) || (paratype == 5))
|
||||
{
|
||||
depthcomparemode=(tafifo_buff[1] >> 29) & 7;
|
||||
cullingmode=(tafifo_buff[1] >> 27) & 3;
|
||||
zwritedisable=(tafifo_buff[1] >> 26) & 1;
|
||||
cachebypass=(tafifo_buff[1] >> 21) & 1;
|
||||
dcalcctrl=(tafifo_buff[1] >> 20) & 1;
|
||||
volumeinstruction=(tafifo_buff[1] >> 29) & 7;
|
||||
textureusize=1 << (3+((tafifo_buff[2] >> 3) & 7));
|
||||
texturevsize=1 << (3+(tafifo_buff[2] & 7));
|
||||
texturesizes=tafifo_buff[2] & 0x3f;
|
||||
srcalphainstr=(tafifo_buff[2] >> 29) & 7;
|
||||
dstalphainstr=(tafifo_buff[2] >> 26) & 7;
|
||||
srcselect=(tafifo_buff[2] >> 25) & 1;
|
||||
dstselect=(tafifo_buff[2] >> 24) & 1;
|
||||
fogcontrol=(tafifo_buff[2] >> 22) & 3;
|
||||
colorclamp=(tafifo_buff[2] >> 21) & 1;
|
||||
usealpha=(tafifo_buff[2] >> 20) & 1;
|
||||
ignoretexalpha=(tafifo_buff[2] >> 19) & 1;
|
||||
flipuv=(tafifo_buff[2] >> 17) & 3;
|
||||
clampuv=(tafifo_buff[2] >> 15) & 3;
|
||||
filtermode=(tafifo_buff[2] >> 13) & 3;
|
||||
sstexture=(tafifo_buff[2] >> 12) & 1;
|
||||
mmdadjust=(tafifo_buff[2] >> 8) & 1;
|
||||
tsinstruction=(tafifo_buff[2] >> 6) & 3;
|
||||
textureaddress=(tafifo_buff[3] & 0x1FFFFF) << 3;
|
||||
scanorder=(tafifo_buff[3] >> 26) & 1;
|
||||
pixelformat=(tafifo_buff[3] >> 27) & 7;
|
||||
mipmapped=(tafifo_buff[3] >> 31) & 1;
|
||||
vqcompressed=(tafifo_buff[3] >> 30) & 1;
|
||||
strideselect=(tafifo_buff[3] >> 25) & 1;
|
||||
|
||||
#if DEBUG_PVRDLIST
|
||||
mame_printf_verbose(" Texture %d x %d at %08x format %d\n", textureusize, texturevsize, (tafifo_buff[3] & 0x1FFFFF) << 3, pixelformat);
|
||||
#endif
|
||||
}
|
||||
|
||||
if (paratype == 7)
|
||||
{ // vertex
|
||||
#if DEBUG_PVRDLIST
|
||||
mame_printf_verbose(" test vertex ");
|
||||
for (a=1; a <= 11; a++)
|
||||
{
|
||||
mame_printf_verbose(" %e", u2f(tafifo_buff[a]));
|
||||
}
|
||||
mame_printf_verbose("\n");
|
||||
mame_printf_verbose(" %e %e %e %e %e %e\n",u2f(tafifo_buff[13] & 0xffff0000),u2f((tafifo_buff[13] & 0xffff) << 16),u2f(tafifo_buff[14] & 0xffff0000),u2f((tafifo_buff[14] & 0xffff) << 16),u2f(tafifo_buff[15] & 0xffff0000),u2f((tafifo_buff[15] & 0xffff) << 16));
|
||||
#endif
|
||||
/* test video start */
|
||||
// pixely=u2f((tafifo_buff[13] & 0xffff) << 16)*1024
|
||||
showsprites[testsprites_size].positionx=u2f(tafifo_buff[1]);
|
||||
showsprites[testsprites_size].positiony=u2f(tafifo_buff[2]);
|
||||
showsprites[testsprites_size].sizex=u2f(tafifo_buff[4])-u2f(tafifo_buff[1]);
|
||||
showsprites[testsprites_size].sizey=u2f(tafifo_buff[8])-u2f(tafifo_buff[2]);
|
||||
showsprites[testsprites_size].u=u2f(tafifo_buff[13] & 0xffff0000);
|
||||
showsprites[testsprites_size].v=u2f((tafifo_buff[13] & 0xffff) << 16);
|
||||
showsprites[testsprites_size].du=u2f(tafifo_buff[14] & 0xffff0000)-showsprites[testsprites_size].u;
|
||||
showsprites[testsprites_size].dv=u2f((tafifo_buff[15] & 0xffff) << 16)-showsprites[testsprites_size].v;
|
||||
showsprites[testsprites_size].textureaddress=textureaddress;
|
||||
showsprites[testsprites_size].texturesizex=textureusize;
|
||||
showsprites[testsprites_size].texturesizey=texturevsize;
|
||||
showsprites[testsprites_size].texturemode=scanorder;
|
||||
showsprites[testsprites_size].texturesizes=texturesizes;
|
||||
showsprites[testsprites_size].texturepf=pixelformat;
|
||||
testsprites_size=testsprites_size+1;
|
||||
/* test video end */
|
||||
}
|
||||
|
||||
if (paratype != 7)
|
||||
{
|
||||
tafifo_vertexwords=8;
|
||||
}
|
||||
if (((paratype == 4) && ((texture == 1) || (coltype == 1))) || (paratype == 5))
|
||||
{
|
||||
tafifo_vertexwords=16;
|
||||
}
|
||||
if ((paratype == 4) || (paratype == 5) || (paratype == 6))
|
||||
{
|
||||
if (tafifo_listtype < 0)
|
||||
{
|
||||
tafifo_listtype = listtype;
|
||||
}
|
||||
}
|
||||
}
|
||||
} // if (tafifo_pos == 0)
|
||||
}
|
||||
|
||||
WRITE64_HANDLER( ta_fifo_yuv_w )
|
||||
{
|
||||
mame_printf_verbose("YUV FIFO: write %llx to %x, mask %llx\n", data, offset, mem_mask);
|
||||
}
|
||||
|
||||
/* test video start */
|
||||
UINT32 dilate0(UINT32 value,int bits) // dilate first "bits" bits in "value"
|
||||
{
|
||||
UINT32 x,m1,m2,m3;
|
||||
int a;
|
||||
|
||||
x = value;
|
||||
for (a=0;a < bits;a++)
|
||||
{
|
||||
m2 = 1 << (a << 1);
|
||||
m1 = m2 - 1;
|
||||
m3 = (~m1) << 1;
|
||||
x = (x & m1) + (x & m2) + ((x & m3) << 1);
|
||||
}
|
||||
return x;
|
||||
}
|
||||
|
||||
UINT32 dilate1(UINT32 value,int bits) // dilate first "bits" bits in "value"
|
||||
{
|
||||
UINT32 x,m1,m2,m3;
|
||||
int a;
|
||||
|
||||
x = value;
|
||||
for (a=0;a < bits;a++)
|
||||
{
|
||||
m2 = 1 << (a << 1);
|
||||
m1 = m2 - 1;
|
||||
m3 = (~m1) << 1;
|
||||
x = (x & m1) + ((x & m2) << 1) + ((x & m3) << 1);
|
||||
}
|
||||
return x;
|
||||
}
|
||||
|
||||
void computedilated(void)
|
||||
{
|
||||
int a,b;
|
||||
|
||||
for (b=0;b <= 10;b++)
|
||||
for (a=0;a < 1024;a++) {
|
||||
dilated0[b][a]=dilate0(a,b);
|
||||
dilated1[b][a]=dilate1(a,b);
|
||||
}
|
||||
for (b=0;b <= 7;b++)
|
||||
for (a=0;a < 7;a++)
|
||||
dilatechose[(b << 3) + a]=3+(a < b ? a : b);
|
||||
}
|
||||
|
||||
void testdrawscreen(bitmap_t *bitmap,const rectangle *cliprect)
|
||||
{
|
||||
int cs,x,y,dx,dy,xi,yi,a;
|
||||
float iu,iv,u,v;
|
||||
UINT32 addrp;
|
||||
UINT32 *bmpaddr;
|
||||
int c,xt,yt,cd;
|
||||
|
||||
fillbitmap(bitmap,MAKE_RGB(128,128,128),cliprect);
|
||||
for (cs=0;cs < testsprites_size;cs++)
|
||||
{
|
||||
dx=showsprites[cs].sizex;
|
||||
dy=showsprites[cs].sizey;
|
||||
iu=showsprites[cs].du/dx;
|
||||
iv=showsprites[cs].dv/dy;
|
||||
cd=dilatechose[showsprites[cs].texturesizes];
|
||||
|
||||
if ((showsprites[cs].positionx+dx) > 640)
|
||||
dx=640-showsprites[cs].positionx;
|
||||
if ((showsprites[cs].positiony+dy) > 480)
|
||||
dy=480-showsprites[cs].positiony;
|
||||
xi=0;
|
||||
yi=0;
|
||||
|
||||
if (showsprites[cs].positionx < 0)
|
||||
xi=-showsprites[cs].positionx;
|
||||
if (showsprites[cs].positiony < 0)
|
||||
yi=-showsprites[cs].positiony;
|
||||
|
||||
for (y = yi;y < dy;y++)
|
||||
{
|
||||
for (x = xi;x < dx;x++)
|
||||
{
|
||||
u=showsprites[cs].u+iu*x;
|
||||
v=showsprites[cs].v+iv*y;
|
||||
yt=v*(showsprites[cs].texturesizey-1);
|
||||
xt=u*(showsprites[cs].texturesizex-1);
|
||||
|
||||
if (showsprites[cs].texturemode == 1)
|
||||
addrp=showsprites[cs].textureaddress+(showsprites[cs].texturesizex*yt+xt)*2;
|
||||
else
|
||||
addrp=showsprites[cs].textureaddress+(dilated1[cd][xt] + dilated0[cd][yt])*2;
|
||||
|
||||
c=*(((UINT16 *)dc_texture_ram) + (WORD2_XOR_LE(addrp) >> 1));
|
||||
if (showsprites[cs].texturepf == 2)
|
||||
{
|
||||
a=(c & 0xf000) >> 8;
|
||||
bmpaddr=BITMAP_ADDR32(bitmap,showsprites[cs].positiony+y,showsprites[cs].positionx+x);
|
||||
*bmpaddr = alpha_blend_r32(*bmpaddr, MAKE_RGB((c&0xf00) >> 4, c&0xf0, (c&0xf) << 4), a);
|
||||
}
|
||||
else
|
||||
{
|
||||
a=(c & 0x7000) >> 7;
|
||||
bmpaddr=BITMAP_ADDR32(bitmap,showsprites[cs].positiony+y,showsprites[cs].positionx+x);
|
||||
*bmpaddr = alpha_blend_r32(*bmpaddr, MAKE_RGB((c&0x7c00) >> 7, (c&0x3e0) >> 2, (c&0x1f) << 3), a);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/* test video end */
|
||||
|
||||
VIDEO_START(dc)
|
||||
{
|
||||
memset(pvrctrl_regs, 0, sizeof(pvrctrl_regs));
|
||||
memset(pvrta_regs, 0, sizeof(pvrta_regs));
|
||||
|
||||
// if the next 2 registers do not have the correct values, the naomi bios will hang
|
||||
pvrta_regs[PVRID]=0x17fd11db;
|
||||
pvrta_regs[REVISION]=0x11;
|
||||
pvrta_regs[VO_CONTROL]=0xC;
|
||||
pvrta_regs[SOFTRESET]=0x7;
|
||||
tafifo_pos=0;
|
||||
tafifo_mask=7;
|
||||
tafifo_vertexwords=8;
|
||||
tafifo_listtype= -1;
|
||||
start_render_received=0;
|
||||
|
||||
testsprites_size=0;
|
||||
toerasesprites=0;
|
||||
computedilated();
|
||||
}
|
||||
|
||||
VIDEO_UPDATE(dc)
|
||||
{
|
||||
int a;
|
||||
|
||||
if (pvrta_regs[VO_CONTROL] & (1 << 3))
|
||||
{
|
||||
fillbitmap(bitmap,pvrta_regs[VO_BORDER_COL] & 0xFFFFFF,cliprect);
|
||||
return 0;
|
||||
}
|
||||
|
||||
testdrawscreen(bitmap,cliprect);
|
||||
|
||||
if (start_render_received)
|
||||
{
|
||||
start_render_received=0;
|
||||
a=4; // tsp end
|
||||
sysctrl_regs[SB_ISTNRM] |= a;
|
||||
update_interrupt_status();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dc_vblank(void)
|
||||
{
|
||||
sysctrl_regs[SB_ISTNRM] |= 0x08; // V Blank-in interrupt
|
||||
update_interrupt_status();
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user