From 3f690ce5eed8836e350674c5924a0c52c5bd8895 Mon Sep 17 00:00:00 2001 From: AJR Date: Thu, 27 Jan 2022 09:26:22 -0500 Subject: [PATCH] 65C02 updates - Add W65C02S CPU emulation with subtly different fetch patterns from classic 65C02 and use it for arbv2, cmmb103, cmmb162 and bbc_tube_rc6502 - Replace ST2XXX's slightly customized CPU emulation with hooks into new W65C02S core --- scripts/src/cpu.lua | 39 +- src/devices/bus/bbc/tube/tube_rc6502.cpp | 2 +- src/devices/bus/bbc/tube/tube_rc6502.h | 2 +- src/devices/cpu/m6502/dst2xxx.lst | 20 - src/devices/cpu/m6502/dw65c02s.lst | 20 + src/devices/cpu/m6502/ost2xxx.lst | 58 -- src/devices/cpu/m6502/ow65c02s.lst | 875 +++++++++++++++++++++++ src/devices/cpu/m6502/st2xxx.cpp | 38 +- src/devices/cpu/m6502/st2xxx.h | 21 +- src/devices/cpu/m6502/w65c02s.cpp | 33 + src/devices/cpu/m6502/w65c02s.h | 71 ++ src/mame/drivers/ave_arb.cpp | 4 +- src/mame/drivers/cmmb.cpp | 4 +- 13 files changed, 1052 insertions(+), 135 deletions(-) delete mode 100644 src/devices/cpu/m6502/dst2xxx.lst create mode 100644 src/devices/cpu/m6502/dw65c02s.lst delete mode 100644 src/devices/cpu/m6502/ost2xxx.lst create mode 100644 src/devices/cpu/m6502/ow65c02s.lst create mode 100644 src/devices/cpu/m6502/w65c02s.cpp create mode 100644 src/devices/cpu/m6502/w65c02s.h diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua index 949eca4d3f8..8528391edc4 100644 --- a/scripts/src/cpu.lua +++ b/scripts/src/cpu.lua @@ -1562,6 +1562,7 @@ end --@src/devices/cpu/m6502/st2xxx.h,CPUS["ST2XXX"] = true --@src/devices/cpu/m6502/st2204.h,CPUS["ST2XXX"] = true --@src/devices/cpu/m6502/st2205u.h,CPUS["ST2XXX"] = true +--@src/devices/cpu/m6502/w65c02s.h,CPUS["M6502"] = true --@src/devices/cpu/m6502/xavix.h,CPUS["XAVIX"] = true --@src/devices/cpu/m6502/xavix.h,CPUS["XAVIX2000"] = true @@ -1603,6 +1604,8 @@ if CPUS["M6502"] then MAME_DIR .. "src/devices/cpu/m6502/r65c02.h", MAME_DIR .. "src/devices/cpu/m6502/r65c19.cpp", MAME_DIR .. "src/devices/cpu/m6502/r65c19.h", + MAME_DIR .. "src/devices/cpu/m6502/w65c02s.cpp", + MAME_DIR .. "src/devices/cpu/m6502/w65c02s.h", MAME_DIR .. "src/devices/cpu/m6502/m740.cpp", MAME_DIR .. "src/devices/cpu/m6502/m740.h", MAME_DIR .. "src/devices/cpu/m6502/m3745x.cpp", @@ -1612,17 +1615,18 @@ if CPUS["M6502"] then } custombuildtask { - { MAME_DIR .. "src/devices/cpu/m6502/odeco16.lst", GEN_DIR .. "emu/cpu/m6502/deco16.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/ddeco16.lst" }, {"@echo Generating deco16 disassembler source file...", PYTHON .. " $(1) s deco16 $(<) $(2) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/om4510.lst", GEN_DIR .. "emu/cpu/m6502/m4510.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm4510.lst" }, {"@echo Generating m4510 disassembler source file...", PYTHON .. " $(1) s m4510 $(<) $(2) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/om6502.lst", GEN_DIR .. "emu/cpu/m6502/m6502.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm6502.lst" }, {"@echo Generating m6502 disassembler source file...", PYTHON .. " $(1) s m6502 $(<) $(2) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/om65c02.lst", GEN_DIR .. "emu/cpu/m6502/m65c02.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm65c02.lst" }, {"@echo Generating m65c02 disassembler source file...", PYTHON .. " $(1) s m65c02 $(<) $(2) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/om65ce02.lst", GEN_DIR .. "emu/cpu/m6502/m65ce02.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm65ce02.lst" }, {"@echo Generating m65ce02 disassembler source file...", PYTHON .. " $(1) s m65ce02 $(<) $(2) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/om6509.lst", GEN_DIR .. "emu/cpu/m6502/m6509.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm6509.lst" }, {"@echo Generating m6509 disassembler source file...", PYTHON .. " $(1) s m6509 $(<) $(2) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/om6510.lst", GEN_DIR .. "emu/cpu/m6502/m6510.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm6510.lst" }, {"@echo Generating m6510 disassembler source file...", PYTHON .. " $(1) s m6510 $(<) $(2) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/on2a03.lst", GEN_DIR .. "emu/cpu/m6502/n2a03.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dn2a03.lst" }, {"@echo Generating n2a03 disassembler source file...", PYTHON .. " $(1) s n2a03_core $(<) $(2) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/om740.lst" , GEN_DIR .. "emu/cpu/m6502/m740.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm740.lst" }, {"@echo Generating m740 disassembler source file...", PYTHON .. " $(1) s m740 $(<) $(2) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/dr65c02.lst", GEN_DIR .. "emu/cpu/m6502/r65c02.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", }, {"@echo Generating r65c02 disassembler source file...", PYTHON .. " $(1) s r65c02 - $(<) $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6502/or65c19.lst", GEN_DIR .. "emu/cpu/m6502/r65c19.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dr65c19.lst" }, {"@echo Generating r65c19 disassembler source file...", PYTHON .. " $(1) s r65c19 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/odeco16.lst", GEN_DIR .. "emu/cpu/m6502/deco16.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/ddeco16.lst" }, {"@echo Generating deco16 instruction source file...", PYTHON .. " $(1) s deco16 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/om4510.lst", GEN_DIR .. "emu/cpu/m6502/m4510.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm4510.lst" }, {"@echo Generating m4510 instruction source file...", PYTHON .. " $(1) s m4510 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/om6502.lst", GEN_DIR .. "emu/cpu/m6502/m6502.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm6502.lst" }, {"@echo Generating m6502 instruction source file...", PYTHON .. " $(1) s m6502 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/om65c02.lst", GEN_DIR .. "emu/cpu/m6502/m65c02.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm65c02.lst" }, {"@echo Generating m65c02 instruction source file...", PYTHON .. " $(1) s m65c02 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/om65ce02.lst", GEN_DIR .. "emu/cpu/m6502/m65ce02.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm65ce02.lst" }, {"@echo Generating m65ce02 instruction source file...", PYTHON .. " $(1) s m65ce02 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/om6509.lst", GEN_DIR .. "emu/cpu/m6502/m6509.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm6509.lst" }, {"@echo Generating m6509 instruction source file...", PYTHON .. " $(1) s m6509 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/om6510.lst", GEN_DIR .. "emu/cpu/m6502/m6510.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm6510.lst" }, {"@echo Generating m6510 instruction source file...", PYTHON .. " $(1) s m6510 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/on2a03.lst", GEN_DIR .. "emu/cpu/m6502/n2a03.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dn2a03.lst" }, {"@echo Generating n2a03 instruction source file...", PYTHON .. " $(1) s n2a03_core $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/om740.lst" , GEN_DIR .. "emu/cpu/m6502/m740.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dm740.lst" }, {"@echo Generating m740 instruction source file...", PYTHON .. " $(1) s m740 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/dr65c02.lst", GEN_DIR .. "emu/cpu/m6502/r65c02.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", }, {"@echo Generating r65c02 instruction source file...", PYTHON .. " $(1) s r65c02 - $(<) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/or65c19.lst", GEN_DIR .. "emu/cpu/m6502/r65c19.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dr65c19.lst" }, {"@echo Generating r65c19 instruction source file...", PYTHON .. " $(1) s r65c19 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/ow65c02s.lst", GEN_DIR .. "emu/cpu/m6502/w65c02s.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dw65c02s.lst" }, {"@echo Generating w65c02s instruction source file...", PYTHON .. " $(1) s w65c02s $(<) $(2) $(@)" }}, } dependency { @@ -1636,6 +1640,7 @@ if CPUS["M6502"] then { MAME_DIR .. "src/devices/cpu/m6502/n2a03.cpp", GEN_DIR .. "emu/cpu/m6502/n2a03.hxx" }, { MAME_DIR .. "src/devices/cpu/m6502/r65c02.cpp", GEN_DIR .. "emu/cpu/m6502/r65c02.hxx" }, { MAME_DIR .. "src/devices/cpu/m6502/r65c19.cpp", GEN_DIR .. "emu/cpu/m6502/r65c19.hxx" }, + { MAME_DIR .. "src/devices/cpu/m6502/w65c02s.cpp", GEN_DIR .. "emu/cpu/m6502/w65c02s.hxx" }, { MAME_DIR .. "src/devices/cpu/m6502/m740.cpp", GEN_DIR .. "emu/cpu/m6502/m740.hxx" }, } end @@ -1649,14 +1654,6 @@ if CPUS["ST2XXX"] then MAME_DIR .. "src/devices/cpu/m6502/st2205u.cpp", MAME_DIR .. "src/devices/cpu/m6502/st2205u.h", } - - custombuildtask { - { MAME_DIR .. "src/devices/cpu/m6502/ost2xxx.lst" , GEN_DIR .. "emu/cpu/m6502/st2xxx.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dst2xxx.lst" }, {"@echo Generating st2xxx disassembler source file...", PYTHON .. " $(1) s st2xxx $(<) $(2) $(@)" }}, - } - - dependency { - { MAME_DIR .. "src/devices/cpu/m6502/st2xxx.cpp", GEN_DIR .. "emu/cpu/m6502/st2xxx.hxx" }, - } end if CPUS["XAVIX"] then @@ -1666,7 +1663,7 @@ if CPUS["XAVIX"] then } custombuildtask { - { MAME_DIR .. "src/devices/cpu/m6502/oxavix.lst", GEN_DIR .. "emu/cpu/m6502/xavix.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dxavix.lst" }, {"@echo Generating xavix disassembler source file...", PYTHON .. " $(1) s xavix $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/oxavix.lst", GEN_DIR .. "emu/cpu/m6502/xavix.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dxavix.lst" }, {"@echo Generating xavix instruction source file...", PYTHON .. " $(1) s xavix $(<) $(2) $(@)" }}, } dependency { @@ -1681,7 +1678,7 @@ if CPUS["XAVIX2000"] then } custombuildtask { - { MAME_DIR .. "src/devices/cpu/m6502/oxavix2000.lst", GEN_DIR .. "emu/cpu/m6502/xavix2000.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dxavix2000.lst" }, {"@echo Generating xavix2000 disassembler source file...", PYTHON .. " $(1) s xavix2000 $(<) $(2) $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6502/oxavix2000.lst", GEN_DIR .. "emu/cpu/m6502/xavix2000.hxx", { MAME_DIR .. "src/devices/cpu/m6502/m6502make.py", MAME_DIR .. "src/devices/cpu/m6502/dxavix2000.lst" }, {"@echo Generating xavix2000 instruction source file...", PYTHON .. " $(1) s xavix2000 $(<) $(2) $(@)" }}, } dependency { diff --git a/src/devices/bus/bbc/tube/tube_rc6502.cpp b/src/devices/bus/bbc/tube/tube_rc6502.cpp index 1c05d6c3b89..18d1fbd93dc 100644 --- a/src/devices/bus/bbc/tube/tube_rc6502.cpp +++ b/src/devices/bus/bbc/tube/tube_rc6502.cpp @@ -129,7 +129,7 @@ void bbc_tube_rc6502_device::add_common_devices(machine_config &config) void bbc_tube_rc6502_device::device_add_mconfig(machine_config &config) { - M65C02(config, m_maincpu, 44.2368_MHz_XTAL); + W65C02S(config, m_maincpu, 44.2368_MHz_XTAL); m_maincpu->set_addrmap(AS_PROGRAM, &bbc_tube_rc6502_device::tube_rc6502_mem); add_common_devices(config); diff --git a/src/devices/bus/bbc/tube/tube_rc6502.h b/src/devices/bus/bbc/tube/tube_rc6502.h index eadb460cc96..5636e8694ef 100644 --- a/src/devices/bus/bbc/tube/tube_rc6502.h +++ b/src/devices/bus/bbc/tube/tube_rc6502.h @@ -13,7 +13,7 @@ #define MAME_BUS_BBC_TUBE_RC6502_H #include "tube.h" -#include "cpu/m6502/m65c02.h" +#include "cpu/m6502/w65c02s.h" #include "cpu/g65816/g65816.h" #include "machine/bankdev.h" #include "machine/ram.h" diff --git a/src/devices/cpu/m6502/dst2xxx.lst b/src/devices/cpu/m6502/dst2xxx.lst deleted file mode 100644 index e9687ba68f9..00000000000 --- a/src/devices/cpu/m6502/dst2xxx.lst +++ /dev/null @@ -1,20 +0,0 @@ -# license:BSD-3-Clause -# copyright-holders:Olivier Galibert -# almost identical to r65c02 -brk_st_imp ora_idx nop_imm nop_c_imp tsb_zpg ora_zpg asl_c_zpg rmb_bzp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_c_aba bbr_zpb -bpl_rel ora_idy ora_zpi nop_c_imp trb_zpg ora_zpx asl_c_zpx rmb_bzp clc_imp ora_aby inc_acc nop_c_imp trb_aba ora_abx asl_c_abx bbr_zpb -jsr_adr and_idx nop_imm nop_c_imp bit_zpg and_zpg rol_c_zpg rmb_bzp plp_imp and_imm rol_acc nop_c_imp bit_aba and_aba rol_c_aba bbr_zpb -bmi_rel and_idy and_zpi nop_c_imp bit_zpx and_zpx rol_c_zpx rmb_bzp sec_imp and_aby dec_acc nop_c_imp bit_abx and_abx rol_c_abx bbr_zpb -rti_st_imp eor_idx nop_imm nop_c_imp nop_zpg eor_zpg lsr_c_zpg rmb_bzp pha_imp eor_imm lsr_acc nop_c_imp jmp_adr eor_aba lsr_c_aba bbr_zpb -bvc_rel eor_idy eor_zpi nop_c_imp nop_zpx eor_zpx lsr_c_zpx rmb_bzp cli_imp eor_aby phy_imp nop_c_imp nop_c_aba eor_abx lsr_c_abx bbr_zpb -rts_imp adc_c_idx nop_imm nop_c_imp stz_zpg adc_c_zpg ror_c_zpg rmb_bzp pla_imp adc_c_imm ror_acc nop_c_imp jmp_c_ind adc_c_aba ror_c_aba bbr_zpb -bvs_rel adc_c_idy adc_c_zpi nop_c_imp stz_zpx adc_c_zpx ror_c_zpx rmb_bzp sei_imp adc_c_aby ply_imp nop_c_imp jmp_iax adc_c_abx ror_c_abx bbr_zpb -bra_rel sta_idx nop_imm nop_c_imp sty_zpg sta_zpg stx_zpg smb_bzp dey_imp bit_imm txa_imp nop_c_imp sty_aba sta_aba stx_aba bbs_zpb -bcc_rel sta_idy sta_zpi nop_c_imp sty_zpx sta_zpx stx_zpy smb_bzp tya_imp sta_aby txs_imp nop_c_imp stz_aba sta_abx stz_abx bbs_zpb -ldy_imm lda_idx ldx_imm nop_c_imp ldy_zpg lda_zpg ldx_zpg smb_bzp tay_imp lda_imm tax_imp nop_c_imp ldy_aba lda_aba ldx_aba bbs_zpb -bcs_rel lda_idy lda_zpi nop_c_imp ldy_zpx lda_zpx ldx_zpy smb_bzp clv_imp lda_aby tsx_imp nop_c_imp ldy_abx lda_abx ldx_aby bbs_zpb -cpy_imm cmp_idx nop_imm nop_c_imp cpy_zpg cmp_zpg dec_c_zpg smb_bzp iny_imp cmp_imm dex_imp wai_imp cpy_aba cmp_aba dec_c_aba bbs_zpb -bne_rel cmp_idy cmp_zpi nop_c_imp nop_zpx cmp_zpx dec_c_zpx smb_bzp cld_imp cmp_aby phx_imp stp_imp nop_c_abx cmp_abx dec_c_abx bbs_zpb -cpx_imm sbc_c_idx nop_imm nop_c_imp cpx_zpg sbc_c_zpg inc_c_zpg smb_bzp inx_imp sbc_c_imm nop_imp nop_c_imp cpx_aba sbc_c_aba inc_c_aba bbs_zpb -beq_rel sbc_c_idy sbc_c_zpi nop_c_imp nop_zpx sbc_c_zpx inc_c_zpx smb_bzp sed_imp sbc_c_aby plx_imp nop_c_imp nop_c_abx sbc_c_abx inc_c_abx bbs_zpb -reset_st diff --git a/src/devices/cpu/m6502/dw65c02s.lst b/src/devices/cpu/m6502/dw65c02s.lst new file mode 100644 index 00000000000..b8d67e3afec --- /dev/null +++ b/src/devices/cpu/m6502/dw65c02s.lst @@ -0,0 +1,20 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert +# w65c02s - WDC variant, with different dummy fetch patterns for indexed modes +brk_s_imp ora_s_idx nop_imm nop_c_imp tsb_s_zpg ora_zpg asl_s_zpg rmb_bzp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_c_aba bbr_zpb +bpl_rel ora_s_idy ora_zpi nop_c_imp trb_s_zpg ora_s_zpx asl_s_zpx rmb_bzp clc_imp ora_s_aby inc_acc nop_c_imp trb_aba ora_s_abx asl_s_abx bbr_zpb +jsr_adr and_s_idx nop_imm nop_c_imp bit_zpg and_zpg rol_s_zpg rmb_bzp plp_s_imp and_imm rol_acc nop_c_imp bit_aba and_aba rol_c_aba bbr_zpb +bmi_rel and_s_idy and_zpi nop_c_imp bit_s_zpx and_s_zpx rol_s_zpx rmb_bzp sec_imp and_s_aby dec_acc nop_c_imp bit_s_abx and_s_abx rol_s_abx bbr_zpb +rti_s_imp eor_s_idx nop_imm nop_c_imp nop_zpg eor_zpg lsr_s_zpg rmb_bzp pha_imp eor_imm lsr_acc nop_c_imp jmp_adr eor_aba lsr_c_aba bbr_zpb +bvc_rel eor_s_idy eor_zpi nop_c_imp nop_s_zpx eor_s_zpx lsr_s_zpx rmb_bzp cli_imp eor_s_aby phy_imp nop_c_imp nop_c_aba eor_s_abx lsr_s_abx bbr_zpb +rts_s_imp adc_s_idx nop_imm nop_c_imp stz_zpg adc_c_zpg ror_s_zpg rmb_bzp pla_s_imp adc_c_imm ror_acc nop_c_imp jmp_s_ind adc_c_aba ror_c_aba bbr_zpb +bvs_rel adc_s_idy adc_c_zpi nop_c_imp stz_s_zpx adc_s_zpx ror_s_zpx rmb_bzp sei_imp adc_s_aby ply_s_imp nop_c_imp jmp_s_iax adc_s_abx ror_s_abx bbr_zpb +bra_rel sta_s_idx nop_imm nop_c_imp sty_zpg sta_zpg stx_zpg smb_bzp dey_imp bit_imm txa_imp nop_c_imp sty_aba sta_aba stx_aba bbs_zpb +bcc_rel sta_s_idy sta_zpi nop_c_imp sty_s_zpx sta_s_zpx stx_s_zpy smb_bzp tya_imp sta_s_aby txs_imp nop_c_imp stz_aba sta_s_abx stz_s_abx bbs_zpb +ldy_imm lda_s_idx ldx_imm nop_c_imp ldy_zpg lda_zpg ldx_zpg smb_bzp tay_imp lda_imm tax_imp nop_c_imp ldy_aba lda_aba ldx_aba bbs_zpb +bcs_rel lda_s_idy lda_zpi nop_c_imp ldy_s_zpx lda_s_zpx ldx_s_zpy smb_bzp clv_imp lda_s_aby tsx_imp nop_c_imp ldy_s_abx lda_s_abx ldx_s_aby bbs_zpb +cpy_imm cmp_s_idx nop_imm nop_c_imp cpy_zpg cmp_zpg dec_s_zpg smb_bzp iny_imp cmp_imm dex_imp wai_imp cpy_aba cmp_aba dec_c_aba bbs_zpb +bne_rel cmp_s_idy cmp_zpi nop_c_imp nop_s_zpx cmp_s_zpx dec_s_zpx smb_bzp cld_imp cmp_s_aby phx_imp stp_imp nop_s_abx cmp_s_abx dec_s_abx bbs_zpb +cpx_imm sbc_s_idx nop_imm nop_c_imp cpx_zpg sbc_c_zpg inc_s_zpg smb_bzp inx_imp sbc_c_imm nop_imp nop_c_imp cpx_aba sbc_c_aba inc_c_aba bbs_zpb +beq_rel sbc_s_idy sbc_c_zpi nop_c_imp nop_s_zpx sbc_s_zpx inc_s_zpx smb_bzp sed_imp sbc_s_aby plx_s_imp nop_c_imp nop_s_abx sbc_s_abx inc_s_abx bbs_zpb +reset_s diff --git a/src/devices/cpu/m6502/ost2xxx.lst b/src/devices/cpu/m6502/ost2xxx.lst deleted file mode 100644 index 4468fe14476..00000000000 --- a/src/devices/cpu/m6502/ost2xxx.lst +++ /dev/null @@ -1,58 +0,0 @@ -# license:BSD-3-Clause -# copyright-holders:Olivier Galibert -# m65c02 opcodes, with a twist - -brk_st_imp - if(irq_taken || nmi_pending) { - read_pc_noinc(); - } else { - read_pc(); - } - write(SP, PC >> 8); - dec_SP(); - write(SP, PC); - dec_SP(); - write(SP, irq_taken || nmi_pending ? P & ~F_B : P); - dec_SP(); - set_irq_service(true); - if(irq_taken && nmi_pending) { // NMI is not present on actual parts - PC = read_vector(0x7ffa); - PC = set_h(PC, read_vector(0x7ffb)); - nmi_pending = false; - } else if(irq_taken) { - TMP = acknowledge_irq(); - PC = read_vector(0x7ff8 - (TMP << 1)); - PC = set_h(PC, read_vector(0x7ff9 - (TMP << 1))); - } else { - PC = read_vector(0x7ffe); - PC = set_h(PC, read_vector(0x7fff)); - } - irq_taken = false; - P = (P | F_I) & ~F_D; // Do *not* move after the prefetch - prefetch(); - inst_state = -1; - -rti_st_imp - read_pc_noinc(); - read(SP); - inc_SP(); - P = read(SP) | (F_B|F_E); - inc_SP(); - PC = read(SP); - inc_SP(); - PC = set_h(PC, read(SP)); - set_irq_service(false); - prefetch(); - -reset_st - read_arg(0xffff); - read_pc_noinc(); - read(SP); dec_SP(); - read(SP); dec_SP(); - read(SP); dec_SP(); - P = (P | F_I) & ~F_D; - set_irq_service(false); - PC = read_vector(0x7ffc); - PC = set_h(PC, read_vector(0x7ffd)); - prefetch(); - inst_state = -1; diff --git a/src/devices/cpu/m6502/ow65c02s.lst b/src/devices/cpu/m6502/ow65c02s.lst new file mode 100644 index 00000000000..d4af33d7074 --- /dev/null +++ b/src/devices/cpu/m6502/ow65c02s.lst @@ -0,0 +1,875 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert +# w65c02s opcodes + +adc_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + TMP = read(TMP); + do_adc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +adc_s_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + TMP += Y; + TMP = read(TMP); + do_adc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +adc_s_idx + TMP2 = read_pc_noinc(); + read_pc_noinc(); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_adc(read(TMP)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +adc_s_idy + TMP2 = read_pc_noinc(); + TMP = read(TMP2); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + do_adc(read(TMP+Y)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +adc_s_zpx + TMP = read_pc_noinc(); + read_pc_noinc(); + TMP = read(uint8_t(TMP+X)); + do_adc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +and_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + A &= read(TMP); + set_nz(A); + PC++; + prefetch(); + +and_s_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + TMP += Y; + A &= read(TMP); + set_nz(A); + PC++; + prefetch(); + +and_s_idx + TMP2 = read_pc_noinc(); + read_pc(); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A &= read(TMP); + set_nz(A); + prefetch(); + +and_s_idy + TMP2 = read_pc_noinc(); + TMP = read(TMP2); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + A &= read(TMP+Y); + set_nz(A); + PC++; + prefetch(); + +and_s_zpx + TMP = read_pc_noinc(); + read_pc(); + A &= read(uint8_t(TMP+X)); + set_nz(A); + prefetch(); + +asl_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + TMP2 = read(TMP); + read(TMP+1); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + PC++; + prefetch(); + +asl_s_zpg + TMP = read_pc(); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +asl_s_zpx + TMP = read_pc_noinc(); + read_pc(); + TMP = uint8_t(TMP+X); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +bit_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + do_bit(read(TMP)); + PC++; + prefetch(); + +bit_s_zpx + TMP = read_pc_noinc(); + read_pc(); + TMP = read(uint8_t(TMP+X)); + do_bit(TMP); + prefetch(); + +brk_s_imp + if(irq_taken || nmi_pending) { + read_pc_noinc(); + } else { + read_pc(); + } + write(SP, PC >> 8); + dec_SP(); + write(SP, PC); + dec_SP(); + write(SP, irq_taken || nmi_pending ? P & ~F_B : P); + dec_SP(); + if(irq_taken && nmi_pending) { + PC = read_vector(0xfffa); + PC = set_h(PC, read_vector(0xfffb)); + nmi_pending = false; + standard_irq_callback(NMI_LINE); + } else { + PC = read_vector(0xfffe); + PC = set_h(PC, read_vector(0xffff)); + if(irq_taken) + standard_irq_callback(IRQ_LINE); + } + irq_taken = false; + P = (P | F_I) & ~F_D; // Do *not* move after the prefetch + prefetch(); + inst_state = -1; + +cmp_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + TMP = read(TMP); + do_cmp(A, TMP); + PC++; + prefetch(); + +cmp_s_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + TMP += Y; + TMP = read(TMP); + do_cmp(A, TMP); + PC++; + prefetch(); + +cmp_s_idx + TMP2 = read_pc_noinc(); + read_pc(); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_cmp(A, read(TMP)); + prefetch(); + +cmp_s_idy + TMP2 = read_pc_noinc(); + TMP = read(TMP2); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + do_cmp(A, read(TMP+Y)); + PC++; + prefetch(); + +cmp_s_zpx + TMP = read_pc_noinc(); + read_pc(); + TMP = read(uint8_t(TMP+X)); + do_cmp(A, TMP); + prefetch(); + +dec_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + TMP2 = read(TMP); + read(TMP+1); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + PC++; + prefetch(); + +dec_s_zpg + TMP = read_pc(); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +dec_s_zpx + TMP = read_pc_noinc(); + read_pc(); + TMP = uint8_t(TMP+X); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +eor_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + A ^= read(TMP); + set_nz(A); + PC++; + prefetch(); + +eor_s_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + TMP += Y; + A ^= read(TMP); + set_nz(A); + PC++; + prefetch(); + +eor_s_idx + TMP2 = read_pc_noinc(); + read_pc(); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A ^= read(TMP); + set_nz(A); + prefetch(); + +eor_s_idy + TMP2 = read_pc_noinc(); + TMP = read(TMP2); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + A ^= read(TMP+Y); + set_nz(A); + PC++; + prefetch(); + +eor_s_zpx + TMP = read_pc_noinc(); + read_pc(); + A ^= read(uint8_t(TMP+X)); + set_nz(A); + prefetch(); + +inc_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + TMP2 = read(TMP); + read(TMP+1); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + PC++; + prefetch(); + +inc_s_zpg + TMP = read_pc(); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +inc_s_zpx + TMP = read_pc_noinc(); + read_pc(); + TMP = uint8_t(TMP+X); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +jmp_s_iax + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + read_pc_noinc(); + TMP += X; + PC = read(TMP); + PC = set_h(PC, read(TMP+1)); + prefetch(); + +jmp_s_ind + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + read_pc_noinc(); + PC = read(TMP); + PC = set_h(PC, read(TMP+1)); + prefetch(); + +lda_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + A = read(TMP + X); + set_nz(A); + PC++; + prefetch(); + +lda_s_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + A = read(TMP + Y); + set_nz(A); + PC++; + prefetch(); + +lda_s_idx + TMP2 = read_pc_noinc(); + read_pc(); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A = read(TMP); + set_nz(A); + prefetch(); + +lda_s_idy + TMP2 = read_pc_noinc(); + TMP = read(TMP2); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + A = read(TMP+Y); + set_nz(A); + PC++; + prefetch(); + +lda_s_zpx + TMP = read_pc_noinc(); + read_pc(); + A = read(uint8_t(TMP+X)); + set_nz(A); + prefetch(); + +ldx_s_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + X = read(TMP + Y); + set_nz(X); + PC++; + prefetch(); + +ldx_s_zpy + TMP = read_pc_noinc(); + read_pc(); + X = read(uint8_t(TMP+Y)); + set_nz(X); + prefetch(); + +ldy_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + Y = read(TMP); + set_nz(Y); + PC++; + prefetch(); + +ldy_s_zpx + TMP = read_pc_noinc(); + read_pc(); + Y = read(uint8_t(TMP+X)); + set_nz(Y); + prefetch(); + +lsr_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + PC++; + prefetch(); + +lsr_s_zpg + TMP = read_pc(); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +lsr_s_zpx + TMP = read_pc_noinc(); + read_pc(); + TMP = uint8_t(TMP+X); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +nop_s_abx + read_pc(); + read_pc_noinc(); + read_pc(); + prefetch(); + +nop_s_zpx + TMP = read_pc_noinc(); + read_pc(); + read(uint8_t(TMP+X)); + prefetch(); + +ora_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + A |= read(TMP); + set_nz(A); + PC++; + prefetch(); + +ora_s_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + TMP += Y; + A |= read(TMP); + set_nz(A); + PC++; + prefetch(); + +ora_s_idx + TMP2 = read_pc_noinc(); + read_pc(); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A |= read(TMP); + set_nz(A); + prefetch(); + +ora_s_idy + TMP2 = read_pc_noinc(); + TMP = read(TMP2); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + A |= read(TMP+Y); + set_nz(A); + PC++; + prefetch(); + +ora_s_zpx + TMP = read_pc_noinc(); + read_pc(); + A |= read(uint8_t(TMP+X)); + set_nz(A); + prefetch(); + +pla_s_imp + read_pc_noinc(); + read_pc_noinc(); + inc_SP(); + A = read(SP); + set_nz(A); + prefetch(); + +plp_s_imp + read_pc_noinc(); + read_pc_noinc(); + inc_SP(); + TMP = read(SP) | (F_B|F_E); + prefetch(); + P = TMP; // Do *not* move it before the prefetch + +plx_s_imp + read_pc_noinc(); + read_pc_noinc(); + inc_SP(); + X = read(SP); + set_nz(X); + prefetch(); + +ply_s_imp + read_pc_noinc(); + read_pc_noinc(); + inc_SP(); + Y = read(SP); + set_nz(Y); + prefetch(); + +rol_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + TMP2 = read(TMP); + read(TMP+1); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + PC++; + prefetch(); + +rol_s_zpg + TMP = read_pc(); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +rol_s_zpx + TMP = read_pc_noinc(); + read_pc(); + TMP = uint8_t(TMP+X); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + TMP2 = read(TMP); + read(TMP+1); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + PC++; + prefetch(); + +ror_s_zpg + TMP = read_pc(); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_s_zpx + TMP = read_pc_noinc(); + read_pc(); + TMP = uint8_t(TMP+X); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +rti_s_imp + read_pc_noinc(); + inc_SP(); + P = read(SP) | (F_B|F_E); + inc_SP(); + TMP = read(SP); + inc_SP(); + TMP = set_h(TMP, read(SP)); + read_pc_noinc(); + end_interrupt(); + PC = TMP; + prefetch(); + +rts_s_imp + read_pc_noinc(); + read_pc_noinc(); + inc_SP(); + TMP = read(SP); + inc_SP(); + TMP = set_h(TMP, read(SP)); + read_pc_noinc(); + PC = TMP + 1; + prefetch(); + +sbc_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, X)) { + read_pc_noinc(); + } + TMP += X; + TMP = read(TMP); + do_sbc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +sbc_s_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + TMP += Y; + TMP = read(TMP); + do_sbc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +sbc_s_idx + TMP2 = read_pc_noinc(); + read_pc_noinc(); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_sbc(read(TMP)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +sbc_s_idy + TMP2 = read_pc_noinc(); + TMP = read(TMP2); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + if(page_changing(TMP, Y)) { + read_pc_noinc(); + } + do_sbc(read(TMP+Y)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +sbc_s_zpx + TMP = read_pc_noinc(); + read_pc_noinc(); + TMP = read(uint8_t(TMP+X)); + do_sbc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + PC++; + prefetch(); + +sta_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + read_pc(); + write(TMP+X, A); + prefetch(); + +sta_s_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + read_pc(); + write(TMP+Y, A); + prefetch(); + +sta_s_idx + TMP2 = read_pc_noinc(); + read_pc(); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + write(TMP, A); + prefetch(); + +sta_s_idy + TMP2 = read_pc_noinc(); + TMP = read(TMP2); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + read_pc(); + write(TMP+Y, A); + prefetch(); + +sta_s_zpx + TMP = read_pc_noinc(); + read_pc(); + write(uint8_t(TMP+X), A); + prefetch(); + +stx_s_zpy + TMP = read_pc_noinc(); + read_pc(); + write(uint8_t(TMP+Y), X); + prefetch(); + +sty_s_zpx + TMP = read_pc_noinc(); + read_pc(); + write(uint8_t(TMP+X), Y); + prefetch(); + +stz_s_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc_noinc()); + read_pc(); + write(TMP+X, 0x00); + prefetch(); + +stz_s_zpx + TMP = read_pc_noinc(); + read_pc(); + write(uint8_t(TMP+X), 0x00); + prefetch(); + +trb_s_zpg + TMP = read_pc(); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 &= ~A; + write(TMP, TMP2); + prefetch(); + +tsb_s_zpg + TMP = read_pc(); + TMP2 = read(TMP); + read((TMP+1) & 0xff); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 |= A; + write(TMP, TMP2); + prefetch(); + +# exceptions +reset_s + read_arg(0xffff); + read_pc_noinc(); + read(SP); dec_SP(); + read(SP); dec_SP(); + read(SP); dec_SP(); + P = (P | F_I) & ~F_D; + PC = read_vector(0xfffc); + PC = set_h(PC, read_vector(0xfffd)); + prefetch(); + inst_state = -1; diff --git a/src/devices/cpu/m6502/st2xxx.cpp b/src/devices/cpu/m6502/st2xxx.cpp index 2c24f65f653..bc73afc7750 100644 --- a/src/devices/cpu/m6502/st2xxx.cpp +++ b/src/devices/cpu/m6502/st2xxx.cpp @@ -38,11 +38,12 @@ #define LOG_IRQ (1 << 1U) #define LOG_BT (1 << 2U) #define LOG_LCDC (1 << 3U) +#define VERBOSE LOG_IRQ //#define VERBOSE (LOG_IRQ | LOG_BT | LOG_LCDC) #include "logmacro.h" st2xxx_device::st2xxx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor internal_map, int data_bits, bool has_banked_ram) - : r65c02_device(mconfig, type, tag, owner, clock) + : w65c02s_device(mconfig, type, tag, owner, clock) , m_data_config("data", ENDIANNESS_LITTLE, 8, data_bits, 0) , m_in_port_cb(*this) , m_out_port_cb(*this) @@ -281,24 +282,35 @@ void st2xxx_device::device_reset() m_bctr = 0; } -u8 st2xxx_device::acknowledge_irq() +u8 st2xxx_device::read_vector(u16 adr) { - // IREQH interrupts have priority over IREQL interrupts - for (int pri = 0; pri < 16; pri++) + if (adr >= 0xfffe) { - int level = pri ^ 8; - if (BIT(m_ireq & m_iena, level)) + u16 ireq_active = m_ireq & m_iena; + if (ireq_active != 0 && irq_taken) { - LOGMASKED(LOG_IRQ, "%s interrupt acknowledged (PC = $%04X, vector = $%04X)\n", + // IREQH interrupts have priority over IREQL interrupts + ireq_active = swapendian_int16(ireq_active); + int level = 31 - int(8 ^ count_leading_zeros_32(ireq_active & -ireq_active)); + adr -= (level + 3) << 1; + + LOGMASKED(LOG_IRQ, "Acknowledging %s interrupt (PC = $%04X, IREQ = $%04X, IENA = $%04X, vector pull from $%04X)\n", st2xxx_irq_name(level), PPC, - 0x7ff8 - (level << 1)); - m_ireq &= ~(1 << level); - update_irq_state(); - return level; + m_ireq, + m_iena, + adr & 0x7fff); + + if (BIT(adr, 0)) + { + m_ireq &= ~(1 << level); + update_irq_state(); + } + else + set_irq_service(true); } } - throw emu_fatalerror("ST2XXX: no IRQ to acknowledge!\n"); + return downcast(*mintf).read_vector(adr); } u8 st2xxx_device::pdata_r(offs_t offset) @@ -892,5 +904,3 @@ void st2xxx_device::bdiv_w(u8 data) { m_bdiv = data; } - -#include "cpu/m6502/st2xxx.hxx" diff --git a/src/devices/cpu/m6502/st2xxx.h b/src/devices/cpu/m6502/st2xxx.h index cd6138b6e12..90f7c4d53c9 100644 --- a/src/devices/cpu/m6502/st2xxx.h +++ b/src/devices/cpu/m6502/st2xxx.h @@ -6,9 +6,9 @@ #pragma once -#include "r65c02.h" +#include "w65c02s.h" -class st2xxx_device : public r65c02_device { +class st2xxx_device : public w65c02s_device { public: enum { ST_PAOUT = M6502_IR + 1, @@ -91,9 +91,6 @@ protected: virtual void device_resolve_objects() override; virtual void device_reset() override; - virtual void do_exec_full() override; - virtual void do_exec_partial() override; - virtual u16 st2xxx_ireq_mask() const = 0; virtual const char *st2xxx_irq_name(int i) const = 0; virtual u8 st2xxx_pmcr_mask() const = 0; @@ -133,11 +130,11 @@ protected: void init_lcd_timer(u16 ireq); void save_common_registers(); - u8 read_vector(u16 adr) { return downcast(*mintf).read_vector(adr); } - void set_irq_service(bool state) { downcast(*mintf).irq_service = state; } + virtual u8 read_vector(u16 adr) override; + virtual void end_interrupt() override { set_irq_service(false); } + void set_irq_service(bool state) { downcast(*mintf).irq_service = state; } void update_irq_state() { irq_state = (m_ireq & m_iena) != 0; } - u8 acknowledge_irq(); TIMER_CALLBACK_MEMBER(bt_interrupt); TIMER_CALLBACK_MEMBER(lcd_interrupt); @@ -242,14 +239,6 @@ protected: u8 bdiv_r(); void bdiv_w(u8 data); -#define O(o) void o ## _full(); void o ## _partial() - - O(brk_st_imp); - O(rti_st_imp); - O(reset_st); - -#undef O - address_space_config m_data_config; devcb_read8::array<7> m_in_port_cb; diff --git a/src/devices/cpu/m6502/w65c02s.cpp b/src/devices/cpu/m6502/w65c02s.cpp new file mode 100644 index 00000000000..171db777dc2 --- /dev/null +++ b/src/devices/cpu/m6502/w65c02s.cpp @@ -0,0 +1,33 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert +/*************************************************************************** + + w65c02s.cpp + + WDC W65C02S, CMOS variant with bitwise instructions, BE, ML, VP pins + and cleaner fetch patterns + +***************************************************************************/ + +#include "emu.h" +#include "w65c02s.h" +#include "r65c02d.h" + +DEFINE_DEVICE_TYPE(W65C02S, w65c02s_device, "w65c02s", "WDC W65C02S") + +w65c02s_device::w65c02s_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + w65c02s_device(mconfig, W65C02S, tag, owner, clock) +{ +} + +w65c02s_device::w65c02s_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : + m65c02_device(mconfig, type, tag, owner, clock) +{ +} + +std::unique_ptr w65c02s_device::create_disassembler() +{ + return std::make_unique(); +} + +#include "cpu/m6502/w65c02s.hxx" diff --git a/src/devices/cpu/m6502/w65c02s.h b/src/devices/cpu/m6502/w65c02s.h new file mode 100644 index 00000000000..a5848f86e68 --- /dev/null +++ b/src/devices/cpu/m6502/w65c02s.h @@ -0,0 +1,71 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert +/*************************************************************************** + + w65c02s.h + + WDC W65C02S, CMOS variant with bitwise instructions, BE, ML, VP pins + and cleaner fetch patterns + +***************************************************************************/ + +#ifndef MAME_CPU_M6502_W65C02S_H +#define MAME_CPU_M6502_W65C02S_H + +#include "m65c02.h" + +class w65c02s_device : public m65c02_device { +public: + w65c02s_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + virtual std::unique_ptr create_disassembler() override; + virtual void do_exec_full() override; + virtual void do_exec_partial() override; + +protected: + w65c02s_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); + + virtual uint8_t read_vector(uint16_t adr) { return mintf->read_arg(adr); } + virtual void end_interrupt() { } + +#define O(o) void o ## _full(); void o ## _partial() + + O(adc_s_abx); O(adc_s_aby); O(adc_s_idx); O(adc_s_idy); O(adc_s_zpx); + O(and_s_abx); O(and_s_aby); O(and_s_idx); O(and_s_idy); O(and_s_zpx); + O(asl_s_abx); O(asl_s_zpg); O(asl_s_zpx); + O(bit_s_abx); O(bit_s_zpx); + O(brk_s_imp); + O(cmp_s_abx); O(cmp_s_aby); O(cmp_s_idx); O(cmp_s_idy); O(cmp_s_zpx); + O(dec_s_abx); O(dec_s_zpg); O(dec_s_zpx); + O(eor_s_abx); O(eor_s_aby); O(eor_s_idx); O(eor_s_idy); O(eor_s_zpx); + O(inc_s_abx); O(inc_s_zpg); O(inc_s_zpx); + O(jmp_s_iax); O(jmp_s_ind); + O(lda_s_abx); O(lda_s_aby); O(lda_s_idx); O(lda_s_idy); O(lda_s_zpx); + O(ldx_s_aby); O(ldx_s_zpy); + O(ldy_s_abx); O(ldy_s_zpx); + O(lsr_s_abx); O(lsr_s_zpg); O(lsr_s_zpx); + O(nop_s_abx); O(nop_s_zpx); + O(ora_s_abx); O(ora_s_aby); O(ora_s_idx); O(ora_s_idy); O(ora_s_zpx); + O(pla_s_imp); + O(plp_s_imp); + O(plx_s_imp); + O(ply_s_imp); + O(rol_s_abx); O(rol_s_zpg); O(rol_s_zpx); + O(ror_s_abx); O(ror_s_zpg); O(ror_s_zpx); + O(rti_s_imp); + O(rts_s_imp); + O(sbc_s_abx); O(sbc_s_aby); O(sbc_s_idx); O(sbc_s_idy); O(sbc_s_zpx); + O(sta_s_abx); O(sta_s_aby); O(sta_s_idx); O(sta_s_idy); O(sta_s_zpx); + O(stx_s_zpy); + O(sty_s_zpx); + O(stz_s_abx); O(stz_s_zpx); + O(trb_s_zpg); + O(tsb_s_zpg); + O(reset_s); + +#undef O +}; + +DECLARE_DEVICE_TYPE(W65C02S, w65c02s_device) + +#endif // MAME_CPU_M6502_W65C02S_H diff --git a/src/mame/drivers/ave_arb.cpp b/src/mame/drivers/ave_arb.cpp index e3152a287a4..0a15c61933c 100644 --- a/src/mame/drivers/ave_arb.cpp +++ b/src/mame/drivers/ave_arb.cpp @@ -42,7 +42,7 @@ TODO: #include "bus/generic/carts.h" #include "bus/generic/slot.h" #include "cpu/m6502/m6502.h" -#include "cpu/m6502/m65c02.h" +#include "cpu/m6502/w65c02s.h" #include "video/pwm.h" #include "machine/sensorboard.h" #include "machine/6522via.h" @@ -289,7 +289,7 @@ INPUT_PORTS_END void arb_state::v2(machine_config &config) { /* basic machine hardware */ - M65C02(config, m_maincpu, 16_MHz_XTAL); // W65C02S6TPG-14 + W65C02S(config, m_maincpu, 16_MHz_XTAL); // W65C02S6TPG-14 m_maincpu->set_addrmap(AS_PROGRAM, &arb_state::v2_map); W65C22S(config, m_via, 16_MHz_XTAL); // W65C22S6TPG-14 diff --git a/src/mame/drivers/cmmb.cpp b/src/mame/drivers/cmmb.cpp index f070fed1f4d..e8ab82f5a41 100644 --- a/src/mame/drivers/cmmb.cpp +++ b/src/mame/drivers/cmmb.cpp @@ -50,7 +50,7 @@ OSC @ 72.576MHz ***************************************************************************/ #include "emu.h" -#include "cpu/m6502/m65sc02.h" +#include "cpu/m6502/w65c02s.h" #include "machine/at29x.h" #include "machine/bankdev.h" #include "emupal.h" @@ -409,7 +409,7 @@ void cmmb_state::machine_reset() void cmmb_state::cmmb(machine_config &config) { /* basic machine hardware */ - M65SC02(config, m_maincpu, MAIN_CLOCK/5); // Unknown clock, but chip rated for 14MHz + W65C02S(config, m_maincpu, MAIN_CLOCK/5); // Unknown clock, but chip rated for 14MHz m_maincpu->set_addrmap(AS_PROGRAM, &cmmb_state::cmmb_map); m_maincpu->set_vblank_int("screen", FUNC(cmmb_state::vblank_irq));