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https://github.com/holub/mame
synced 2025-05-10 00:01:52 +03:00
N64, RSP, drc : Wrap PC to 12 bits in a few more places.
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parent
66ac95eb05
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3fc3f8254e
@ -671,7 +671,7 @@ void rsp_device::generate_checksum_block(drcuml_block *block, compiler_state *co
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if (seqhead->delay.first() != nullptr && seqhead->physpc != seqhead->delay.first()->physpc)
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{
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base = m_direct->read_ptr(seqhead->delay.first()->physpc | 0x1000);
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base = m_direct->read_ptr((seqhead->delay.first()->physpc & 0x00000fff) | 0x1000);
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assert(base != nullptr);
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UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword
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UML_ADD(block, I0, I0, I1); // add i0,i0,i1
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@ -702,7 +702,7 @@ void rsp_device::generate_checksum_block(drcuml_block *block, compiler_state *co
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if (curdesc->delay.first() != nullptr && (curdesc == seqlast || (curdesc->next() != nullptr && curdesc->next()->physpc != curdesc->delay.first()->physpc)))
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{
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base = m_direct->read_ptr(curdesc->delay.first()->physpc | 0x1000);
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base = m_direct->read_ptr((curdesc->delay.first()->physpc & 0x00000fff) | 0x1000);
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assert(base != nullptr);
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UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword
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UML_ADD(block, I0, I0, I1); // add i0,i0,i1
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@ -813,7 +813,7 @@ void rsp_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_st
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/* set the link if needed -- before the delay slot */
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if (linkreg != 0)
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{
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UML_MOV(block, R32(linkreg), (int32_t)(desc->pc + 8)); // mov <linkreg>,desc->pc + 8
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UML_MOV(block, R32(linkreg), (int32_t)((desc->pc + 8) & 0x0000fff)); // mov <linkreg>,desc->pc + 8
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}
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/* compile the delay slot using temporary compiler state */
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@ -37,7 +37,7 @@ bool rsp_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
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uint32_t op, opswitch;
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// fetch the opcode
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op = desc.opptr.l[0] = m_rsp.m_direct->read_dword(desc.physpc | 0x1000);
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op = desc.opptr.l[0] = m_rsp.m_direct->read_dword((desc.physpc & 0x00000fff) | 0x1000);
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// all instructions are 4 bytes and default to a single cycle each
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desc.length = 4;
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