diff --git a/src/emu/sound/disc_mth.c b/src/emu/sound/disc_mth.c index de6dc723807..aa020899e21 100644 --- a/src/emu/sound/disc_mth.c +++ b/src/emu/sound/disc_mth.c @@ -699,166 +699,112 @@ static DISCRETE_RESET(dst_bits_decode) * * DST_LOGIC_AND - Logic AND gate implementation * - * input[0] - Enable - * input[1] - input[0] value - * input[2] - input[1] value - * input[3] - input[2] value - * input[4] - input[3] value + * input[0] - input[0] value + * input[1] - input[1] value + * input[2] - input[2] value + * input[3] - input[3] value * ************************************************************************/ -#define DST_LOGIC_AND__ENABLE DISCRETE_INPUT(0) -#define DST_LOGIC_AND__IN0 DISCRETE_INPUT(1) -#define DST_LOGIC_AND__IN1 DISCRETE_INPUT(2) -#define DST_LOGIC_AND__IN2 DISCRETE_INPUT(3) -#define DST_LOGIC_AND__IN3 DISCRETE_INPUT(4) +#define DST_LOGIC_AND__IN0 DISCRETE_INPUT(0) +#define DST_LOGIC_AND__IN1 DISCRETE_INPUT(1) +#define DST_LOGIC_AND__IN2 DISCRETE_INPUT(2) +#define DST_LOGIC_AND__IN3 DISCRETE_INPUT(3) static DISCRETE_STEP(dst_logic_and) { - if(DST_LOGIC_AND__ENABLE) - { - node->output[0] = (DST_LOGIC_AND__IN0 && DST_LOGIC_AND__IN1 && DST_LOGIC_AND__IN2 && DST_LOGIC_AND__IN3)? 1.0 : 0.0; - } - else - { - node->output[0] = 0.0; - } + node->output[0] = (DST_LOGIC_AND__IN0 && DST_LOGIC_AND__IN1 && DST_LOGIC_AND__IN2 && DST_LOGIC_AND__IN3)? 1.0 : 0.0; } /************************************************************************ * * DST_LOGIC_NAND - Logic NAND gate implementation * - * input[0] - Enable - * input[1] - input[0] value - * input[2] - input[1] value - * input[3] - input[2] value - * input[4] - input[3] value + * input[0] - input[0] value + * input[1] - input[1] value + * input[2] - input[2] value + * input[3] - input[3] value * ************************************************************************/ -#define DST_LOGIC_NAND__ENABLE DISCRETE_INPUT(0) -#define DST_LOGIC_NAND__IN0 DISCRETE_INPUT(1) -#define DST_LOGIC_NAND__IN1 DISCRETE_INPUT(2) -#define DST_LOGIC_NAND__IN2 DISCRETE_INPUT(3) -#define DST_LOGIC_NAND__IN3 DISCRETE_INPUT(4) +#define DST_LOGIC_NAND__IN0 DISCRETE_INPUT(0) +#define DST_LOGIC_NAND__IN1 DISCRETE_INPUT(1) +#define DST_LOGIC_NAND__IN2 DISCRETE_INPUT(2) +#define DST_LOGIC_NAND__IN3 DISCRETE_INPUT(3) static DISCRETE_STEP(dst_logic_nand) { - if(DST_LOGIC_NAND__ENABLE) - { - node->output[0]= (DST_LOGIC_NAND__IN0 && DST_LOGIC_NAND__IN1 && DST_LOGIC_NAND__IN2 && DST_LOGIC_NAND__IN3)? 0.0 : 1.0; - } - else - { - node->output[0] = 0.0; - } + node->output[0]= (DST_LOGIC_NAND__IN0 && DST_LOGIC_NAND__IN1 && DST_LOGIC_NAND__IN2 && DST_LOGIC_NAND__IN3)? 0.0 : 1.0; } /************************************************************************ * * DST_LOGIC_OR - Logic OR gate implementation * - * input[0] - Enable - * input[1] - input[0] value - * input[2] - input[1] value - * input[3] - input[2] value - * input[4] - input[3] value + * input[0] - input[0] value + * input[1] - input[1] value + * input[2] - input[2] value + * input[3] - input[3] value * ************************************************************************/ -#define DST_LOGIC_OR__ENABLE DISCRETE_INPUT(0) -#define DST_LOGIC_OR__IN0 DISCRETE_INPUT(1) -#define DST_LOGIC_OR__IN1 DISCRETE_INPUT(2) -#define DST_LOGIC_OR__IN2 DISCRETE_INPUT(3) -#define DST_LOGIC_OR__IN3 DISCRETE_INPUT(4) +#define DST_LOGIC_OR__IN0 DISCRETE_INPUT(0) +#define DST_LOGIC_OR__IN1 DISCRETE_INPUT(1) +#define DST_LOGIC_OR__IN2 DISCRETE_INPUT(2) +#define DST_LOGIC_OR__IN3 DISCRETE_INPUT(3) static DISCRETE_STEP(dst_logic_or) { - if(DST_LOGIC_OR__ENABLE) - { - node->output[0] = (DST_LOGIC_OR__IN0 || DST_LOGIC_OR__IN1 || DST_LOGIC_OR__IN2 || DST_LOGIC_OR__IN3) ? 1.0 : 0.0; - } - else - { - node->output[0] = 0.0; - } + node->output[0] = (DST_LOGIC_OR__IN0 || DST_LOGIC_OR__IN1 || DST_LOGIC_OR__IN2 || DST_LOGIC_OR__IN3) ? 1.0 : 0.0; } /************************************************************************ * * DST_LOGIC_NOR - Logic NOR gate implementation * - * input[0] - Enable - * input[1] - input[0] value - * input[2] - input[1] value - * input[3] - input[2] value - * input[4] - input[3] value + * input[0] - input[0] value + * input[1] - input[1] value + * input[2] - input[2] value + * input[3] - input[3] value * ************************************************************************/ -#define DST_LOGIC_NOR__ENABLE DISCRETE_INPUT(0) -#define DST_LOGIC_NOR__IN0 DISCRETE_INPUT(1) -#define DST_LOGIC_NOR__IN1 DISCRETE_INPUT(2) -#define DST_LOGIC_NOR__IN2 DISCRETE_INPUT(3) -#define DST_LOGIC_NOR__IN3 DISCRETE_INPUT(4) +#define DST_LOGIC_NOR__IN0 DISCRETE_INPUT(0) +#define DST_LOGIC_NOR__IN1 DISCRETE_INPUT(1) +#define DST_LOGIC_NOR__IN2 DISCRETE_INPUT(2) +#define DST_LOGIC_NOR__IN3 DISCRETE_INPUT(3) static DISCRETE_STEP(dst_logic_nor) { - if(DST_LOGIC_NOR__ENABLE) - { - node->output[0] = (DST_LOGIC_NOR__IN0 || DST_LOGIC_NOR__IN1 || DST_LOGIC_NOR__IN2 || DST_LOGIC_NOR__IN3) ? 0.0 : 1.0; - } - else - { - node->output[0] = 0.0; - } + node->output[0] = (DST_LOGIC_NOR__IN0 || DST_LOGIC_NOR__IN1 || DST_LOGIC_NOR__IN2 || DST_LOGIC_NOR__IN3) ? 0.0 : 1.0; } /************************************************************************ * * DST_LOGIC_XOR - Logic XOR gate implementation * - * input[0] - Enable - * input[1] - input[0] value - * input[2] - input[1] value + * input[0] - input[0] value + * input[1] - input[1] value * ************************************************************************/ -#define DST_LOGIC_XOR__ENABLE DISCRETE_INPUT(0) -#define DST_LOGIC_XOR__IN0 DISCRETE_INPUT(1) -#define DST_LOGIC_XOR__IN1 DISCRETE_INPUT(2) +#define DST_LOGIC_XOR__IN0 DISCRETE_INPUT(0) +#define DST_LOGIC_XOR__IN1 DISCRETE_INPUT(1) static DISCRETE_STEP(dst_logic_xor) { - if(DST_LOGIC_XOR__ENABLE) - { - node->output[0] = ((DST_LOGIC_XOR__IN0 && !DST_LOGIC_XOR__IN1) || (!DST_LOGIC_XOR__IN0 && DST_LOGIC_XOR__IN1)) ? 1.0 : 0.0; - } - else - { - node->output[0] = 0.0; - } + node->output[0] = ((DST_LOGIC_XOR__IN0 && !DST_LOGIC_XOR__IN1) || (!DST_LOGIC_XOR__IN0 && DST_LOGIC_XOR__IN1)) ? 1.0 : 0.0; } /************************************************************************ * * DST_LOGIC_NXOR - Logic NXOR gate implementation * - * input[0] - Enable - * input[1] - input[0] value - * input[2] - input[1] value + * input[0] - input[0] value + * input[1] - input[1] value * ************************************************************************/ -#define DST_LOGIC_XNOR__ENABLE DISCRETE_INPUT(0) -#define DST_LOGIC_XNOR__IN0 DISCRETE_INPUT(1) -#define DST_LOGIC_XNOR__IN1 DISCRETE_INPUT(2) +#define DST_LOGIC_XNOR__IN0 DISCRETE_INPUT(0) +#define DST_LOGIC_XNOR__IN1 DISCRETE_INPUT(1) static DISCRETE_STEP(dst_logic_nxor) { - if(DST_LOGIC_XNOR__ENABLE) - { - node->output[0] = ((DST_LOGIC_XNOR__IN0 && !DST_LOGIC_XNOR__IN1) || (!DST_LOGIC_XNOR__IN0 && DST_LOGIC_XNOR__IN1)) ? 0.0 : 1.0; - } - else - { - node->output[0] = 0.0; - } + node->output[0] = ((DST_LOGIC_XNOR__IN0 && !DST_LOGIC_XNOR__IN1) || (!DST_LOGIC_XNOR__IN0 && DST_LOGIC_XNOR__IN1)) ? 0.0 : 1.0; } @@ -866,18 +812,16 @@ static DISCRETE_STEP(dst_logic_nxor) * * DST_LOGIC_DFF - Standard D-type flip-flop implementation * - * input[0] - enable - * input[1] - /Reset - * input[2] - /Set - * input[3] - clock - * input[4] - data + * input[0] - /Reset + * input[1] - /Set + * input[2] - clock + * input[3] - data * ************************************************************************/ -#define DST_LOGIC_DFF__ENABLE DISCRETE_INPUT(0) -#define DST_LOGIC_DFF__RESET !DISCRETE_INPUT(1) -#define DST_LOGIC_DFF__SET !DISCRETE_INPUT(2) -#define DST_LOGIC_DFF__CLOCK DISCRETE_INPUT(3) -#define DST_LOGIC_DFF__DATA DISCRETE_INPUT(4) +#define DST_LOGIC_DFF__RESET !DISCRETE_INPUT(0) +#define DST_LOGIC_DFF__SET !DISCRETE_INPUT(1) +#define DST_LOGIC_DFF__CLOCK DISCRETE_INPUT(2) +#define DST_LOGIC_DFF__DATA DISCRETE_INPUT(3) static DISCRETE_STEP(dst_logic_dff) { @@ -885,19 +829,12 @@ static DISCRETE_STEP(dst_logic_dff) int clk = (int)DST_LOGIC_DFF__CLOCK; - if (DST_LOGIC_DFF__ENABLE) - { - if (DST_LOGIC_DFF__RESET) - node->output[0] = 0; - else if (DST_LOGIC_DFF__SET) - node->output[0] = 1; - else if (!context->last_clk && clk) /* low to high */ - node->output[0] = DST_LOGIC_DFF__DATA; - } - else - { + if (DST_LOGIC_DFF__RESET) node->output[0] = 0; - } + else if (DST_LOGIC_DFF__SET) + node->output[0] = 1; + else if (!context->last_clk && clk) /* low to high */ + node->output[0] = DST_LOGIC_DFF__DATA; context->last_clk = clk; } @@ -914,20 +851,18 @@ static DISCRETE_RESET(dst_logic_ff) * * DST_LOGIC_JKFF - Standard JK-type flip-flop implementation * - * input[0] - enable - * input[1] - /Reset - * input[2] - /Set - * input[3] - clock - * input[4] - J - * input[5] - K + * input[0] - /Reset + * input[1] - /Set + * input[2] - clock + * input[3] - J + * input[4] - K * ************************************************************************/ -#define DST_LOGIC_JKFF__ENABLE DISCRETE_INPUT(0) -#define DST_LOGIC_JKFF__RESET !DISCRETE_INPUT(1) -#define DST_LOGIC_JKFF__SET !DISCRETE_INPUT(2) -#define DST_LOGIC_JKFF__CLOCK DISCRETE_INPUT(3) -#define DST_LOGIC_JKFF__J DISCRETE_INPUT(4) -#define DST_LOGIC_JKFF__K DISCRETE_INPUT(5) +#define DST_LOGIC_JKFF__RESET !DISCRETE_INPUT(0) +#define DST_LOGIC_JKFF__SET !DISCRETE_INPUT(1) +#define DST_LOGIC_JKFF__CLOCK DISCRETE_INPUT(2) +#define DST_LOGIC_JKFF__J DISCRETE_INPUT(3) +#define DST_LOGIC_JKFF__K DISCRETE_INPUT(4) static DISCRETE_STEP(dst_logic_jkff) { @@ -937,35 +872,28 @@ static DISCRETE_STEP(dst_logic_jkff) int j = (int)DST_LOGIC_JKFF__J; int k = (int)DST_LOGIC_JKFF__K; - if (DST_LOGIC_JKFF__ENABLE) - { - if (DST_LOGIC_JKFF__RESET) - node->output[0] = 0; - else if (DST_LOGIC_JKFF__SET) - node->output[0] = 1; - else if (context->last_clk && !clk) /* high to low */ - { - if (!j) - { - /* J=0, K=0 - Hold */ - if (k) - /* J=0, K=1 - Reset */ - node->output[0] = 0; - } - else - { - if (!k) - /* J=1, K=0 - Set */ - node->output[0] = 1; - else - /* J=1, K=1 - Toggle */ - node->output[0] = !(int)node->output[0]; - } - } - } - else - { + if (DST_LOGIC_JKFF__RESET) node->output[0] = 0; + else if (DST_LOGIC_JKFF__SET) + node->output[0] = 1; + else if (context->last_clk && !clk) /* high to low */ + { + if (!j) + { + /* J=0, K=0 - Hold */ + if (k) + /* J=0, K=1 - Reset */ + node->output[0] = 0; + } + else + { + if (!k) + /* J=1, K=0 - Set */ + node->output[0] = 1; + else + /* J=1, K=1 - Toggle */ + node->output[0] = !(int)node->output[0]; + } } context->last_clk = clk; } diff --git a/src/emu/sound/discrete.h b/src/emu/sound/discrete.h index 557242d26c1..9a6e1d42ba0 100644 --- a/src/emu/sound/discrete.h +++ b/src/emu/sound/discrete.h @@ -259,22 +259,22 @@ * DISCRETE_BITS_DECODE(NODE,INP,BIT_FROM,BIT_TO,VOUT) * * DISCRETE_LOGIC_INVERT(NODE,INP0) - * DISCRETE_LOGIC_AND(NODE,ENAB,INP0,INP1) - * DISCRETE_LOGIC_AND3(NODE,ENAB,INP0,INP1,INP2) - * DISCRETE_LOGIC_AND4(NODE,ENAB,INP0,INP1,INP2,INP3) - * DISCRETE_LOGIC_NAND(NODE,ENAB,INP0,INP1) - * DISCRETE_LOGIC_NAND3(NODE,ENAB,INP0,INP1,INP2) - * DISCRETE_LOGIC_NAND4(NODE,ENAB,INP0,INP1,INP2,INP3) - * DISCRETE_LOGIC_OR(NODE,ENAB,INP0,INP1) - * DISCRETE_LOGIC_OR3(NODE,ENAB,INP0,INP1,INP2) - * DISCRETE_LOGIC_OR4(NODE,ENAB,INP0,INP1,INP2,INP3) - * DISCRETE_LOGIC_NOR(NODE,ENAB,INP0,INP1) - * DISCRETE_LOGIC_NOR3(NODE,ENAB,INP0,INP1,INP2) - * DISCRETE_LOGIC_NOR4(NODE,ENAB,INP0,INP1,INP2,INP3) - * DISCRETE_LOGIC_XOR(NODE,ENAB,INP0,INP1) - * DISCRETE_LOGIC_NXOR(NODE,ENAB,INP0,INP1) - * DISCRETE_LOGIC_DFLIPFLOP(NODE,ENAB,RESET,SET,CLK,INP) - * DISCRETE_LOGIC_JKFLIPFLOP(NODE,ENAB,RESET,SET,CLK,J,K) + * DISCRETE_LOGIC_AND(NODE,INP0,INP1) + * DISCRETE_LOGIC_AND3(NODE,INP0,INP1,INP2) + * DISCRETE_LOGIC_AND4(NODE,INP0,INP1,INP2,INP3) + * DISCRETE_LOGIC_NAND(NODE,INP0,INP1) + * DISCRETE_LOGIC_NAND3(NODE,INP0,INP1,INP2) + * DISCRETE_LOGIC_NAND4(NODE,INP0,INP1,INP2,INP3) + * DISCRETE_LOGIC_OR(NODE,INP0,INP1) + * DISCRETE_LOGIC_OR3(NODE,INP0,INP1,INP2) + * DISCRETE_LOGIC_OR4(NODE,INP0,INP1,INP2,INP3) + * DISCRETE_LOGIC_NOR(NODE,INP0,INP1) + * DISCRETE_LOGIC_NOR3(NODE,INP0,INP1,INP2) + * DISCRETE_LOGIC_NOR4(NODE,INP0,INP1,INP2,INP3) + * DISCRETE_LOGIC_XOR(NODE,INP0,INP1) + * DISCRETE_LOGIC_NXOR(NODE,INP0,INP1) + * DISCRETE_LOGIC_DFLIPFLOP(NODE,RESET,SET,CLK,INP) + * DISCRETE_LOGIC_JKFLIPFLOP(NODE,RESET,SET,CLK,J,K) * DISCRETE_MULTIPLEX2(NODE,ENAB,ADDR,INP0,INP1) * DISCRETE_MULTIPLEX4(NODE,ENAB,ADDR,INP0,INP1,INP2,INP3) * DISCRETE_MULTIPLEX8(NODE,ENAB,ADDR,INP0,INP1,INP2,INP3,INP4,INP5,INP6,INP7) @@ -1286,7 +1286,7 @@ * *********************************************************************** * - * DISCRETE_LOGIC_INVERT - Logic invertor (no enable node) + * DISCRETE_LOGIC_INVERT - Logic invertor * DISCRETE_LOGIC_AND - Logic AND gate (3 & 4 input also available) * DISCRETE_LOGIC_NAND - Logic NAND gate (3 & 4 input also available) * DISCRETE_LOGIC_OR - Logic OR gate (3 & 4 input also available) @@ -1296,8 +1296,6 @@ * * .------------. * | | - * ENAB -0------>| | - * | | * INPUT0 -0------>| | * | LOGIC | * [INPUT1] -1------>| FUNCTION |----> Netlist node @@ -1311,7 +1309,7 @@ * Declaration syntax * * DISCRETE_LOGIC_XXXn(name of node, - * (X=INV/AND/etc) enable node or static value, + * (X=INV/AND/etc) * (n=Blank/2/3) input0 node or static value, * [input1 node or static value], * [input2 node or static value], @@ -1319,9 +1317,9 @@ * * Example config lines * - * DISCRETE_LOGIC_INVERT(NODE_03,1,NODE_12) - * DISCRETE_LOGIC_AND(NODE_03,1,NODE_12,NODE_13) - * DISCRETE_LOGIC_NOR4(NODE_03,1,NODE_12,NODE_13,NODE_14,NODE_15) + * DISCRETE_LOGIC_INVERT(NODE_03,NODE_12) + * DISCRETE_LOGIC_AND(NODE_03,NODE_12,NODE_13) + * DISCRETE_LOGIC_NOR4(NODE_03,NODE_12,NODE_13,NODE_14,NODE_15) * * Node output is always either 0.0 or 1.0 any input value !=0.0 is * taken as a logic 1. @@ -1348,7 +1346,6 @@ * Declaration syntax * * DISCRETE_LOGIC_DFLIPFLOP(name of node, - * enable node or static value, * reset node or static value, * set node or static value, * clock node, @@ -1356,7 +1353,7 @@ * * Example config line * - * DISCRETE_LOGIC_DFLIPFLOP(NODE_7,1,NODE_17,0,NODE_13,1) + * DISCRETE_LOGIC_DFLIPFLOP(NODE_7,NODE_17,0,NODE_13,1) * * A flip-flop that clocks a logic 1 through on the rising edge of * NODE_13. A logic 1 on NODE_17 resets the output to 0. @@ -1385,7 +1382,6 @@ * Declaration syntax * * DISCRETE_LOGIC_JKFLIPFLOP(name of node, - * enable node or static value, * reset node or static value, * set node or static value, * clock node, @@ -4299,22 +4295,22 @@ enum #define DISCRETE_BIT_DECODE(NODE, INP, BIT_N, VOUT) { NODE, DST_BITS_DECODE , 3, { INP,NODE_NC,NODE_NC,NODE_NC }, { INP,BIT_N,BIT_N, VOUT }, NULL, "DISCRETE_BIT_DECODE" }, #define DISCRETE_BITS_DECODE(NODE, INP, BIT_FROM, BIT_TO, VOUT) { NODE, DST_BITS_DECODE , 4, { INP,NODE_NC,NODE_NC,NODE_NC }, { INP,BIT_FROM,BIT_TO, VOUT }, NULL, "DISCRETE_BITS_DECODE" }, -#define DISCRETE_LOGIC_AND(NODE,ENAB,INP0,INP1) { NODE, DST_LOGIC_AND , 5, { ENAB,INP0,INP1,NODE_NC,NODE_NC }, { ENAB,INP0,INP1,1.0,1.0 }, NULL, "DISCRETE_LOGIC_AND" }, -#define DISCRETE_LOGIC_AND3(NODE,ENAB,INP0,INP1,INP2) { NODE, DST_LOGIC_AND , 5, { ENAB,INP0,INP1,INP2,NODE_NC }, { ENAB,INP0,INP1,INP2,1.0 }, NULL, "DISCRETE_LOGIC_AND3" }, -#define DISCRETE_LOGIC_AND4(NODE,ENAB,INP0,INP1,INP2,INP3) { NODE, DST_LOGIC_AND , 5, { ENAB,INP0,INP1,INP2,INP3 }, { ENAB,INP0,INP1,INP2,INP3 } ,NULL, "DISCRETE_LOGIC_AND4" }, -#define DISCRETE_LOGIC_NAND(NODE,ENAB,INP0,INP1) { NODE, DST_LOGIC_NAND , 5, { ENAB,INP0,INP1,NODE_NC,NODE_NC }, { ENAB,INP0,INP1,1.0,1.0 }, NULL, "DISCRETE_LOGIC_NAND" }, -#define DISCRETE_LOGIC_NAND3(NODE,ENAB,INP0,INP1,INP2) { NODE, DST_LOGIC_NAND , 5, { ENAB,INP0,INP1,INP2,NODE_NC }, { ENAB,INP0,INP1,INP2,1.0 }, NULL, "DISCRETE_LOGIC_NAND3" }, -#define DISCRETE_LOGIC_NAND4(NODE,ENAB,INP0,INP1,INP2,INP3) { NODE, DST_LOGIC_NAND , 5, { ENAB,INP0,INP1,INP2,INP3 }, { ENAB,INP0,INP1,INP2,INP3 }, NULL, ")DISCRETE_LOGIC_NAND4" }, -#define DISCRETE_LOGIC_OR(NODE,ENAB,INP0,INP1) { NODE, DST_LOGIC_OR , 5, { ENAB,INP0,INP1,NODE_NC,NODE_NC }, { ENAB,INP0,INP1,0.0,0.0 }, NULL, "DISCRETE_LOGIC_OR" }, -#define DISCRETE_LOGIC_OR3(NODE,ENAB,INP0,INP1,INP2) { NODE, DST_LOGIC_OR , 5, { ENAB,INP0,INP1,INP2,NODE_NC }, { ENAB,INP0,INP1,INP2,0.0 }, NULL, "DISCRETE_LOGIC_OR3" }, -#define DISCRETE_LOGIC_OR4(NODE,ENAB,INP0,INP1,INP2,INP3) { NODE, DST_LOGIC_OR , 5, { ENAB,INP0,INP1,INP2,INP3 }, { ENAB,INP0,INP1,INP2,INP3 }, NULL, "DISCRETE_LOGIC_OR4" }, -#define DISCRETE_LOGIC_NOR(NODE,ENAB,INP0,INP1) { NODE, DST_LOGIC_NOR , 5, { ENAB,INP0,INP1,NODE_NC,NODE_NC }, { ENAB,INP0,INP1,0.0,0.0 }, NULL, "DISCRETE_LOGIC_NOR" }, -#define DISCRETE_LOGIC_NOR3(NODE,ENAB,INP0,INP1,INP2) { NODE, DST_LOGIC_NOR , 5, { ENAB,INP0,INP1,INP2,NODE_NC }, { ENAB,INP0,INP1,INP2,0.0 }, NULL, "DISCRETE_LOGIC_NOR3" }, -#define DISCRETE_LOGIC_NOR4(NODE,ENAB,INP0,INP1,INP2,INP3) { NODE, DST_LOGIC_NOR , 5, { ENAB,INP0,INP1,INP2,INP3 }, { ENAB,INP0,INP1,INP2,INP3 }, NULL, "DISCRETE_LOGIC_NOR4" }, -#define DISCRETE_LOGIC_XOR(NODE,ENAB,INP0,INP1) { NODE, DST_LOGIC_XOR , 3, { ENAB,INP0,INP1 }, { ENAB,INP0,INP1 }, NULL, "DISCRETE_LOGIC_XOR" }, -#define DISCRETE_LOGIC_NXOR(NODE,ENAB,INP0,INP1) { NODE, DST_LOGIC_NXOR , 3, { ENAB,INP0,INP1 }, { ENAB,INP0,INP1 }, NULL, "DISCRETE_LOGIC_NXOR" }, -#define DISCRETE_LOGIC_DFLIPFLOP(NODE,ENAB,RESET,SET,CLK,INP) { NODE, DST_LOGIC_DFF , 5, { ENAB,RESET,SET,CLK,INP }, { ENAB,RESET,SET,CLK,INP }, NULL, "DISCRETE_LOGIC_DFLIPFLOP" }, -#define DISCRETE_LOGIC_JKFLIPFLOP(NODE,ENAB,RESET,SET,CLK,J,K) { NODE, DST_LOGIC_JKFF , 6, { ENAB,RESET,SET,CLK,J,K }, { ENAB,RESET,SET,CLK,J,K }, NULL, "DISCRETE_LOGIC_JKFLIPFLOP" }, +#define DISCRETE_LOGIC_AND(NODE,INP0,INP1) { NODE, DST_LOGIC_AND , 4, { INP0,INP1,NODE_NC,NODE_NC }, { INP0,INP1,1.0,1.0 }, NULL, "DISCRETE_LOGIC_AND" }, +#define DISCRETE_LOGIC_AND3(NODE,INP0,INP1,INP2) { NODE, DST_LOGIC_AND , 4, { INP0,INP1,INP2,NODE_NC }, { INP0,INP1,INP2,1.0 }, NULL, "DISCRETE_LOGIC_AND3" }, +#define DISCRETE_LOGIC_AND4(NODE,INP0,INP1,INP2,INP3) { NODE, DST_LOGIC_AND , 4, { INP0,INP1,INP2,INP3 }, { INP0,INP1,INP2,INP3 } ,NULL, "DISCRETE_LOGIC_AND4" }, +#define DISCRETE_LOGIC_NAND(NODE,INP0,INP1) { NODE, DST_LOGIC_NAND , 4, { INP0,INP1,NODE_NC,NODE_NC }, { INP0,INP1,1.0,1.0 }, NULL, "DISCRETE_LOGIC_NAND" }, +#define DISCRETE_LOGIC_NAND3(NODE,INP0,INP1,INP2) { NODE, DST_LOGIC_NAND , 4, { INP0,INP1,INP2,NODE_NC }, { INP0,INP1,INP2,1.0 }, NULL, "DISCRETE_LOGIC_NAND3" }, +#define DISCRETE_LOGIC_NAND4(NODE,INP0,INP1,INP2,INP3) { NODE, DST_LOGIC_NAND , 4, { INP0,INP1,INP2,INP3 }, { INP0,INP1,INP2,INP3 }, NULL, ")DISCRETE_LOGIC_NAND4" }, +#define DISCRETE_LOGIC_OR(NODE,INP0,INP1) { NODE, DST_LOGIC_OR , 4, { INP0,INP1,NODE_NC,NODE_NC }, { INP0,INP1,0.0,0.0 }, NULL, "DISCRETE_LOGIC_OR" }, +#define DISCRETE_LOGIC_OR3(NODE,INP0,INP1,INP2) { NODE, DST_LOGIC_OR , 4, { INP0,INP1,INP2,NODE_NC }, { INP0,INP1,INP2,0.0 }, NULL, "DISCRETE_LOGIC_OR3" }, +#define DISCRETE_LOGIC_OR4(NODE,INP0,INP1,INP2,INP3) { NODE, DST_LOGIC_OR , 4, { INP0,INP1,INP2,INP3 }, { INP0,INP1,INP2,INP3 }, NULL, "DISCRETE_LOGIC_OR4" }, +#define DISCRETE_LOGIC_NOR(NODE,INP0,INP1) { NODE, DST_LOGIC_NOR , 4, { INP0,INP1,NODE_NC,NODE_NC }, { INP0,INP1,0.0,0.0 }, NULL, "DISCRETE_LOGIC_NOR" }, +#define DISCRETE_LOGIC_NOR3(NODE,INP0,INP1,INP2) { NODE, DST_LOGIC_NOR , 4, { INP0,INP1,INP2,NODE_NC }, { INP0,INP1,INP2,0.0 }, NULL, "DISCRETE_LOGIC_NOR3" }, +#define DISCRETE_LOGIC_NOR4(NODE,INP0,INP1,INP2,INP3) { NODE, DST_LOGIC_NOR , 4, { INP0,INP1,INP2,INP3 }, { INP0,INP1,INP2,INP3 }, NULL, "DISCRETE_LOGIC_NOR4" }, +#define DISCRETE_LOGIC_XOR(NODE,INP0,INP1) { NODE, DST_LOGIC_XOR , 2, { INP0,INP1 }, { INP0,INP1 }, NULL, "DISCRETE_LOGIC_XOR" }, +#define DISCRETE_LOGIC_NXOR(NODE,INP0,INP1) { NODE, DST_LOGIC_NXOR , 2, { INP0,INP1 }, { INP0,INP1 }, NULL, "DISCRETE_LOGIC_NXOR" }, +#define DISCRETE_LOGIC_DFLIPFLOP(NODE,RESET,SET,CLK,INP) { NODE, DST_LOGIC_DFF , 4, { RESET,SET,CLK,INP }, { RESET,SET,CLK,INP }, NULL, "DISCRETE_LOGIC_DFLIPFLOP" }, +#define DISCRETE_LOGIC_JKFLIPFLOP(NODE,RESET,SET,CLK,J,K) { NODE, DST_LOGIC_JKFF , 5, { RESET,SET,CLK,J,K }, { RESET,SET,CLK,J,K }, NULL, "DISCRETE_LOGIC_JKFLIPFLOP" }, #define DISCRETE_LOOKUP_TABLE(NODE,ENAB,ADDR,SIZE,TABLE) { NODE, DST_LOOKUP_TABLE, 3, { ENAB,ADDR,NODE_NC }, { ENAB,ADDR,SIZE }, TABLE, "DISCRETE_LOOKUP_TABLE" }, #define DISCRETE_MULTIPLEX2(NODE,ENAB,ADDR,INP0,INP1) { NODE, DST_MULTIPLEX , 4, { ENAB,ADDR,INP0,INP1 }, { ENAB,ADDR,INP0,INP1 }, NULL, "DISCRETE_MULTIPLEX2" }, #define DISCRETE_MULTIPLEX4(NODE,ENAB,ADDR,INP0,INP1,INP2,INP3) { NODE, DST_MULTIPLEX , 6, { ENAB,ADDR,INP0,INP1,INP2,INP3 }, { ENAB,ADDR,INP0,INP1,INP2,INP3 }, NULL, "DISCRETE_MULTIPLEX4" }, diff --git a/src/mame/audio/8080bw.c b/src/mame/audio/8080bw.c index 381972c80fa..3f75b10fdbc 100644 --- a/src/mame/audio/8080bw.c +++ b/src/mame/audio/8080bw.c @@ -503,8 +503,8 @@ DISCRETE_SOUND_START(polaris) DISCRETE_TRANSFORM2(NODE_43, NODE_41, 16, "01&!") // IC 5F, pin 8 DISCRETE_ONESHOT(NODE_44, NODE_43, 1, 0.0015, DISC_ONESHOT_REDGE | DISC_ONESHOT_NORETRIG | DISC_OUT_ACTIVE_HIGH) - DISCRETE_LOGIC_OR(NODE_45, 1, NODE_42, POLARIS_SX3_EN) - DISCRETE_LOGIC_DFLIPFLOP(NODE_46, 1, 1, 1, NODE_40, NODE_45) + DISCRETE_LOGIC_OR(NODE_45, NODE_42, POLARIS_SX3_EN) + DISCRETE_LOGIC_DFLIPFLOP(NODE_46, 1, 1, NODE_40, NODE_45) DISCRETE_OP_AMP_VCO1(NODE_47, 1, POLARIS_NOISE_LO_FILT, &polaris_sonar_vco_info) DISCRETE_OP_AMP_TRIG_VCA(POLARIS_SONARSND, NODE_45, NODE_46, 0, NODE_47, 0, &polaris_sonar_tvca_info) diff --git a/src/mame/audio/bzone.c b/src/mame/audio/bzone.c index b410283f530..ac87fe58383 100644 --- a/src/mame/audio/bzone.c +++ b/src/mame/audio/bzone.c @@ -207,7 +207,7 @@ static DISCRETE_SOUND_START(bzone) DISCRETE_BITS_DECODE(NODE_32, NODE_SUB(30,1), 11, 14, 1) /* to NAND LS20, J4 */ /* 11-14 */ - DISCRETE_LOGIC_NAND4(NODE_33,1,NODE_SUB(32,0),NODE_SUB(32,1),NODE_SUB(32,2),NODE_SUB(32,3)) + DISCRETE_LOGIC_NAND4(NODE_33,NODE_SUB(32,0),NODE_SUB(32,1),NODE_SUB(32,2),NODE_SUB(32,3)) /* divide by 2 */ DISCRETE_COUNTER(NODE_34, 1, 0, NODE_33, 1, DISC_COUNT_UP, 0, DISC_CLK_ON_R_EDGE) diff --git a/src/mame/audio/canyon.c b/src/mame/audio/canyon.c index 5be95aac64a..f2cbfdb18d6 100644 --- a/src/mame/audio/canyon.c +++ b/src/mame/audio/canyon.c @@ -172,7 +172,7 @@ DISCRETE_SOUND_START(canyon) /* Output is binary weighted with 4 bits of */ /* crash volume. */ /************************************************/ - DISCRETE_LOGIC_OR(NODE_60, 1, CANYON_ATTRACT1_EN, CANYON_ATTRACT2_EN) + DISCRETE_LOGIC_OR(NODE_60, CANYON_ATTRACT1_EN, CANYON_ATTRACT2_EN) DISCRETE_LFSR_NOISE(CANYON_NOISE, NODE_60, NODE_60, 15750.0/4, 1.0, 0, 0, &canyon_lfsr) DISCRETE_MULTIPLY(NODE_61, CANYON_NOISE, CANYON_EXPLODE_DATA) diff --git a/src/mame/audio/dkong.c b/src/mame/audio/dkong.c index 457bfb91171..209a73f281e 100644 --- a/src/mame/audio/dkong.c +++ b/src/mame/audio/dkong.c @@ -940,13 +940,13 @@ static DISCRETE_SOUND_START(dkongjr) DISCRETE_RCFILTER(NODE_112, 1, NODE_111, JR_R10, JR_C17) DISCRETE_74LS624(NODE_113, 1, NODE_112, DK_SUP_V, JR_C18, DISC_LS624_OUT_ENERGY) - DISCRETE_LOGIC_XOR(NODE_115, 1, NODE_105, NODE_106) + DISCRETE_LOGIC_XOR(NODE_115, NODE_105, NODE_106) DISCRETE_TRANSFORM2(NODE_116, NODE_107, TTL_HIGH, "0!1*") DISCRETE_RCFILTER(NODE_117, 1, NODE_116, JR_R11, JR_C16) DISCRETE_74LS624(NODE_118, 1, NODE_117, DK_SUP_V, JR_C19, DISC_LS624_OUT_COUNT_F) - DISCRETE_LOGIC_NAND(NODE_120, 1, NODE_115, NODE_110) + DISCRETE_LOGIC_NAND(NODE_120, NODE_115, NODE_110) DISCRETE_MULTIPLY(DS_OUT_SOUND0, NODE_120, TTL_HIGH) /************************************************/ diff --git a/src/mame/audio/firetrk.c b/src/mame/audio/firetrk.c index c75b680f6b8..f01016f8279 100644 --- a/src/mame/audio/firetrk.c +++ b/src/mame/audio/firetrk.c @@ -427,7 +427,7 @@ DISCRETE_SOUND_START(superbug) NODE_22, DISC_CLK_ON_F_EDGE) // from IC A6, pin 3 DISCRETE_TRANSFORM2(NODE_24, NODE_23, 0x04, "01&") // IC A7, pin 8-QD DISCRETE_TRANSFORM2(NODE_25, NODE_23, 0x01, "01&") // IC A7, pin 11-QB - DISCRETE_LOGIC_XOR(NODE_26, 1, NODE_24, NODE_25) // Gate A9, pin 8 + DISCRETE_LOGIC_XOR(NODE_26, NODE_24, NODE_25) // Gate A9, pin 8 DISCRETE_COUNTER(NODE_27, 1, SUPERBUG_ATTRACT_EN, // IC A7, pin 12-QA NODE_26, // from IC A9, pin 8 1, 1, 0, DISC_CLK_ON_F_EDGE) @@ -611,7 +611,7 @@ DISCRETE_SOUND_START(montecar) NODE_22, DISC_CLK_ON_F_EDGE) // from IC C9, pin 9 DISCRETE_TRANSFORM2(NODE_24, NODE_23, 0x04, "01&") // IC B/C9, pin 8-QD DISCRETE_TRANSFORM2(NODE_25, NODE_23, 0x01, "01&") // IC B/C9, pin 11-QB - DISCRETE_LOGIC_XOR(NODE_26, 1, NODE_24, NODE_25) // Gate A9, pin 11 + DISCRETE_LOGIC_XOR(NODE_26, NODE_24, NODE_25) // Gate A9, pin 11 DISCRETE_COUNTER(NODE_27, 1, MONTECAR_ATTRACT_EN, // IC B/C9, pin 12-QA NODE_26, // from IC A9, pin 11 1, 1, 0, DISC_CLK_ON_F_EDGE) @@ -646,7 +646,7 @@ DISCRETE_SOUND_START(montecar) NODE_42, DISC_CLK_ON_F_EDGE) // from IC C9, pin 5 DISCRETE_TRANSFORM2(NODE_44, NODE_43, 0x04, "01&") // IC A/B9, pin 8-QD DISCRETE_TRANSFORM2(NODE_45, NODE_43, 0x01, "01&") // IC A/B9, pin 11-QB - DISCRETE_LOGIC_XOR(NODE_46, 1, NODE_44, NODE_45) // Gate A9, pin 6 + DISCRETE_LOGIC_XOR(NODE_46, NODE_44, NODE_45) // Gate A9, pin 6 DISCRETE_COUNTER(NODE_47, 1, MONTECAR_ATTRACT_EN, // IC A/B9, pin 12-QA NODE_46, // from IC A9, pin 6 1, 1, 0, DISC_CLK_ON_F_EDGE) diff --git a/src/mame/audio/galaxian.c b/src/mame/audio/galaxian.c index 2b83720ef87..e5d3551b2fb 100644 --- a/src/mame/audio/galaxian.c +++ b/src/mame/audio/galaxian.c @@ -324,7 +324,7 @@ static DISCRETE_SOUND_START(galaxian) */ DISCRETE_LFSR_NOISE(NODE_150, 1, 1, RNG_RATE/100, 1.0, 0, 0.5, &galaxian_lfsr) DISCRETE_SQUAREWFIX(NODE_151,1,60*264/2,1.0,50,0.5,0) /* 2V signal */ - DISCRETE_LOGIC_DFLIPFLOP(NODE_152,1,1,1,NODE_151,NODE_150) + DISCRETE_LOGIC_DFLIPFLOP(NODE_152,1,1,NODE_151,NODE_150) /* Not 100% correct - switching causes high impedance input for node_157 diff --git a/src/mame/audio/hitme.c b/src/mame/audio/hitme.c index d4de0734123..a73aeaca817 100644 --- a/src/mame/audio/hitme.c +++ b/src/mame/audio/hitme.c @@ -64,7 +64,7 @@ DISCRETE_SOUND_START(hitme) /* This flipflop represents the latch at 1L. It is clocked when OUT1 is written and latches * the value from the processor. When the downcounter above rolls over, it clears the latch. */ - DISCRETE_LOGIC_DFLIPFLOP(NODE_22,1,NODE_21,1,HITME_OUT1,HITME_ENABLE_VAL) + DISCRETE_LOGIC_DFLIPFLOP(NODE_22,NODE_21,1,HITME_OUT1,HITME_ENABLE_VAL) /* The output of the latch goes through a series of various capacitors in parallel. */ DISCRETE_COMP_ADDER(NODE_23,NODE_22,&desc_hitme_adder) diff --git a/src/mame/audio/mario.c b/src/mame/audio/mario.c index 624c17fffaa..5c34c5e68cc 100644 --- a/src/mame/audio/mario.c +++ b/src/mame/audio/mario.c @@ -308,12 +308,12 @@ static DISCRETE_SOUND_START(mario) DISCRETE_RCFILTER(NODE_112, 1, NODE_111, MR_R65, MR_C44) DISCRETE_74LS624(NODE_113, 1, NODE_112, VSS, MR_C40, DISC_LS624_OUT_LOGIC) - DISCRETE_LOGIC_XOR(NODE_115, 1, NODE_102, NODE_113) + DISCRETE_LOGIC_XOR(NODE_115, NODE_102, NODE_113) DISCRETE_RCFILTER(NODE_117, 1, NODE_104, MR_R64, MR_C43) DISCRETE_74LS624(NODE_118, 1, NODE_117, VSS, MR_C39, DISC_LS624_OUT_COUNT_F) - DISCRETE_LOGIC_AND(NODE_120, 1, NODE_115, NODE_110) + DISCRETE_LOGIC_AND(NODE_120, NODE_115, NODE_110) DISCRETE_MULTIPLY(NODE_121, NODE_120, TTL_HIGH * MR_MIXER_RPAR / MR_R41) DISCRETE_RCFILTER(DS_OUT_SOUND7, 1, NODE_121, MR_MIXER_RPAR, MR_C31) diff --git a/src/mame/audio/mw8080bw.c b/src/mame/audio/mw8080bw.c index 42277358861..9c2b5ab26f9 100644 --- a/src/mame/audio/mw8080bw.c +++ b/src/mame/audio/mw8080bw.c @@ -289,10 +289,10 @@ static DISCRETE_SOUND_START(tornbase) DISCRETE_SQUAREWFIX(TORNBASE_SQUAREW_120, 1, 120, 1.0, 50.0, 1.0/2, 0) /* pin V */ /* 7403 O/C NAND gate at G6. 3 of the 4 gates used with their outputs tied together */ - DISCRETE_LOGIC_NAND(TORNBASE_TONE_240_SND, 1, TORNBASE_SQUAREW_240, TORNBASE_TONE_240_EN) /* pins 4,5,6 */ - DISCRETE_LOGIC_NAND(TORNBASE_TONE_960_SND, 1, TORNBASE_SQUAREW_960, TORNBASE_TONE_960_EN) /* pins 2,1,3 */ - DISCRETE_LOGIC_NAND(TORNBASE_TONE_120_SND, 1, TORNBASE_SQUAREW_120, TORNBASE_TONE_120_EN) /* pins 13,12,11 */ - DISCRETE_LOGIC_AND3(TORNBASE_TONE_SND, 1, TORNBASE_TONE_240_SND, TORNBASE_TONE_960_SND, TORNBASE_TONE_120_SND) + DISCRETE_LOGIC_NAND(TORNBASE_TONE_240_SND, TORNBASE_SQUAREW_240, TORNBASE_TONE_240_EN) /* pins 4,5,6 */ + DISCRETE_LOGIC_NAND(TORNBASE_TONE_960_SND, TORNBASE_SQUAREW_960, TORNBASE_TONE_960_EN) /* pins 2,1,3 */ + DISCRETE_LOGIC_NAND(TORNBASE_TONE_120_SND, TORNBASE_SQUAREW_120, TORNBASE_TONE_120_EN) /* pins 13,12,11 */ + DISCRETE_LOGIC_AND3(TORNBASE_TONE_SND, TORNBASE_TONE_240_SND, TORNBASE_TONE_960_SND, TORNBASE_TONE_120_SND) /* 47K resistor (R601) and 0.047uF capacitor (C601) There is also a 50K pot acting as a volume control, but we output at @@ -485,7 +485,6 @@ static DISCRETE_SOUND_START(maze) CAP_U(100), /* C204 */ &maze_555_F2) DISCRETE_LOGIC_JKFLIPFLOP(MAZE_AUDIO_ENABLE,/* IC F1, pin 5 */ - 1, /* ENAB */ MAZE_COIN, /* RESET */ 1, /* SET */ MAZE_GAME_OVER, /* CLK */ @@ -494,14 +493,12 @@ static DISCRETE_SOUND_START(maze) DISCRETE_LOGIC_INVERT(MAZE_TONE_ENABLE, /* IC F1, pin 6 */ MAZE_AUDIO_ENABLE) /* IN0 */ DISCRETE_LOGIC_AND3(NODE_21, - 1, /* ENAB */ MAZE_JOYSTICK_IN_USE, /* INP0 */ MAZE_TONE_ENABLE, /* INP1 */ MAZE_TONE_TIMING) /* INP2 */ /* The following circuits use the control info to generate a tone. */ DISCRETE_LOGIC_JKFLIPFLOP(MAZE_PLAYER_SEL, /* IC C1, pin 3 */ - 1, /* ENAB */ 1, /* RESET */ 1, /* SET */ MAZE_TONE_TIMING, /* CLK */ @@ -2691,7 +2688,6 @@ static DISCRETE_SOUND_START(spcenctr) CAP_U(1), /* C713 */ &spcenctr_555_bonus) DISCRETE_LOGIC_AND3(NODE_82, /* IC C-D, pin 6 */ - 1, /* ENAB */ NODE_80, /* INP0 */ NODE_81, /* INP1 */ SPCENCTR_BONUS_EN) /* INP2 */ @@ -3524,7 +3520,6 @@ static const discrete_mixer_desc invaders_mixer = 1.0/2, /* BIAS */ \ 0) /* PHASE */ \ DISCRETE_LOGIC_AND3(INVADERS_NODE(42, _board), /* IC F3, pin 12 */ \ - 1, /* ENAB */ \ INVADERS_NODE(INVADERS_BONUS_MISSLE_BASE_EN, _board),/* INP0 */ \ INVADERS_NODE(41, _board), /* INP1 */ \ INVADERS_NODE(40, _board) ) /* INP2 */ \ diff --git a/src/mame/audio/poolshrk.c b/src/mame/audio/poolshrk.c index 2d7ba4e4588..780ef332ed5 100644 --- a/src/mame/audio/poolshrk.c +++ b/src/mame/audio/poolshrk.c @@ -131,7 +131,7 @@ DISCRETE_SOUND_START(poolshrk) /* not at TC, so the click is counted once. */ /* This should also happen on the original PCB. */ /************************************************/ - DISCRETE_LOGIC_OR(NODE_40 ,1 ,POOLSHRK_CLICK_EN , NODE_39) // gate K9, pin 11 + DISCRETE_LOGIC_OR(NODE_40, POOLSHRK_CLICK_EN , NODE_39) // gate K9, pin 11 DISCRETE_COUNTER(NODE_41, // Counter J9 (9316 is a 74161) NODE_42, // Clock enabled by F8, pin 1 NODE_40, // Reset/triggered by K9, pin 11 diff --git a/src/mame/audio/sprint2.c b/src/mame/audio/sprint2.c index 9f0ddb366c1..f413c45e005 100644 --- a/src/mame/audio/sprint2.c +++ b/src/mame/audio/sprint2.c @@ -144,7 +144,7 @@ DISCRETE_SOUND_START(sprint2) /* Mask the bits and XOR for clock input */ DISCRETE_TRANSFORM2(NODE_24, NODE_23, 1, "01&") DISCRETE_TRANSFORM2(NODE_25, NODE_23, 4, "01&") - DISCRETE_LOGIC_XOR(NODE_26, 1, NODE_24, NODE_25) + DISCRETE_LOGIC_XOR(NODE_26, NODE_24, NODE_25) /* QA of 7492 */ DISCRETE_COUNTER(NODE_27, 1, SPRINT2_ATTRACT_EN, NODE_26, 1, 1, 0, DISC_CLK_ON_F_EDGE) @@ -182,7 +182,7 @@ DISCRETE_SOUND_START(sprint2) /* Mask the bits and XOR for clock input */ DISCRETE_TRANSFORM2(NODE_44, NODE_43, 1, "01&") DISCRETE_TRANSFORM2(NODE_45, NODE_43, 4, "01&") - DISCRETE_LOGIC_XOR(NODE_46, 1, NODE_44, NODE_45) + DISCRETE_LOGIC_XOR(NODE_46, NODE_44, NODE_45) /* QA of 7492 */ DISCRETE_COUNTER(NODE_47, 1, SPRINT2_ATTRACT_EN, NODE_46, 1, 1, 0, DISC_CLK_ON_F_EDGE) @@ -267,7 +267,7 @@ DISCRETE_SOUND_START(sprint1) /* Mask the bits and XOR for clock input */ DISCRETE_TRANSFORM2(NODE_24, NODE_23, 1, "01&") DISCRETE_TRANSFORM2(NODE_25, NODE_23, 4, "01&") - DISCRETE_LOGIC_XOR(NODE_26, 1, NODE_24, NODE_25) + DISCRETE_LOGIC_XOR(NODE_26, NODE_24, NODE_25) /* QA of 7492 */ DISCRETE_COUNTER(NODE_27, 1, SPRINT2_ATTRACT_EN, NODE_26, 1, 1, 0, DISC_CLK_ON_F_EDGE) diff --git a/src/mame/audio/subs.c b/src/mame/audio/subs.c index de34f57ede1..e2e4ed76423 100644 --- a/src/mame/audio/subs.c +++ b/src/mame/audio/subs.c @@ -125,12 +125,12 @@ DISCRETE_SOUND_START(subs) /************************************************/ DISCRETE_RCDISC2(NODE_40, SUBS_SONAR1_EN, SUBS_SONAR1_EN, 680000.0, SUBS_SONAR1_EN, 1000.0, 1e-6) /* Decay envelope */ DISCRETE_ADDER2(NODE_41, 1, NODE_40, 800) - DISCRETE_LOGIC_AND(NODE_42, 1, SUBS_SONAR1_EN, SUBS_NOISE) + DISCRETE_LOGIC_AND(NODE_42, SUBS_SONAR1_EN, SUBS_NOISE) DISCRETE_TRIANGLEWAVE(SUBS_SONAR1_SND, NODE_42, NODE_41, 320.8, 0.0, 0) DISCRETE_RCDISC2(NODE_50, SUBS_SONAR2_EN, SUBS_SONAR2_EN, 18600.0, SUBS_SONAR2_EN, 20.0, 4.7e-6) /* Decay envelope */ DISCRETE_ADDER2(NODE_51, 1, NODE_50, 800) - DISCRETE_LOGIC_AND(NODE_52, 1, SUBS_SONAR2_EN, SUBS_NOISE) + DISCRETE_LOGIC_AND(NODE_52, SUBS_SONAR2_EN, SUBS_NOISE) DISCRETE_TRIANGLEWAVE(SUBS_SONAR2_SND, NODE_52, NODE_51, 320.8, 0.0, 0) /************************************************/ diff --git a/src/mame/audio/triplhnt.c b/src/mame/audio/triplhnt.c index 2b7659e0b17..e0eda3307d9 100644 --- a/src/mame/audio/triplhnt.c +++ b/src/mame/audio/triplhnt.c @@ -149,8 +149,8 @@ DISCRETE_SOUND_START(triplhnt) 5, 1, 0, DISC_CLK_ON_R_EDGE) // /6 counter on rising edge DISCRETE_TRANSFORM2(NODE_24, NODE_23, 2, "01>") // IC B6, pin 8 DISCRETE_LOGIC_INVERT(NODE_25, NODE_22) // IC D9, pin 3 - DISCRETE_LOGIC_NAND(NODE_26, 1, NODE_25, TRIPLHNT_NOISE) // IC D9, pin 11 - DISCRETE_LOGIC_XOR(NODE_27, 1, NODE_24, NODE_26) // IC B8, pin 6 + DISCRETE_LOGIC_NAND(NODE_26, NODE_25, TRIPLHNT_NOISE) // IC D9, pin 11 + DISCRETE_LOGIC_XOR(NODE_27, NODE_24, NODE_26) // IC B8, pin 6 DISCRETE_COUNTER(NODE_28, 1, TRIPLHNT_BEAR_EN, // IC B6, pin 12 NODE_27, // from IC B8, pin 6 1, 1, 0, DISC_CLK_ON_R_EDGE) // /2 counter on rising edge