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https://github.com/holub/mame
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more of the same (nw)
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@ -59,6 +59,7 @@ static ADDRESS_MAP_START( coldfire_regs_map, AS_0, 32, mcf5206e_peripheral_devic
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AM_RANGE(0x1e4, 0x1e7) AM_READWRITE8(MFDR_r, MFDR_w, 0xffffffff)
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AM_RANGE(0x1e4, 0x1e7) AM_READWRITE8(MFDR_r, MFDR_w, 0xffffffff)
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AM_RANGE(0x1e8, 0x1eb) AM_READWRITE8(MBCR_r, MBCR_w, 0xffffffff)
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AM_RANGE(0x1e8, 0x1eb) AM_READWRITE8(MBCR_r, MBCR_w, 0xffffffff)
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AM_RANGE(0x1ec, 0x1ef) AM_READWRITE8(MBSR_r, MBSR_w, 0xffffffff)
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AM_RANGE(0x1ec, 0x1ef) AM_READWRITE8(MBSR_r, MBSR_w, 0xffffffff)
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AM_RANGE(0x1f0, 0x1f3) AM_READWRITE8(MBDR_r, MBDR_w, 0xffffffff)
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ADDRESS_MAP_END
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ADDRESS_MAP_END
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@ -528,7 +529,7 @@ WRITE8_MEMBER( mcf5206e_peripheral_device::MFDR_w)
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READ8_MEMBER( mcf5206e_peripheral_device::MBSR_r)
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READ8_MEMBER( mcf5206e_peripheral_device::MBSR_r)
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{
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{
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static int hack = 0x00;
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int hack = 0x00;
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switch (offset)
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switch (offset)
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{
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{
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@ -536,7 +537,7 @@ READ8_MEMBER( mcf5206e_peripheral_device::MBSR_r)
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{
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{
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hack ^= (machine().rand()&0xff);
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hack ^= (machine().rand()&0xff);
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debuglog("%s: MBSR_r\n", this->machine().describe_context());
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debuglog("%s: MBSR_r\n", this->machine().describe_context());
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return m_MBSR | hack; // will loop on this after a while
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return m_MBSR ^ hack; // will loop on this after a while
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}
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}
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case 1:
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case 1:
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case 2:
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case 2:
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@ -567,6 +568,48 @@ WRITE8_MEMBER( mcf5206e_peripheral_device::MBSR_w)
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READ8_MEMBER( mcf5206e_peripheral_device::MBDR_r)
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{
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int hack = 0x00;
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switch (offset)
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{
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case 0:
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{
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hack ^= (machine().rand()&0xff);
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debuglog("%s: MBDR_r\n", this->machine().describe_context());
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return m_MBDR ^ hack;
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}
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case 1:
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case 2:
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case 3:
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debuglog("%s: invalid MBDR_r %d\n", this->machine().describe_context(), offset);
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return 0;
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}
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return 0;
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}
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WRITE8_MEMBER( mcf5206e_peripheral_device::MBDR_w)
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{
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switch (offset)
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{
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case 0:
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m_MBDR = data;
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debuglog("%s: MBDR_w %02x\n", this->machine().describe_context(), data);
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break;
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case 1:
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case 2:
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case 3:
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debuglog("%s: invalid MBDR_w %d, %02x\n", this->machine().describe_context(), offset, data);
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break;
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}
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}
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READ16_MEMBER( mcf5206e_peripheral_device::IMR_r)
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READ16_MEMBER( mcf5206e_peripheral_device::IMR_r)
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{
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{
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switch (offset)
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switch (offset)
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@ -614,7 +657,7 @@ TIMER_CALLBACK_MEMBER(mcf5206e_peripheral_device::timer1_callback)
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// technically we should do the vector check in the IRQ callback as well as various checks based on the IRQ masks before asserting the interrupt
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// technically we should do the vector check in the IRQ callback as well as various checks based on the IRQ masks before asserting the interrupt
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if (ICR & 0x80) // AVEC
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if (ICR & 0x80) // AVEC
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{
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{
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m_cpu->set_input_line((ICR&0x1c)>>2, HOLD_LINE);
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if (!(m_IMR & 0x0200)) m_cpu->set_input_line((ICR&0x1c)>>2, HOLD_LINE);
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}
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}
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debuglog("timer1_callback\n");
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debuglog("timer1_callback\n");
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@ -903,8 +946,10 @@ void mcf5206e_peripheral_device::init_regs(bool first_init)
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m_IMR = 0x3FFE;
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m_IMR = 0x3FFE;
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m_MFDR = 0x00;
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m_MBCR = 0x00;
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m_MBCR = 0x00;
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m_MBSR = 0x00;
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m_MBSR = 0x00;
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m_MBDR = 0x00;
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}
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}
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/*
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/*
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@ -1025,7 +1070,7 @@ $1E0 MADR 8 M-Bus Address Register
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$1E4*- MFDR 8 M-Bus Frequency Divider Register 00 R/W
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$1E4*- MFDR 8 M-Bus Frequency Divider Register 00 R/W
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$1E8*- MBCR 8 M-Bus Control Register 00 R/W
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$1E8*- MBCR 8 M-Bus Control Register 00 R/W
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$1EC*- MBSR 8 M-Bus Status Register 00 R/W
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$1EC*- MBSR 8 M-Bus Status Register 00 R/W
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$1F0 MBDR 8 M-Bus Data I/O Register 00 R/W
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$1F0*- MBDR 8 M-Bus Data I/O Register 00 R/W
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------------ DMA Controller -----------
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------------ DMA Controller -----------
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$200 DMASAR0 32 Source Address Register 0 00 R/W
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$200 DMASAR0 32 Source Address Register 0 00 R/W
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$204 DMADAR0 32 Destination Address Register 0 00 R/W
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$204 DMADAR0 32 Destination Address Register 0 00 R/W
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@ -151,6 +151,8 @@ public:
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DECLARE_WRITE8_MEMBER( MBSR_w );
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DECLARE_WRITE8_MEMBER( MBSR_w );
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DECLARE_READ8_MEMBER( MFDR_r );
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DECLARE_READ8_MEMBER( MFDR_r );
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DECLARE_WRITE8_MEMBER( MFDR_w );
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DECLARE_WRITE8_MEMBER( MFDR_w );
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DECLARE_READ8_MEMBER( MBDR_r );
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DECLARE_WRITE8_MEMBER( MBDR_w );
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@ -197,6 +199,7 @@ private:
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UINT8 m_MBCR;
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UINT8 m_MBCR;
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UINT8 m_MBSR;
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UINT8 m_MBSR;
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UINT8 m_MFDR;
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UINT8 m_MFDR;
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UINT8 m_MBDR;
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UINT32 m_coldfire_regs[0x400/4];
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UINT32 m_coldfire_regs[0x400/4];
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